专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

WO2011133404A1 PROGRAMMING NON-VOLATILE STORAGE INCLUDNG REDUCING IMPACT FROM OTHER MEMORY CELLS 审中-公开
标题翻译：编程非易失性存储包括减少其他记忆细胞的影响
公开(公告)号：WO2011133404A1
公开(公告)日：2011-10-27
申请号：PCT/US2011/032575
申请日：2011-04-14
申请人： SANDISK CORPORATION , DONG, Yingda , LEE, Shih-Chung , OOWADA, Ken
发明人： DONG, Yingda , LEE, Shih-Chung , OOWADA, Ken
IPC分类号： G11C16/10 , G11C16/34 , G11C11/56
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/3459 , G11C2211/5621 , G11C2211/5622
摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells using a programming signal that increases over time. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells using a programming signal that has been lowered in magnitude in response to the first trigger. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells with the programming signal being raised in response to the second trigger. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
摘要翻译：提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。存储单元分为两个或更多个组。在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。在第一触发之前，使用随时间增加的编程信号将第一组存储器单元与第二组存储器单元一起编程。在第一触发之后和在第二触发之前，使用已经响应于第一触发而被大幅度降低的编程信号，将第一组存储器单元与第二组存储器单元分开编程。在第二触发之后，第一组存储器单元与第二组存储器单元一起编程，响应于第二触发而使编程信号升高。在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

22. 发明申请

WO2011066228A1 PROGRAMMING MEMORY WITH SENSING-BASED BIT LINE COMPENSATION TO REDUCE CHANNEL -TO-FLOATING GATE COUPLING 审中-公开
标题翻译：具有基于感测的位线补偿的编程存储器，以减少通道到浮动门的耦合
公开(公告)号：WO2011066228A1
公开(公告)日：2011-06-03
申请号：PCT/US2010/057645
申请日：2010-11-22
申请人： SANDISK CORPORATION , LI, Yan
发明人： LI, Yan
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C16/3427
摘要： During programming of storage elements, channel-to-floating gate coupling effects are compensated to avoid increased programming speed and threshold voltage distribution widening. In connection with a programming iteration, unselected bit lines voltages are stepped up to induce coupling to selected bit lines, and the amount of coupling which is experienced by the selected bit lines is sensed. When a program pulse is applied, voltages of the selected bit lines are set based on the amount of coupling. The bit line voltage is set higher when more coupling is sensed. The amount of coupling experience by a given selected bit line is a function of its proximity to unselected bit lines. One or more coupling thresholds can be used to indicate that a given selected bit line has one or two adjacent unselected bit lines, respectively.
摘要翻译：在存储元件的编程期间，补偿了沟道到浮置栅极耦合效应，以避免增加的编程速度和阈值电压分布加宽。结合编程迭代，非选择的位线电压被升高以感应到选定位线的耦合，并且感测所选位线所经历的耦合量。当施加编程脉冲时，基于耦合量设置所选位线的电压。当检测到更多的耦合时，位线电压被设置得更高。给定选定位线的耦合体验量是其与未选定位线的接近度的函数。可以使用一个或多个耦合阈值来指示给定的所选位线分别具有一个或两个相邻的未选位线。

23. 发明申请

WO2011060078A1 DATA STATE-DEPENDENT CHANNEL BOOSTING TO REDUCE CHANNEL-TO-FLOATING GATE COUPLING IN MEMORY 审中-公开
标题翻译：数据状态相关通道提升降低存储器中的通道到浮动门耦合
公开(公告)号：WO2011060078A1
公开(公告)日：2011-05-19
申请号：PCT/US2010/056248
申请日：2010-11-10
申请人： SANDISK CORPORATION , DUTTA, Deepanshu , LUTZE, Jeffrey, W. , SHAH, Grishma
发明人： DUTTA, Deepanshu , LUTZE, Jeffrey, W. , SHAH, Grishma
IPC分类号： G11C16/10 , G11C16/34 , G11C16/04 , G11C16/12
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3427
摘要： In a programming operation, selected storage elements on a selected word line are programmed while unselected storage elements on the selected word line are inhibited from programming by channel boosting. To provide a sufficient but not excessive level of boosting, the amount of boosting can be set based on a data state of the unselected storage element. A greater amount of boosting can be provided for a lower data state which represents a lower threshold voltage and hence is more vulnerable to program disturb. A common boosting scheme can be used for groups of multiple data states. The amount of boosting can be set by adjusting the timing and magnitude of voltages used for a channel pre-charge operation and for pass voltages which are applied to word lines. In one approach, stepped pass voltages on unselected word lines can be used to adjust boosting for channels with selected data states.
摘要翻译：在编程操作中，选择的字线上的所选择的存储元件被编程，同时通过通道增强来禁止所选字线上的未选择的存储元件的编程。为了提供足够但不是过高的升压水平，可以基于未选择的存储元件的数据状态来设定升压量。可以为代表较低阈值电压的较低数据状态提供更大量的升压，因此更易受编程干扰的影响。一个共同的升压方案可以用于多个数据状态的组。可以通过调整用于通道预充电操作的电压的时序和幅度以及施加到字线的通过电压来设置升压量。在一种方法中，可以使用未选择字线上的阶梯式通过电压来调整具有所选数据状态的通道的升压。

24. 发明申请

WO2010002942A1 METHOD AND APPARATUS FOR WRITE-SIDE INTERCELL INTERFERENCE MITIGATION IN FLASH MEMORIES 审中-公开
标题翻译：用于闪存中写入边缘干扰减轻的方法和装置
公开(公告)号：WO2010002942A1
公开(公告)日：2010-01-07
申请号：PCT/US2009/049327
申请日：2009-06-30
申请人： LSI CORPORATION , HARATSCH, Erich, F. , IVKOVIC, Milos , KRACHKOVSKY, Victor , MILADINOVIC, Nenad , VITYAEV, Andrei , YEN, Johnson
发明人： HARATSCH, Erich, F. , IVKOVIC, Milos , KRACHKOVSKY, Victor , MILADINOVIC, Nenad , VITYAEV, Andrei , YEN, Johnson
IPC分类号： G11C16/10 , G11C11/56
CPC分类号： G11C16/3427 , G06F11/1072 , G11C5/00 , G11C7/02 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3418
摘要： Methods and apparatus are provided for write-side intercell interference mitigation in flash memories. A flash memory device is written by obtaining program data to be written to at least one target cell in the flash memory; obtaining one or more bits of program data for at least one aggressor cell to be programmed later than the target cell: and precompensating for intercell interference for the target cell by generating precompensated program values. The aggressor cells comprise one or more cells adjacent to the target cell, such as adjacent cells in a same wordline as the target cell and/or cells in an upper or lower adjacent wordline to the target cell. The precompensated program values for the target cell are optionally provided to the flash memory.
摘要翻译：提供了用于闪存中的写侧小区间干扰减轻的方法和装置。通过获得写入到闪速存储器中的至少一个目标单元的程序数据来写入闪速存储器件; 为至少一个侵略者单元获得待编程的比目标小区晚的一个或多个程序数据位;并且通过产生预补偿的程序值来预补偿目标小区的小区间干扰。侵略者细胞包括与靶细胞相邻的一个或多个细胞，例如与靶细胞相同的字线中的相邻细胞和/或与靶细胞的上或下相邻字线中的细胞。目标单元的预补偿程序值可选地提供给闪存。

25. 发明申请

WO2010002941A1 METHODS AND APPARATUS FOR READ-SIDE INTERCELL INTERFERENCE MITIGATION IN FLASH MEMORIES 审中-公开
标题翻译：闪存中读取边界干扰减轻的方法和装置
公开(公告)号：WO2010002941A1
公开(公告)日：2010-01-07
申请号：PCT/US2009/049326
申请日：2009-06-30
申请人： LSI CORPORATION , HARATSCH, Erich, F. , IVKOVIC, Milos , KRACHKOVSKY, Victor , MILADINOVIC, Nenad , VITYAEV, Andrei , YEN, Johnson
发明人： HARATSCH, Erich, F. , IVKOVIC, Milos , KRACHKOVSKY, Victor , MILADINOVIC, Nenad , VITYAEV, Andrei , YEN, Johnson
IPC分类号： G11C16/26 , G11C16/34 , G11C11/56
CPC分类号： G11C16/3427 , G06F11/1072 , G11C5/00 , G11C7/02 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3418
摘要： Methods and apparatus are provided for read-side intercell interference mitigation in flash memories, A flash memory device is read by obtaining a read value for at least one target cell; obtaining a value representing a voltage stored in at least one aggressor cell that was programmed after the target cell; determining intercell interference for the target cell from the at least one aggressor cell; and obtaining a new read value that compensates for the intercell interference by removing the determined intercell interference from the read value for the at least one target cell. The new read value can optionally be provided to a decoder. In an iterative implementation, one or more intercell interference mitigation parameters can be adjusted if a decoding error occurs.
摘要翻译：提供了用于闪速存储器中的读侧细胞间干扰减轻的方法和装置。通过获得至少一个目标单元的读取值来读取闪速存储器件; 获得代表在目标小区之后编程的至少一个攻击者小区中存储的电压的值; 从所述至少一个侵略者小区确定所述目标小区的小区间干扰; 以及通过从所述至少一个目标小区的读取值中去除所确定的小区间干扰来获得补偿小区间干扰的新的读取值。可以可选地将新的读取值提供给解码器。在迭代实现中，如果发生解码错误，则可以调整一个或多个小区间干扰减轻参数。

26. 发明申请

WO2009086198A1 CONTROLLING AC DISTURBANCE WHILE PROGRAMMING 审中-公开
标题翻译：控制交流干扰编程
公开(公告)号：WO2009086198A1
公开(公告)日：2009-07-09
申请号：PCT/US2008/087829
申请日：2008-12-19
申请人： SPANSION LLC , CHUNG, Sung-Yong , LIU, Zhizheng , MIZUGUCHI, Yugi , WANG, Xuguang Alan , HE, Yi , KWAN, Ming , HAMILTON, Darlene , LEE, Sung-chul , WANG, Guowei , LEONG, Nancy
发明人： CHUNG, Sung-Yong , LIU, Zhizheng , MIZUGUCHI, Yugi , WANG, Xuguang Alan , HE, Yi , KWAN, Ming , HAMILTON, Darlene , LEE, Sung-chul , WANG, Guowei , LEONG, Nancy
IPC分类号： G11C16/24 , G11C16/34
CPC分类号： G11C16/3418 , G11C16/0416 , G11C16/24 , G11C16/3427
摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory (102), such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array (104) to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells (402, 404). A pre-charge voltage can be applied to all bit lines in a block in the memory array (104), or to bit lines associated with a selected memory cell (402) and neighbor memory cells (404) adjacent to the selected memory cell (402) in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell (402). This can facilitate minimizing AC disturbances in the selected memory cell (402) during the AC operation.
摘要翻译：提供了一种可以在与存储器（102）相关联的AC操作（例如，程序，读取和/或擦除）期间最小化干扰的系统和方法。在AC操作期间，系统将存储器阵列（104）中的所有或所需的位线子集预充电到指定的电压，以有助于减少相邻小区（402,404）之间的AC干扰。可以将预充电电压施加到存储器阵列（104）中的块中的所有位线，或者施加到与所选存储器单元（104）相邻的所选存储器单元（402）和相邻存储器单元（404）相关联的位线 402）。该系统确保在选择存储单元（402）的同时或基本相同的时间点将源极和漏极电压电平设置为期望的电平。这可以有助于在AC操作期间最小化所选择的存储单元（402）中的AC干扰。

27. 发明申请

WO2009067448A1 M+N BIT PROGRAMMING AND M+L BIT READ FOR M BIT MEMORY CELLS 审中-公开
标题翻译： M + N位编程和M + L位读取M位存储器单元
公开(公告)号：WO2009067448A1
公开(公告)日：2009-05-28
申请号：PCT/US2008/083915
申请日：2008-11-18
申请人： MICRON TECHNOLOGY, INC. , SARIN, Vishal , HOEI, Jung-Sheng , ROOHPARVAR, Frankie, F.
发明人： SARIN, Vishal , HOEI, Jung-Sheng , ROOHPARVAR, Frankie, F.
IPC分类号： G11C16/04 , G11C16/10 , G11C16/12 , G11C16/26
CPC分类号： G11C16/0483 , G11C7/16 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C27/005 , G11C2211/5641
摘要： A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage resolution than required. In programming non-volatile memory cells, this allows a more accurate threshold voltage placement during programming and enables pre-compensation for program disturb, increasing the accuracy of any subsequent read or verify operation on the cell. In reading/sensing memory cells, the increased threshold voltage resolution allows more accurate interpretations of the programmed state of the memory cell and also enables more effective use of probabilistic data encoding techniques such as convolutional code, partial response maximum likelihood (PRML), low-density parity check (LDPC), Turbo, and Trellis modulation encoding and/or decoding, reducing the overall error rate of the memory.
摘要翻译：描述了存储器件和编程和/或读取过程，其以比所需的更高的阈值电压分辨率编程和/或读取存储器阵列中的单元。在编程非易失性存储器单元中，这允许在编程期间更准确的阈值电压放置，并且能够对程序干扰进行预补偿，从而提高单元上随后的任何读取或验证操作的准确性。在读/读存储器单元中，增加的阈值电压分辨率允许更准确地解释存储器单元的编程状态，并且还能够更有效地使用概率数据编码技术，例如卷积码，部分响应最大似然（PRML）密度奇偶校验（LDPC），Turbo和网格调制编码和/或解码，降低了存储器的总体错误率。

28. 发明申请

WO2009045400A1 METHOD AND APPARATUS FOR PROGRAMMING MEMORY CELL ARRAY 审中-公开
标题翻译：用于编程存储器细胞阵列的方法和装置
公开(公告)号：WO2009045400A1
公开(公告)日：2009-04-09
申请号：PCT/US2008/011315
申请日：2008-09-30
申请人： CYPRESS SEMICONDUCTOR CORPORATION , JENNE, Fredrick, B. , RATNAKUMAR, Cynthia
发明人： JENNE, Fredrick, B. , RATNAKUMAR, Cynthia
IPC分类号： G11C11/34
CPC分类号： G11C16/3418 , G11C16/0466 , G11C16/24 , G11C16/3427 , G11C16/349
摘要： Disclosed are a method and device for programming an array of memory cells.
摘要翻译：公开了一种用于对存储器单元阵列进行编程的方法和装置。

29. 发明申请

WO2009036194A1 METHODS TO PREVENT PROGRAM DISTURB IN NONVOLATILE MEMORY 审中-公开
标题翻译：防止非易失性存储器中程序干扰的方法
公开(公告)号：WO2009036194A1
公开(公告)日：2009-03-19
申请号：PCT/US2008/076050
申请日：2008-09-11
申请人： SCHILTRON CORPORATION , WALKER, Andrew, J.
发明人： WALKER, Andrew, J.
IPC分类号： G11C11/34
CPC分类号： G11C16/0408 , G11C16/10 , G11C16/3418 , G11C16/3427 , H01L29/42344
摘要： Methods are provided to be used individually or in any combination that reduce program disturb in a non-volatile memory consisting of dual-gate memory cells. These methods counteract the effect of a leakage current in reducing a boosted voltage in a non-selected dual-gate memory string. According to one approach, a voltage applied to the gate electrode of an access device of a dual-gate memory cell is increased during a programming event. According to a second approach, the gate electrodes of an access device of a dual-gate memory cell is applied a series of electrical pulses synchronously with programming the memory device of the dual-gate memory cell by a second series of electrical pulses. According to a third approach, multiple dual-gate select devices are provided between a string of dual-gate memory devices and either a source line or a bit line, or both.
摘要翻译：提供单独使用或以任何组合方式使用减少由双栅极存储器单元组成的非易失性存储器中的程序干扰的方法。这些方法抵消了泄漏电流在降低未选择的双栅极存储器串中的升压电压的作用。根据一种方法，在编程事件期间增加施加到双栅极存储器单元的存取装置的栅电极的电压。根据第二种方法，双栅极存储器单元的存取器件的栅极电极通过第二系列电脉冲与双栅极存储器单元的存储器件同步地施加一系列电脉冲。根据第三种方法，在一对双栅极存储器件与源极线或位线之间或两者之间提供多个双栅极选择器件。

30. 发明申请

WO2008027681A3 NON-VOLATILE MEMORY DEVICE AND METHOD HAVING BIT-STATE ASSIGNMENTS SELECTED TO MINIMIZE SIGNAL COUPLING 审中-公开
标题翻译：非易失性存储器装置和具有选择的最小化信号耦合的位状态分配的方法
公开(公告)号：WO2008027681A3
公开(公告)日：2008-12-04
申请号：PCT/US2007074867
申请日：2007-07-31
申请人： MICRON TECHNOLOGY INC , NAZARIAN HAGOP A
发明人： NAZARIAN HAGOP A
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/04 , G11C11/5628 , G11C16/0483 , G11C16/12 , G11C16/3418 , G11C16/3427 , G11C2211/5641 , G11C2211/5643 , G11C2211/5647
摘要： A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the cells in a row using a set of bit state assignments chosen by evaluating data that are to be written to the cells in the row. The control logic unit performs this evaluation by determining the number of cells in the row that will be programmed to each of a plurality of bit states corresponding to the write data. The control logic unit then selects a set of bit state assignments that will cause the programming level assigned to each bit state to be inversely proportional to the number of memory cells in the row that are programmed with the bit state. The selected set of bit states is then used to program the memory cells in the row.
摘要翻译：非易失性存储器件以使寄生信号的耦合最小化的方式对每行中的存储器单元进行编程。控制逻辑单元使用通过评估将被写入行中的单元的数据而选择的一组位状态分配来对单元中的单元进行编程。控制逻辑单元通过确定将被编程到与写入数据相对应的多个位状态中的每一个的行中的单元的数量来执行该评估。然后控制逻辑单元选择一组位状态分配，这将导致分配给每个位状态的编程电平与该行状态下用该位状态编程的存储单元的数量成反比。然后使用所选的一组位状态来编程该行中的存储单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式