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11. 发明申请

WO2004077638A1 TESTING USING INDEPENDENTLY CONTROLLABLE VOLTAGE ISLANDS 审中-公开
标题翻译：使用独立的可控电压岛进行测试
公开(公告)号：WO2004077638A1
公开(公告)日：2004-09-10
申请号：PCT/US2003/005313
申请日：2003-02-20
申请人： INTERNATIONAL BUSINESS MACHINES COPORATION , GATTIKER, Anne , NIGH, Phil , PASTEL, Leah , VAN HORN, Jody , ZUCHOWSKI, Paul, S. , OAKLAND, Steven, F.
发明人： GATTIKER, Anne , NIGH, Phil , PASTEL, Leah , VAN HORN, Jody , ZUCHOWSKI, Paul, S. , OAKLAND, Steven, F.
IPC分类号： H02J9/00
CPC分类号： G01R31/318536 , G01R31/318544 , G01R31/318555 , G01R31/318575 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of voltage islands (102, 104), each powered by a respective island source voltage (VDDI1, VDDI2), and a testing circuit (116), coupled to the voltage islands, and powered by a global source voltage (Vg) that is always on during test , wherein each island source voltage may be independently controlled (106, 108) during test.
摘要翻译：一种电压岛结构，其中每个电压岛的源电压可以在基于扫描的测试期间独立地接通/关断或调节。该架构包括多个电压岛（102,104），每个电压岛由各自的岛源电压（VDDI1，VDDI2）供电，以及耦合到电压岛的测试电路（116），并由全局源极电压 Vg），其在测试期间总是导通，其中每个岛源电压可以在测试期间被独立地控制（106,108）。

12. 发明申请

WO03083904B1 SERIAL INTEGRATED SCAN-BASED TESTING OF INK JET PRINT HEAD 审中-公开
标题翻译：喷墨打印头的串行集成扫描测试
公开(公告)号：WO03083904B1
公开(公告)日：2004-08-26
申请号：PCT/US0309151
申请日：2003-03-24
申请人： LEXMARK INT INC
发明人： COOK WILLIAM PAUL , EDELEN JOHN GLENN , PARISH GEORGE KEITH , ROWE KRISTI MAGGARD , ZEARFOSS SUSAN MARIE
IPC分类号： B41J2/05 , G01R31/3185 , B41J29/38 , B41J29/393 , G01R31/28
CPC分类号： B41J2/04541 , B41J2/04543 , B41J2/0458 , G01R31/318536
摘要： An n-bit serial register (12) in an ink jet print head (10) operates in a print mode or a test mode. When the shift register (12) is operating in the print mode or a test mode. When the shift register is operating in the print mode, n bits of print data (PDATA) are serially scanned into n number of bit registers (12) and are then latched out to heater addressing logic circuitry (20), (22), (24), in the print head (10) to control a print operation. When the circuit is operating in the test mode, x bits of test point data from x number of test nodes (TP) in the print head (10) are loaded in parallel into x number of the n number of bit registers (12), and are then serially scanned out to a test data output (TDATA). In this manner, a single shift register (12) may be used to scan in print data (PDATA) and scan out test data (TDATA), thereby providing observability and controllability of the internal logic nodes of the print head (10) while minimizing logic size and the number of input/output connections on the print head.
摘要翻译：喷墨打印头（10）中的n位串行寄存器（12）以打印模式或测试模式操作。当移位寄存器（12）在打印模式或测试模式下操作时。当移位寄存器以打印模式操作时，将n位打印数据（PDATA）串行扫描到n个位寄存器（12）中，然后锁存到加热器寻址逻辑电路（20），（22），（在打印头（10）中控制打印操作。当电路在测试模式下工作时，来自打印头（10）中x个测试节点（TP）的测试点数据的x位被并行加载到n个位寄存器（12）中的x个数中，然后被串行扫描输出到测试数据输出（TDATA）。以这种方式，可以使用单个移位寄存器（12）来扫描打印数据（PDATA）并且扫描出测试数据（TDATA），从而提供打印头（10）的内部逻辑节点的可观察性和可控制性，同时最小化逻辑大小和打印头上输入/输出连接的数量。

13. 发明申请

WO2003098244A1 CELL WITH FIXED OUTPUT VOLTAGE FOR INTEGRATED CIRCUIT 审中-公开
标题翻译：用于集成电路的固定输出电压的电池
公开(公告)号：WO2003098244A1
公开(公告)日：2003-11-27
申请号：PCT/IB2003/002077
申请日：2003-05-15
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , DA SILVA, Patrick , SOUEF, Laurent
发明人： DA SILVA, Patrick , SOUEF, Laurent
IPC分类号： G01R31/3185
CPC分类号： G01R31/318541 , G01R31/318536 , G01R31/318572
摘要： The invention relates to a testable integrated circuit. In order to replace ground and VDD in certain points of such a circuit, the circuit comprises a cell (34) which comprises a flipflop (11) and means (31) able to set the output voltage of the cell when the circuit is in the operation mode. These means for setting the output voltage are controlled by a control signal (15) which depends on the mode signal that indicates whether the signal is in the test mode or in the operation mode.
摘要翻译：本发明涉及可测试的集成电路。为了在这种电路的某些点处替换接地和VDD，该电路包括一个单元（34），该单元包括一个触发器（11）和一个装置（31），当电路处于操作模式。用于设定输出电压的这些装置由控制信号（15）控制，控制信号（15）取决于指示信号是处于测试模式还是处于操作模式的模式信号。

14. 发明申请

WO2003067477A1 METHOD AND PROGRAM PRODUCT FOR COMPLETING A CIRCUIT DESIGN HAVING EMBEDDED TEST STRUCTURES 审中-公开
标题翻译：用于完成具有嵌入式测试结构的电路设计的方法和程序产品
公开(公告)号：WO2003067477A1
公开(公告)日：2003-08-14
申请号：PCT/US2003/001829
申请日：2003-01-23
申请人： LOGICVISION, INC. , CÔTÉ, Jean-François , PRICE, Paul
发明人： CÔTÉ, Jean-François , PRICE, Paul
IPC分类号： G06F17/50
CPC分类号： G01R31/318314 , G01R31/31704 , G01R31/318342 , G01R31/318536 , G06F17/5045
摘要： A sign-off method for use in verifying of embedded test structures in a circuit design extracts a description of all embedded test structures from a circuit description to create a test connection map file (52), and verifies the connections of the test structures to circuit pins or nets, creates verification configuration files for use in performing a sign-off verification of the circuit, for a circuit containing logic test structures (56), verifies that each logic test structure complies with logic test design rules and creates logic test vectors and a reference signature (58), performs a formal verification (60) and a static timing analysis of the circuit (62), generates a sign-off simulation test bench for each test structure using the verification configuration files and the test connection map file, executes the test benches to simulate all test structures in the circuit (66); and creates manufacturing test patterns (80).
摘要翻译：用于验证电路设计中嵌入式测试结构的签名方法从电路描述中提取所有嵌入式测试结构的描述，以创建测试连接映射文件（52），并验证测试结构与电路的连接引脚或网络创建用于执行电路的签发验证的验证配置文件，对于包含逻辑测试结构（56）的电路，验证每个逻辑测试结构符合逻辑测试设计规则并创建逻辑测试向量，并且参考签名（58）执行电路（62）的形式验证（60）和静态定时分析，使用验证配置文件和测试连接映射文件为每个测试结构生成签发模拟测试台，执行测试台以模拟电路中的所有测试结构（66）; 并创建制造测试图案（80）。

15. 发明申请

WO02095587A2 METHOD AND APPARATUS FOR FAULT TOLERANT AND FLEXIBLE TEST SIGNATURE GENERATOR 审中-公开
标题翻译：用于容错和灵活测试签名生成器的方法和装置
公开(公告)号：WO02095587A2
公开(公告)日：2002-11-28
申请号：PCT/US0215806
申请日：2002-05-16
申请人： INTEL CORP , UDAWATTA KAPILA B , BABELLA ANTHONY
发明人： UDAWATTA KAPILA B , BABELLA ANTHONY
IPC分类号： G01R31/3185 , G06F11/28
CPC分类号： G01R31/318544 , G01R31/318536 , G01R31/318547
摘要： An apparatus with a generator to generate a pattern and multiple scan chains (110) configured to receive the pattern from the generator. Multiple signature registers (116, 118) coupled to the scan chains, to receive an output of at least one of scan chains during a mode of the integrated device.
摘要翻译：一种具有用于产生图案的发生器和被配置为从发生器接收图案的多个扫描链（110）的装置。耦合到扫描链的多个签名寄存器（116,118）在集成设备的模式期间接收扫描链中的至少一个的输出。

16. 发明申请

WO01053844A1 HIERARCHICAL TEST CIRCUIT STRUCTURE FOR CHIPS WITH MULTIPLE CIRCUIT BLOCKS 审中-公开
标题翻译：具有多个电路块的电路的分层测试电路结构
公开(公告)号：WO01053844A1
公开(公告)日：2001-07-26
申请号：PCT/US2001/002007
申请日：2001-01-18
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22 , H01L21/822 , H01L27/04
CPC分类号： G01R31/318505 , G01R31/318536
摘要： A system and method for testing an integrated circuit (200) having internal circuit blocks (210 and 212). Each of the internal circuit blocks may have their own test circuit blocks, referred to as socket access ports (220 and 221). The integrated circuit includes a chip access port (205) that is an IEEE 1149.1 compliant test access port connected to a set of boundary scan cells (240), and connected in a hierarchical order to lower-level test circuit blocks (230 and 232). Each of the lower-level test control blocks comprises a socket access port (235 and 236). Test operations are transferred downward and upward within the hierarchical structure by communicating between test control circuit blocks at the immediately higher or lower level in the hierarchical structure. Existing boundary scans can be easily modified for use in the hierarchical structure by adding push instructions to send to lower levels and pop instructions to return control to higher level test circuit blocks.
摘要翻译：一种用于测试具有内部电路块（210和212）的集成电路（200）的系统和方法。每个内部电路块可以具有它们自己的测试电路块，称为插座接入端口（220和221）。集成电路包括芯片接入端口（205），该芯片接入端口（205）是连接到一组边界扫描单元（240）的符合IEEE 1149.1标准的测试访问端口，并且以等级顺序连接到较低级别的测试电路块（230和232）。每个下级测试控制块包括插座访问端口（235和236）。通过在层次结构中立即更高或更低层的测试控制电路块之间进行通信，在层次结构内向下和向上传送测试操作。现有的边界扫描可以通过添加推送指令发送到较低级别和弹出指令以便将控制权返回给更高级别的测试电路块，可以容易地修改为在层次结构中使用。

17. 发明申请

WO2015050786A1 BUFFER TESTING FOR RECONFIGURABLE INSTRUCTION CELL ARRAYS 审中-公开
标题翻译：用于可重构指令单元阵列的缓冲器测试
公开(公告)号：WO2015050786A1
公开(公告)日：2015-04-09
申请号：PCT/US2014/057680
申请日：2014-09-26
申请人： QUALCOMM INCORPORATED
发明人： RAO, Hari , NARAYANAN, Venkatasubramanian , BOYNAPALLI, Venugopal , SABADE, Sagar Suresh , ZAFAR, Bilal
IPC分类号： G06F11/27 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/3185 , G01R31/318516 , G01R31/318533 , G01R31/318536 , G01R31/3187 , G06F11/27 , G11C29/022 , G11C29/12
摘要： A reconfigurable instruction cell array (RICA) is provided that includes a plurality of master switch boxes that are configured to read and write from a plurality of buffers through a cross-bar switch. A master built-in-self-test (MBIST) engine is configured to drive a test word into the write path of at least one master switch box and to control the cross-bar switch so that the driven test word is broadcast to all the buffers for storage. The MBIST engine is also configured to retrieve the stored test words from the buffers through a read bus within the cross-bar switch.
摘要翻译：提供了可重构指令单元阵列（RICA），其包括多个主开关盒，其被配置为通过交叉开关从多个缓冲器读取和写入。主内置自检（MBIST）引擎被配置为将测试字驱动到至少一个主开关盒的写入路径中并且控制交叉开关，使得驱动的测试字广播到所有用于存储的缓冲区 MBIST引擎还被配置为通过交叉开关中的读总线从缓冲器中检索存储的测试字。

18. 发明申请

WO2013043615A1 MEMORY HARD MACRO PARTITION OPTIMIZATION FOR TESTING EMBEDDED MEMORIES 审中-公开
标题翻译：用于测试嵌入式存储器的内存硬分区优化
公开(公告)号：WO2013043615A1
公开(公告)日：2013-03-28
申请号：PCT/US2012/055944
申请日：2012-09-18
申请人： SYNOPSYS, INC.
发明人： ZORIAN, Yervant , DARBINYAN, Karen , TORJYAN, Gevorg
IPC分类号： G01R31/28
CPC分类号： G06F17/5031 , G01R31/318536 , G01R31/318572 , G06F17/505 , G06F17/5068 , G11C29/12 , G11C29/16 , G11C29/32 , G11C2029/0401
摘要： A memory hard macro designed to support multiple design for test (DFT) techniques having signal paths associated with the DFT techniques and the functional operation of the memory instance that share logic devices or components. The memory hard macro includes a functional input port and a functional output port, forming a functional memory data path, which includes input latches from the memory instance. The memory hard macro also includes a scan input port and a scan output port, forming a scan data path, which includes input latches from the array of data buffer circuits and output latches from the array of sense amplifiers. The memory hard macro further includes a BIST input port and a BIST output port, forming a BIST data path, which includes at least one input latch from the array of data buffer circuits and at least one output latch from the array of sense amplifiers.
摘要翻译：设计用于支持具有与DFT技术相关联的信号路径和共享逻辑设备或组件的存储器实例的功能操作的测试（DFT）技术的多个设计的存储器硬宏。存储器硬宏包括功能输入端口和功能输出端口，形成功能存储器数据路径，其包括来自存储器实例的输入锁存器。存储器硬宏还包括扫描输入端口和扫描输出端口，形成扫描数据路径，其包括来自数据缓冲电路阵列的输入锁存器和来自读出放大器阵列的输出锁存器。存储器硬宏还包括BIST输入端口和BIST输出端口，形成BIST数据路径，其包括来自数据缓冲器电路阵列的至少一个输入锁存器和来自读出放大器阵列的至少一个输出锁存器。

19. 发明申请

WO2009022276A3 SOFTWARE-BASED VERIFICATION OF SYSTEM-ON-CHIP DIRECT INTERCONNECT THROUGH ADDITIONAL REGISTERS 审中-公开
标题翻译：通过附加寄存器进行基于软件的片上直接互连的验证
公开(公告)号：WO2009022276A3
公开(公告)日：2009-04-09
申请号：PCT/IB2008053194
申请日：2008-08-08
申请人： NXP BV , STUYT JAN , DE RUYTER BERNARD W , DE JONG ROELOF P , STRUIK PIETER , GEURTS JORIS H J
发明人： STUYT JAN , DE RUYTER BERNARD W , DE JONG ROELOF P , STRUIK PIETER , GEURTS JORIS H J
IPC分类号： G01R31/317
CPC分类号： G01R31/318536 , G01R31/318541
摘要： A system on a chip comprises a plurality of circuit blocks (18), a programmable processor (12) and a communication circuit (16) coupled between the processor (12) and the plurality of circuit blocks (18), the communication circuit (16) being configured to support program controlled access to registers in the circuit blocks (18) from the processor (12), a first and second one of the circuit blocks (18) of the plurality having direct mutual connection (19) for directly passing a signal between the first and second one of the circuit blocks (18) without communication through the communication circuit (12). Design information is used that comprises connection data including an identification of the direct mutual connection (19) and the first and second circuit blocks (18) coupled by the direct mutual connection (19). An additional register is added to the system on a chip coupled to the direct mutual connection (19) to capture and/or control signals at the direct mutual connection (19). The additional register (44, 46) is coupled to the communication circuit to support program controlled access to the additional register (44, 46). Interface programs for the processor (12) are used, each for a specific one of the circuit blocks (18), the interface programs for the first one of the circuit blocks (18) being configured to accept standardized access calls to access the additional register (44, 46). Verification programs are used, each for a respective one of the circuit blocks (18), the verification program for the second one of the circuit blocks (18) comprising instructions for the processor (12) to access registers in the second one of the circuit blocks (18), to use the connection data, or information derived therefrom to select the first one of the circuit blocks (18) on the basis of the identification of the first one of the circuit blocks (18) in the connection data, and to issue the standardized call to the interface program of the selected further one of the circuit blocks (18) to observe and/or control a signal via the direct mutual connection (19) during execution of the verification program for the second one of the circuit blocks (18). Operation of the system on a chip is monitored when operating under control of the verification program.
摘要翻译：芯片上的系统包括耦合在处理器（12）和多个电路块（18）之间的多个电路块（18），可编程处理器（12）和通信电路（16），通信电路（16））被配置为支持对来自处理器（12）的电路块（18）中的寄存器的程序控制访问，所述多个电路块（18）中的第一和第二电路块（18）具有直接相互连接（19），用于直接通过在第一和第二电路块（18）之间的信号，而不通过通信电路（12）进行通信。使用包括通过直接相互连接（19）和通过直接相互连接（19）耦合的第一和第二电路块（18）的标识的连接数据的设计信息。在耦合到直接相互连接（19）的芯片上的附加寄存器被添加到系统，以在直接相互连接（19）处捕获和/或控制信号。附加寄存器（44,46）耦合到通信电路以支持对附加寄存器（44,46）的程序控制访问。使用用于处理器（12）的接口程序，每个用于电路块（18）中的特定的一个，用于第一个电路块（18）的接口程序被配置为接受标准化访问呼叫以访问附加寄存器（44,46）。使用验证程序，每个用于电路块（18）中的相应一个，用于第二电路块（18）的验证程序包括用于处理器（12）访问电路的第二个中的寄存器的指令块（18），以使用连接数据或其导出的信息根据连接数据中的第一个电路块（18）的识别来选择电路块（18）中的第一个，以及发出对所选择的另一个电路块（18）的接口程序的标准化呼叫，以在电路的第二个的验证程序执行期间经由直接相互连接（19）观察和/或控制信号块（18）。在验证程序的控制下进行操作时，会对芯片上的系统进行操作。

20. 发明申请

WO2009022276A2 VERIFICATION OF DESIGN INFORMATION FOR CONTROLLING MANUFACTURE OF A SYSTEM ON A SHIP 审中-公开
标题翻译：船舶系统制造控制设计信息验证
公开(公告)号：WO2009022276A2
公开(公告)日：2009-02-19
申请号：PCT/IB2008/053194
申请日：2008-08-08
申请人： NXP B.V. , STUYT, Jan , DE RUYTER, Bernard, W. , DE JONG, Roelof, P. , STRUIK, Pieter , GEURTS, Joris, H., J.
发明人： STUYT, Jan , DE RUYTER, Bernard, W. , DE JONG, Roelof, P. , STRUIK, Pieter , GEURTS, Joris, H., J.
IPC分类号： G01R31/317
CPC分类号： G01R31/318536 , G01R31/318541
摘要： A system on a chip comprises a plurality of circuit blocks (18), a programmable processor (12) and a communication circuit (16) coupled between the processor (12) and the plurality of circuit blocks (18), the communication circuit (16) being configured to support program controlled access to registers in the circuit blocks (18) from the processor (12), a first and second one of the circuit blocks (18) of the plurality having direct mutual connection (19) for directly passing a signal between the first and second one of the circuit blocks (18) without communication through the communication circuit (12). Design information is used that comprises connection data including an identification of the direct mutual connection (19) and the first and second circuit blocks (18) coupled by the direct mutual connection (19). An additional register is added to the system on a chip coupled to the direct mutual connection (19) to capture and/or control signals at the direct mutual connection (19). The additional register (44, 46) is coupled to the communication circuit to support program controlled access to the additional register (44, 46). Interface programs for the processor (12) are used, each for a specific one of the circuit blocks (18), the interface programs for the first one of the circuit blocks (18) being configured to accept standardized access calls to access the additional register (44, 46). Verification programs are used, each for a respective one of the circuit blocks (18), the verification program for the second one of the circuit blocks (18) comprising instructions for the processor (12) to access registers in the second one of the circuit blocks (18), to use the connection data, or information derived therefrom to select the first one of the circuit blocks (18) on the basis of the identification of the first one of the circuit blocks (18) in the connection data, and to issue the standardized call to the interface program of the selected further one of the circuit blocks (18) to observe and/or control a signal via the direct mutual connection (19) during execution of the verification program for the second one of the circuit blocks (18). Operation of the system on a chip is monitored when operating under control of the verification program.
摘要翻译：芯片上的系统包括耦合在处理器（12）和多个电路块（18）之间的多个电路块（18），可编程处理器（12）和通信电路（16），通信电路（16））被配置为支持对来自处理器（12）的电路块（18）中的寄存器的程序控制访问，所述多个电路块（18）中的第一和第二电路块（18）具有直接相互连接（19），用于直接通过在第一和第二电路块（18）之间的信号，而不通过通信电路（12）通信。使用包括通过直接相互连接（19）和通过直接相互连接（19）耦合的第一和第二电路块（18）的标识的连接数据的设计信息。在耦合到直接相互连接（19）的芯片上的附加寄存器被添加到系统，以在直接相互连接（19）处捕获和/或控制信号。附加寄存器（44,46）耦合到通信电路以支持对附加寄存器（44,46）的程序控制访问。使用用于处理器（12）的接口程序，每个用于电路块（18）中的特定的一个，用于第一个电路块（18）的接口程序被配置为接受标准化访问呼叫以访问附加寄存器（44,46）。使用验证程序，每个用于电路块（18）中的相应一个，用于第二电路块（18）的验证程序包括用于处理器（12）访问电路的第二个中的寄存器的指令块（18），以使用连接数据或其导出的信息根据连接数据中的第一个电路块（18）的识别来选择电路块（18）中的第一个，以及发出对所选择的另一个电路块（18）的接口程序的标准化呼叫，以在电路的第二个的验证程序执行期间经由直接相互连接（19）观察和/或控制信号块（18）。在验证程序的控制下进行操作时，会对芯片上的系统进行操作。

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