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11. 发明申请

WO2018147919A1 DETECTING MISALIGNMENT IN MEMORY ARRAY AND ADJUSTING READ AND VERIFY TIMING PARAMETERS ON SUB-BLOCK AND BLOCK LEVELS 审中-公开
公开(公告)号：WO2018147919A1
公开(公告)日：2018-08-16
申请号：PCT/US2017/063440
申请日：2017-11-28
申请人： SANDISK TECHNOLOGIES LLC
发明人： YU, Xuehong , PANG, Liang , DONG, Yingda
IPC分类号： G11C16/08 , G11C29/02 , G11C8/08
摘要： A memory device and associated techniques adjust voltage ramping times optimally for each block or sub-block of memory cells to account for fabrication variations. The widths of word lines and select gate lines can vary in different sub-blocks due to misalignments in the fabrication process. The resistance and voltage settling times vary based on the widths. In one aspect, a shortest acceptable ramp down period is determined for a select gate line. This period avoids excessive read errors. A corresponding shortest acceptable word line voltage ramping period is then determined for each sub-block. A pattern in the ramp down periods can be detected among the tested sub-blocks or blocks and used to set ramp down periods in other sub-blocks or blocks. The overall time for a programming or read operation is therefore minimized.

12. 发明申请

WO2017218055A1 DYNAMIC TUNING OF FIRST READ COUNTERMEASURES 审中-公开
标题翻译：动态调整第一次读取的对策
公开(公告)号：WO2017218055A1
公开(公告)日：2017-12-21
申请号：PCT/US2017/018637
申请日：2017-02-21
申请人： SANDISK TECHNOLOGIES LLC
发明人： PANG, Liang , DONG, Yingda , YUAN, Jiahui , KWONG, Charles
IPC分类号： G11C16/34 , G11C16/26 , G11C11/56 , G11C7/04 , G11C29/02 , G11C29/42 , G11C16/04 , G11C16/20
摘要： Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage (Vth) of a memory cell can shift depending on when the read operation occurs. Countermeasures are provided for a first read situation in which a memory is read after a power on event or after a long delay since a last read. Read voltages of lower or higher programmed data states are set according to a positive or negative temperature coefficient (Tco), respectively. Read voltages for error recovery can be set similarly. In another aspect, a wait period between a dummy voltage and a read voltage is a function of temperature. In another aspect, word line voltages of unselected blocks are set according to a negative Tco. In another aspect, pass voltages are set based on a Tco for each programmed data state.
摘要翻译：提供了用于提高存储器单元的读取操作的准确性的技术，其中存储器单元的阈值电压（Vth）可以根据读取操作何时发生而移位。针对第一次读取情况提供了对策，其中在上电事件之后或自上次读取之后的长时间延迟之后读取存储器。根据正或负温度系数（Tco）分别设置较低或较高编程数据状态的读取电压。用于错误恢复的读取电压可以类似地设置。另一方面，虚拟电压和读取电压之间的等待时间是温度的函数。在另一方面，未选块的字线电压根据负Tco来设定。在另一方面，通过电压基于每个编程数据状态的Tco来设置。

13. 发明申请

WO2017069869A1 WORD LINE DEPENDENT CHANNEL PRE-CHARGE FOR MEMORY 审中-公开
标题翻译：字库相关通道预存储器
公开(公告)号：WO2017069869A1
公开(公告)日：2017-04-27
申请号：PCT/US2016/051362
申请日：2016-09-12
申请人： SANDISK TECHNOLOGIES LLC
发明人： PANG, Liang , YUAN, Jiahui , DONG, Yingda
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/12 , G11C16/24 , G11C16/3427 , G11C2211/5621 , H01L27/11524 , H01L27/11582
摘要： Techniques are provided for programming a memory device. A pre-charge phase is used to boost the channel of an unselected NAND string by allowing a bit line voltage to reach the channel. To maximize the channel pre-charge while also minimizing program disturb, a drain-side dummy word line voltage is controlled based on the position of the selected word line. The drain-side dummy word line voltage can be relatively high or low when the selected word line is relatively far from or close to the drain-side dummy word line, respectively. When the drain-side dummy word line voltage is relatively high, the bit line voltage can easily pass through and boost the channel. When the drain-side dummy word line voltage is relatively low, program disturb of drain-side data word lines is reduced due to a smaller channel gradient and a corresponding reduced amount of hot carriers.
摘要翻译：提供了用于编程存储设备的技术。预充电阶段用于通过允许位线电压到达通道来升高未选NAND串的通道。为了最大化沟道预充电同时也使编程干扰最小化，基于所选字线的位置来控制漏极侧伪字线电压。当选择的字线分别相对远离或靠近漏极侧伪字线时，漏极侧伪字线电压可以相对较高或较低。当漏极侧伪字线电压相对较高时，位线电压可以很容易地通过并且升高沟道。当漏侧虚拟字线电压相对较低时，由于较小的沟道梯度和相应减少的热载流子量，所以漏极侧数据字线的编程干扰减小。

14. 发明申请

WO2016118225A1 METHOD AND APPARATUS FOR REFRESH PROGRAMMING OF MEMORY CELLS BASED ON AMOUNT OF THRESHOLD VOLTAGE DOWNSHIFT 审中-公开
标题翻译：基于阈值电压梯度的存储器细胞刷新编程的方法和装置
公开(公告)号：WO2016118225A1
公开(公告)日：2016-07-28
申请号：PCT/US2015/061441
申请日：2015-11-18
申请人： SanDisk Technologies LLC
发明人： PANG, Liang , DONG, Yingda , CHEN, Jian
IPC分类号： G11C16/34 , G11C11/56
CPC分类号： G11C16/3431 , G11C11/5621 , G11C11/5671 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C16/3459
摘要： Techniques are provided for periodically monitoring and adjusting the threshold voltage levels of memory cells in a charge-trapping memory device. When a criterion is met, such as based on the passage of a specified time period, the memory cells are read to classify them into different subsets according to an amount of downshift in threshold voltage (Vth). Two or more subsets can be used per data state. A subset can also comprise cells which are corrected using Error Correction Code (ECC) decoding. The subsets of memory cells are refresh programmed, without being erased, in which a Vth upshift is provided in proportion to the Vth downshift. The refresh programming can use a fixed or adaptive number of program pulses per subset. Some cells will have no detectable Vth downshift or a minor amount of Vth downshift which can be ignored. These cells need not be refresh programmed.
摘要翻译：提供了用于周期性地监视和调整电荷俘获存储器件中的存储器单元的阈值电压电平的技术。当满足标准时，例如基于指定时间段的过去，存储器单元被读取以根据阈值电压（Vth）的降档量将其分类成不同的子集。每个数据状态可以使用两个或多个子集。子集还可以包括使用纠错码（ECC）解码来校正的单元。存储器单元的子集被刷新编程，而不被擦除，其中与Vth降档成比例地提供Vth升档。刷新编程可以使用每个子集的固定或自适应编程脉冲数。一些电池将没有可检测的Vth降档或少量的Vth降档，这可以被忽略。这些单元不需要刷新编程。

15. 发明申请

WO2018132186A1 SUPPRESSING DISTURB OF SELECT GATE TRANSISTORS DURING ERASE IN MEMORY 审中-公开
公开(公告)号：WO2018132186A1
公开(公告)日：2018-07-19
申请号：PCT/US2017/063414
申请日：2017-11-28
申请人： SANDISK TECHNOLOGIES LLC
发明人： ZHANG, Zhengyi , PANG, Liang , DONG, Yingda
IPC分类号： G11C16/14 , G11C16/16 , G11C16/34 , G11C16/04 , G11C16/08
摘要： A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel of the string is charged up from a source end of the string. However, there is a delay in charging up a drain end of the channel. A voltage detector connected to a bit line detects when a drain end of the channel reaches a reference voltage. When the reference voltage is reached, a voltage of the select gate transistor at the drain end of the string can be floated. This avoids unintentional programming of the select gate transistor which could otherwise occur if the voltage was floated to soon. Also, a substrate voltage may be ramped up to a first detected level before being ramped up to a second, final level.

16. 发明申请

WO2018102001A1 EQUALIZING ERASE DEPTH IN DIFFERENT BLOCKS OF MEMORY CELLS 审中-公开
公开(公告)号：WO2018102001A1
公开(公告)日：2018-06-07
申请号：PCT/US2017/050861
申请日：2017-09-09
申请人： SANDISK TECHNOLOGIES LLC
发明人： ZHANG, Zhengyi , PANG, Liang , ZENG, Caifu , YU, Xuehong , DONG, Yingda
IPC分类号： G11C16/34 , G11C16/16
摘要： A memory device and associated techniques provide a uniform erase depth for different blocks of memory cells which are at different distances from pass gates of a voltage source. In one approach, a voltage of a source side select gate transistor of a memory string is a decreasing function of the distance. In another approach, a magnitude or duration of an erase voltage at a source end of a memory string is an increasing function of the distance. Adjacent blocks can be arranged in subsets and treated as being at a common distance. In another approach, an additional erase pulse can be applied when the distance of the block exceeds a threshold. Other variables such as initial erase voltage and step size can also be adjusted as a function of distance.

17. 发明申请

WO2018071116A1 SELECT TRANSISTORS WITH TIGHT THRESHOLD VOLTAGE IN 3D MEMORY 审中-公开
标题翻译：在三维存储器中选择具有较高阈值电压的晶体管
公开(公告)号：WO2018071116A1
公开(公告)日：2018-04-19
申请号：PCT/US2017/050440
申请日：2017-09-07
申请人： SANDISK TECHNOLOGIES LLC
发明人： PANG, Liang , PACHAMUTHU, Jayavel , DONG, Yingda
IPC分类号： H01L27/1158 , H01L27/11524 , H01L27/11553 , H01L27/1157
CPC分类号： H01L27/11519 , H01L21/02532 , H01L21/0262 , H01L27/11524 , H01L27/11553 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/1158 , H01L27/11582 , H01L29/40114 , H01L29/40117 , H01L29/66825 , H01L29/66833
摘要： Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope.
摘要翻译：这里公开的是具有选择晶体管的3D存储器及其制造方法。选择晶体管可以具有导电浮置栅极，导电控制栅极，导电浮置栅极和导电控制栅极之间的第一电介质以及主体和导电浮置栅极之间的第二电介质。在一个方面中，使用在晶体半导体选择晶体管主体附近的凹槽中的横向外延生长，随后通过外延生长形成栅极电介质来形成均匀的栅极电介质。技术有助于防止或至少降低选择晶体管控制栅极与选择晶体管下方的选择晶体管主体和/或半导体衬底之间的泄漏电流。因此，选择具有基本均匀的阈值电压，电流和S因子的晶体管。另外，选择晶体管具有较高的导通电流和陡峭的亚阈值斜率。

18. 发明申请

WO2017204870A1 REDUCING NEIGHBORING WORD LINE IN INTERFERENCE USING LOW-K OXIDE 审中-公开
标题翻译：使用低K氧化物减少干扰相邻词干线
公开(公告)号：WO2017204870A1
公开(公告)日：2017-11-30
申请号：PCT/US2017/018550
申请日：2017-02-19
申请人： SANDISK TECHNOLOGIES LLC
发明人： PANG, Liang , DONG, Yingda , PACHAMUTHU, Jayavel , LU, Ching-Huang
IPC分类号： H01L29/66 , H01L29/788 , H01L29/792 , H01L27/11524 , H01L27/1157
CPC分类号： H01L21/7682 , H01L21/76816 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/5329 , H01L27/1157 , H01L27/11582 , H01L29/40117 , H01L29/66833
摘要： Techniques for fabricating a memory device which has reduced neighboring word line interference, and a corresponding memory device. The memory device comprises a stack of alternating conductive and dielectric layers, where the conductive layers form word lines or control gates of memory cells. In one aspect, the memory device is provided with a reduced dielectric constant (k) in locations of a fringing electric field of the control gate. For example, portions of the dielectric layers can be replaced with a low-k material. One approach involves recessing the dielectric layer and providing a low-k material in the recess. Another approach involves doping a portion of the blocking oxide layer to reduce its dielectric constant. Another approach involves removing a portion of the blocking oxide layer. In another aspect, the memory device is provided with an increased dielectric constant adjacent to the control gates.
摘要翻译：制造具有减小的邻近字线干扰的存储器件的技术以及相应的存储器件。存储器件包括交替的导电层和介电层的堆叠，其中导电层形成存储器单元的字线或控制栅极。在一个方面，存储器件在控制栅极的边缘电场的位置处具有降低的介电常数（k）。例如，介电层的部分可以用低k材料替代。一种方法涉及使电介质层凹陷并在凹陷中提供低k材料。另一种方法涉及掺杂一部分阻挡氧化物层以降低其介电常数。另一种方法涉及去除阻挡氧化层的一部分。在另一方面，存储器装置具有与控制栅极相邻的增加的介电常数。

19. 发明申请

WO2017112009A1 WORD LINE-DEPENDENT RAMPING OF PASS VOLTAGE AND PROGRAM VOLTAGE FOR THREE-DIMENSIONAL MEMORY 审中-公开
标题翻译：三维存储器通道电压和程序电压的字符线依赖性砰击
公开(公告)号：WO2017112009A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/051365
申请日：2016-09-12
申请人： SANDISK TECHNOLOGIES LLC
发明人： PANG, Liang , YUAN, Jiahui , DONG, Yingda , REN, Jingjian
IPC分类号： G11C16/04 , G11C16/10 , G11C16/08 , G11C16/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/08 , G11C16/10 , G11C16/3427 , G11C16/3459
摘要： Techniques are provided for programming a three-dimensional memory device while minimizing over-programming and program disturb. When a selected word line is at the source-side of a set of word lines, a channel gradient is created in the channel adjacent to the selected word line when a program voltage is applied. The gradient generates hot carriers which can cause over-programming of memory cells connected to the selected word line. To reduce the amount of hot carriers, a ramp rate and/or duration of a first step up of the program voltage is reduced. When the selected word line is not at the source-side of the set of word lines, a baseline ramp rate and/or duration can be used. A ramp rate and/or duration of the voltage applied to unselected word lines can be reduced as well but by a lesser amount.
摘要翻译：提供了用于编程三维存储器装置的技术，同时最小化过度编程和编程干扰。当所选字线位于一组字线的源侧时，当施加编程电压时，在与所选字线相邻的通道中创建通道梯度。该梯度生成热载流子，这会导致连接到所选字线的存储单元的过度编程。为了减少热载流子的数量，降低编程电压第一次升压的斜率和/或持续时间。当所选字线不在该组字线的源侧时，可以使用基线斜率和/或持续时间。施加到未选字线的电压的斜坡速率和/或持续时间也可以减少，但数量较少。

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