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11. 发明申请

WO2008048563A3 CRYSTAL OSCILLATOR EMULATOR 审中-公开
标题翻译：水晶振荡器仿真器
公开(公告)号：WO2008048563A3
公开(公告)日：2008-06-26
申请号：PCT/US2007022015
申请日：2007-10-16
申请人： MARVELL WORLD TRADE LTD , SUTARDJA SEHAT
发明人： SUTARDJA SEHAT
IPC分类号： H03L1/00 , H03L5/00
CPC分类号： H01L23/34 , H01L2924/0002 , H01L2924/16152 , H01L2924/16235 , H01L2924/3011 , H03L1/026 , H03L1/027 , H03L5/00 , H03L7/07 , H03L7/1974 , H03L7/1976 , H01L2924/00
摘要： A crystal oscillator emulator integrated circuit comprises a first temperature sensor that senses a first temperature of the integrated circuit. Memory stores calibration parameters and selects at least one of the calibration parameters based on the first temperature. A semiconductor oscillator generates an output signal having a frequency, which is based on the calibration parameters, and an amplitude. An amplitude adjustment module compares the amplitude to a predetermined amplitude and generates a control signal that adjusts the amplitude based on the comparison.
摘要翻译：晶体振荡器模拟器集成电路包括感测集成电路的第一温度的第一温度传感器。存储器存储校准参数并且基于第一温度选择至少一个校准参数。半导体振荡器产生具有基于校准参数的频率的输出信号和振幅。幅度调整模块将振幅与预定幅度进行比较，并产生基于该比较来调节振幅的控制信号。

12. 发明申请

WO2007133646B1 ADAPTIVE STORAGE SYSTEM INCLUDING HARD DISK DRIVE WITH FLASH INTERFACE 审中-公开
标题翻译：自适应存储系统，包括带有闪存接口的硬盘驱动器
公开(公告)号：WO2007133646B1
公开(公告)日：2008-04-17
申请号：PCT/US2007011326
申请日：2007-05-10
申请人： MARVELL WORLD TRADE LTD , SUTARDJA SEHAT , YANG YUN
发明人： SUTARDJA SEHAT , YANG YUN
IPC分类号： G06F1/32
CPC分类号： G06F3/0625 , G06F1/32 , G06F1/3203 , G06F1/3221 , G06F1/3268 , G06F3/0632 , G06F3/0634 , G06F3/0644 , G06F3/0656 , G06F3/068 , G06F3/0685 , G06F12/0866 , G06F2212/222 , G06F2212/224 , G11B19/00 , Y02D10/154 , Y02D50/20
摘要： Various types of data storage systems employ low power disk drives to cache data to/from high power disk drives to reduce power consumption and access times. Some of the disk drives may communicate with a host device via a non-volatile semiconductor memory interface such as a flash memory interface.
摘要翻译：各种类型的数据存储系统使用低功率磁盘驱动器来高速缓存来自高功率磁盘驱动器的数据以减少功耗和访问时间。一些磁盘驱动器可以通过诸如闪存接口的非易失性半导体存储器接口与主机设备通信。

13. 发明申请

WO2008079399A2 POWER CONTROL DEVICE 审中-公开
标题翻译：电源控制装置
公开(公告)号：WO2008079399A2
公开(公告)日：2008-07-03
申请号：PCT/US2007026309
申请日：2007-12-26
申请人： MARVELL WORLD TRADE LTD , SUTARDJA SEHAT
发明人： SUTARDJA SEHAT
IPC分类号： H05B37/02 , F21Y101/00
CPC分类号： H05B37/0263 , H05B37/02
摘要： A controllable light bulb comprises an electrical connector, a receiver module, an electronic switch, a translucent casing, and a light producing element. The electrical connector receives a power signal. The receiver module is powered by the power signal received via the electrical connector and determines control parameters based upon on/off modulation of the power signal. The receiver module generates a control signal based upon the control parameters while the power signal is on. The electronic switch outputs an output power signal and reduces the output power signal based on the control signal. The translucent casing encloses the light producing element. The light producing element receives the output power signal.
摘要翻译：可控灯泡包括电连接器，接收器模块，电子开关，半透明外壳和发光元件。电连接器接收电源信号。接收器模块由通过电连接器接收的功率信号供电，并且基于功率信号的开/关调制确定控制参数。接收器模块在功率信号接通时基于控制参数产生控制信号。电子开关输出输出功率信号，并根据控制信号减小输出功率信号。半透明外壳包围发光元件。发光元件接收输出功率信号。

14. 发明申请

WO2008045196A3 GPS-BASED TRAFFIC MONITORING SYSTEM 审中-公开
标题翻译：基于GPS的交通监控系统
公开(公告)号：WO2008045196A3
公开(公告)日：2008-07-03
申请号：PCT/US2007020524
申请日：2007-09-21
申请人： MARVELL WORLD TRADE LTD , SUTARDJA SEHAT
发明人： SUTARDJA SEHAT
IPC分类号： G08G1/01
CPC分类号： G08G1/0104 , G08G1/096775
摘要： A cellular phone comprises a cellular phone control module that controls the cellular phone, a global positioning system (GPS) selectively generates vector and location data, and a transmitter. The cellular phone control module selectively wirelessly transmits the vector and location data using the transmitter when at least one of the cellular phone is traveling on a first set of predetermined roads and does not transmit the vector and location data when the cellular phone is traveling on a second set of roads, and the cellular phone is traveling at a first speed that is greater than a predetermined speed.
摘要翻译：蜂窝电话包括控制蜂窝电话的蜂窝电话控制模块，全球定位系统（GPS）选择性地生成矢量和位置数据，以及发射机。蜂窝电话控制模块在至少一个蜂窝电话在第一组预定道路上行驶时使用发射机选择性地无线发送矢量和位置数据，并且当蜂窝电话在第一组预定道路上行驶时不发送矢量和位置数据第二组道路，并且蜂窝电话以大于预定速度的第一速度行进。

15. 发明申请

WO2007136556A3 EFFICIENT TRANSISTOR STRUCTURE 审中-公开
标题翻译：有效的晶体管结构
公开(公告)号：WO2007136556A3
公开(公告)日：2008-07-03
申请号：PCT/US2007011207
申请日：2007-05-08
申请人： MARVELL WORLD TRADE LTD , SUTARDJA SEHAT
发明人： SUTARDJA SEHAT
IPC分类号： H01L27/02
CPC分类号： H01L27/0207 , H01L21/76816 , H01L21/76838 , H01L21/76895 , H01L21/823418 , H01L21/823437 , H01L27/0203 , H01L27/088 , H01L27/105 , H01L29/41758 , H01L29/4238
摘要： An integrated circuit comprises a first source, a first drain, a second source, a first gate arranged between the first source and the first drain, and a second gate arranged between the first drain and the second source. The first and second gates define alternating first and second regions in the drain. The first and second gates are arranged farther apart in the first regions than in the second regions.
摘要翻译：集成电路包括第一源极，第一漏极，第二源极，布置在第一源极和第一漏极之间的第一栅极，以及布置在第一漏极和第二源极之间的第二栅极。第一和第二栅极限定漏极中交替的第一和第二区域。第一和第二栅极在第一区域中比在第二区域中分开更远。

16. 发明申请

WO2008018989A2 FULLY- BUFFERED DUAL IN-LINE MEMORY MODULE WITH FAULT CORRECTION 审中-公开
标题翻译：全缓冲双列直插式内存模块，具有故障校正功能
公开(公告)号：WO2008018989A2
公开(公告)日：2008-02-14
申请号：PCT/US2007016661
申请日：2007-07-24
申请人： MARVELL WORLD TRADE LTD , SUTARDJA SEHAT , AZIMI SAEED
发明人： SUTARDJA SEHAT , AZIMI SAEED
CPC分类号： G11C29/02 , G11C11/401 , G11C11/406 , G11C29/028 , G11C29/50 , G11C29/50016 , G11C29/72 , G11C2211/4061
摘要： A memory module comprises first memory that stores data in memory blocks; second memory that temporarily stores data from at least one of the memory blocks and third memory for storing a relationship between addresses of the at least one of the memory blocks in the first memory and corresponding addresses of the data from the at least one of the memory blocks in the second memory. Storage capacities of the second and third memories are less than a storage capacity of the first memory. A control module selectively transfers data in the at least one of the memory blocks in the first memory to the second memory and stores and retrieves data from the second memory for the at least one of the memory blocks based on the relationship during the testing.
摘要翻译：存储器模块包括将数据存储在存储器块中的第一存储器; 暂时存储来自至少一个存储块的数据的第二存储器和用于存储第一存储器中的至少一个存储块的地址与来自存储器中的至少一个的数据的对应地址之间的关系的第三存储器块在第二个内存中。第二和第三存储器的存储容量小于第一存储器的存储容量。控制模块基于测试期间的关系，选择性地将第一存储器中的至少一个存储器块中的数据传送到第二存储器，并且存储和从第二存储器取回针对至少一个存储器块的数据。

17. 发明申请

WO2008005112A2 CONFIGURABLE VOLTAGE REGULATOR 审中-公开
标题翻译：可配置电压调节器
公开(公告)号：WO2008005112A2
公开(公告)日：2008-01-10
申请号：PCT/US2007011880
申请日：2007-05-18
申请人： MARVELL WORLD TRADE LTD , SUTARDJA SEHAT
发明人： SUTARDJA SEHAT
CPC分类号： G01R31/31924
摘要： A testing system comprises a configurable integrated circuit that selectively communicates with one or more of N external impedances, that has M predetermined configurations that are selected based on an electrical characteristic of the one or more of the N external impedances, where N and M are integers greater than one. The configurable integrated circuit generates a selected one of M discrete values of an output characteristic of the configurable integrated circuit based on the selected one of the M predetermined configurations. An integrated circuit is tested in accordance with an output of the configurable integrated circuit.
摘要翻译：测试系统包括可配置集成电路，其选择性地与N个外部阻抗中的一个或多个通信，N个外部阻抗具有基于N个外部阻抗中的一个或多个的电气特性选择的M个预定配置，其中N和M是整数大于一。可配置集成电路基于所选择的M个预定配置中的一个，生成可配置集成电路的输出特性的M个离散值中的一个选定的一个。集成电路根据可配置集成电路的输出进行测试。

18. 发明申请

WO2015127207A4 METHOD AND APPARATUS FOR INCORPORATING PASSIVE DEVICES IN AN INTEGRATED PASSIVE DEVICE SEPARATE FROM A DIE 审中-公开
标题翻译：用于在一个DIE中分离的集成无源器件中的被动设备的方法和装置
公开(公告)号：WO2015127207A4
公开(公告)日：2015-11-19
申请号：PCT/US2015016823
申请日：2015-02-20
申请人： MARVELL WORLD TRADE LTD , LEONG POH BOON , WU ALBERT , WANG LONG-CHING , SUTARDJA SEHAT
发明人： LEONG POH BOON , WU ALBERT , WANG LONG-CHING , SUTARDJA SEHAT
IPC分类号： H01L23/66 , H01L25/16 , H01L49/02
CPC分类号： H04B1/40 , H01L21/76898 , H01L23/481 , H01L23/49503 , H01L23/49575 , H01L23/645 , H01L23/66 , H01L24/17 , H01L24/48 , H01L24/49 , H01L24/85 , H01L25/16 , H01L25/162 , H01L25/50 , H01L28/10 , H01L2223/6644 , H01L2223/6672 , H01L2223/6677 , H01L2224/16145 , H01L2224/16225 , H01L2224/16265 , H01L2224/32145 , H01L2224/32265 , H01L2224/48247 , H01L2224/48465 , H01L2224/49 , H01L2224/73204 , H01L2224/85 , H01L2924/00014 , H01L2924/102 , H01L2924/10253 , H01L2924/1304 , H01L2924/13091 , H01L2924/1421 , H01L2924/19011 , H01L2924/19103 , H04B1/00 , H04B15/04 , H01L2224/45099 , H01L2224/05599 , H01L2924/00
摘要： A circuit including a first die, an integrated passive device and a second layer. The first die includes a first substrate and active devices. The integrated passive device includes a first layer, a second substrate and passive devices. The second substrate includes vias. The passive devices are implemented at least on the first layer or the second substrate. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The second layer is disposed between the first die and the integrated passive device. The second layer includes pillars. Each of the pillars connects a corresponding one of the active devices to (i) one of the vias, or (ii) one of the passive devices. The first die, the integrated passive device and the second layer are disposed relative to each other to form a stack.
摘要翻译：一种包括第一管芯，集成无源器件和第二层的电路。第一管芯包括第一衬底和有源器件。集成无源器件包括第一层，第二衬底和无源器件。第二基板包括通孔。无源器件至少在第一层或第二衬底上实现。第二基板的每单位面积的电阻率大于第一基板的每单位面积的电阻率。第二层设置在第一管芯和集成的无源器件之间。第二层包括柱子。每个支柱将相应的一个有源器件连接到（i）一个通孔，或（ii）一个无源器件。第一管芯，集成无源器件和第二层相对于彼此设置以形成堆叠。

19. 发明申请

WO2013067137A4 SCALABLE SUCCESSIVE-APPROXIMATION-REGISTER ANALOG-TO-DIGITAL CONVERTERS 审中-公开
公开(公告)号：WO2013067137A4
公开(公告)日：2013-09-06
申请号：PCT/US2012062990
申请日：2012-11-01
申请人： MARVELL WORLD TRADE LTD , SUTARDJA SEHAT , CESURA GIOVANNI ANTONIO , REZZI FRANCESCO , CASTELLO RINALDO
发明人： SUTARDJA SEHAT , CESURA GIOVANNI ANTONIO , REZZI FRANCESCO , CASTELLO RINALDO
IPC分类号： H03M1/00
CPC分类号： H03M1/20 , A01K79/00 , A23K50/80 , H03M1/002 , H03M1/0643 , H03M1/0678 , H03M1/1076 , H03M1/121 , H03M1/468
摘要： A system including a clock generator configured to generate a clock; a plurality of analog-to-digital converters each configured to convert a signal based on the clock, and to output a first number of bits in response to converting the signal based on the clock; and an averaging module configured to receive the first number of bits from each of the plurality of analog-to-digital converters, and to output a second number of bits. The second number of bits is greater than the first number of bits.

20. 发明申请

WO2013078311A4 FREQUENCY SCALING OF VARIABLE SPEED SYSTEMS FOR FAST RESPONSE AND POWER REDUCTION 审中-公开
标题翻译：用于快速响应和降低功率的变速系统的频率标定
公开(公告)号：WO2013078311A4
公开(公告)日：2013-07-18
申请号：PCT/US2012066257
申请日：2012-11-21
申请人： MARVELL WORLD TRADE LTD , SUTARDJA PANTAS , SUTARDJA SEHAT
发明人： SUTARDJA PANTAS , SUTARDJA SEHAT
IPC分类号： G06F1/08 , G06F1/32 , H03L7/00
CPC分类号： H03K3/02 , G06F1/08 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A system including a plurality of amplifiers configured to generate a clock signal having a frequency. The clock signal is input to a processor. The amplifiers are connected in series. An output of a last one of the amplifiers is fed back to an input of a first one of the amplifiers. Each of the amplifiers has a transconductance. A frequency adjustment module is configured to adjust, based on an activity level of the processor, the frequency of the clock signal by adjusting the transconductance of the amplifiers.
摘要翻译：一种包括被配置为生成具有频率的时钟信号的多个放大器的系统。时钟信号被输入到处理器。放大器串联连接。最后一个放大器的输出被反馈到第一个放大器的输入端。每个放大器都有一个跨导。频率调整模块被配置为基于处理器的活动水平通过调整放大器的跨导来调整时钟信号的频率。

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