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11. 发明申请

WO2009040608A1 TIMER UNIT, SYSTEM, COMPUTER PROGRAM PRODUCT AND METHOD FOR TESTING A LOGIC CIRCUIT 审中-公开
标题翻译：定时器单元，系统，计算机程序产品和测试逻辑电路的方法
公开(公告)号：WO2009040608A1
公开(公告)日：2009-04-02
申请号：PCT/IB2007/053878
申请日：2007-09-25
申请人： FREESCALE SEMICONDUCTOR, INC. , BOGENBERGER, Florian , CHALUPA, Leos
发明人： BOGENBERGER, Florian , CHALUPA, Leos
IPC分类号： G01R31/317
CPC分类号： G01R31/31701 , G01R31/31727
摘要： A timer unit (28) includes a timer (281) for timing the period of time the logic circuit has been in the self-test mode. A comparator (282) is connected to the timer, for comparing the period of time with a maximum for the period of time the logic circuit is allowed to be in the self-test mode and outputting an error signal when the period of time exceeds the maximum. The test timer unit further includes a mode detector (283) for detecting a switching of the logic circuit to the self-test mode. The mode detector is connected to the timer, for starting the timer upon the switching to the self-test mode and stopping the timer upon a switching of the logic circuit out of the self-test mode.
摘要翻译：定时器单元（28）包括定时器（281），用于对逻辑电路处于自检模式的时间段进行定时。比较器（282）连接到定时器，用于将逻辑电路被允许处于自检模式的时间段的最大值的时间段与时间段相比较，并且当时间段超过时间时输出错误信号最大值。测试定时器单元还包括用于检测逻辑电路到自检模式的切换的模式检测器（283）。模式检测器连接到定时器，用于在切换到自检模式时启动定时器，并且在逻辑电路切换到自检模式之后停止定时器。

12. 发明申请

WO2008099239A1 SYSTEM, COMPUTER PROGRAM PRODUCT AND METHOD FOR TESTING A LOGIC CIRCUIT 审中-公开
标题翻译：系统，计算机程序产品和测试逻辑电路的方法
公开(公告)号：WO2008099239A1
公开(公告)日：2008-08-21
申请号：PCT/IB2007/050518
申请日：2007-02-16
申请人： FREESCALE SEMICONDUCTOR, INC. , SAKADA, Oleksandr , BOGENBERGER, Florian
发明人： SAKADA, Oleksandr , BOGENBERGER, Florian
IPC分类号： G01R31/3187 , G01R31/3183 , G06F11/27
CPC分类号： G06F11/27 , G01R31/005 , G01R31/007 , G01R31/3183 , G01R31/3187
摘要： A system (25) for testing a logic circuit (20) which has two or more test routine modules (27). Each module contains a set of instructions which is executable by (a part of) the logic circuit (20). The set forms a test routine for performing a self-test by the part of the logic circuit (20). The self-test includes the part of the logic circuit (20) testing itself for faulty behaviour, and the part of the logic circuit (20) determining a self-test result of the testing. The system (25) includes a test module which can execute a test application which subjects the logic circuit (20) to a test by performing the self-test on at least a part of the logic circuit (20) by causes the part of the logic circuit (20) to execute a selected test routine, and determining, by the test module, an overall test result at least based on a performed self-tests. The test module includes a control output interface for activates the execution of the a selected test routine. A second test module input interface can receive the self-test result from a selected test routine. At a test module output interface the overall test result may be outputted. The test routine includes instructions for outputting, by the part of the logic circuit (20), data to a test routine output interface which is not connected to the second test module input interface, for outputting information about the self-test result by the test routines without passing the information through the test module.
摘要翻译：一种用于测试具有两个或更多个测试程序模块（27）的逻辑电路（20）的系统（25）。每个模块包含一组由逻辑电路（20）的（一部分）可执行的指令。该组形成用于由逻辑电路（20）的一部分进行自检的测试程序。自检包括逻辑电路（20）的一部分测试自身的故障行为，并且逻辑电路（20）的一部分确定测试的自检结果。系统（25）包括测试模块，该测试模块可以执行测试应用，测试应用通过在逻辑电路（20）的至少一部分上执行自检来使逻辑电路（20）进行测试，逻辑电路（20），用于执行所选择的测试程序，并且由所述测试模块至少基于执行的自检来确定总体测试结果。测试模块包括用于激活所选择的测试例程的执行的控制输出接口。第二个测试模块输入接口可以从选定的测试程序中接收自检结果。在测试模块输出接口，可以输出整体测试结果。该测试例程包括由逻辑电路（20）的一部分将数据输出到未连接到第二测试模块输入接口的测试例程输出接口，用于通过测试输出关于自检结果的信息例程不通过测试模块的信息。

13. 发明申请

WO2003105392A1 METHODS FOR USE WITH TIMESLOT IDENTIFIERS IN A TIMESLOT-BASED PROTOCOL AND APPARATUS 审中-公开
标题翻译：使用TIMESLOT标识符在基于TIMESLOT的协议和设备中使用的方法
公开(公告)号：WO2003105392A1
公开(公告)日：2003-12-18
申请号：PCT/EP2003/005073
申请日：2003-05-12
申请人： MOTOROLA INC , BOGENBERGER, Florian , RAUSCH, Mathias
发明人： BOGENBERGER, Florian , RAUSCH, Mathias
IPC分类号： H04L1/00
CPC分类号： H04L1/0072 , H04L1/0061 , H04L1/0083
摘要： A system (100) transmitter (200) receiver (300) and methods for use with timeslot identifiers in a timeslot-based protocol. A message identifier (ID-t) which marks the (mini) slot number is encoded with a cyclic redundancy value (CRC) into a message's error detection code in a way that can be easily inverted by the message receiver without loss of a CRC's hamming distance, which leads to the benefits of reduction of the control information in the transmitted data (reduction of overhead); and saving of bandwidth in serial data transmission.
摘要翻译：一种系统（100）发射机（200）接收机（300）以及用于基于时隙的协议中的时隙标识符的方法。标记（迷你）时隙号的消息标识符（ID-t）以循环冗余值（CRC）被编码成消息的错误检测码，可以容易地被消息接收机反转而不丢失CRC的汉明距离，这导致减少传输数据中的控制信息（减少开销）的好处; 并在串行数据传输中节省带宽。

14. 发明申请

WO2004051925A2 SYSTEM NODE AND METHOD FOR PROVIDING MEDIA ARBITRATION 审中-公开
标题翻译：用于提供媒体仲裁的系统节点和方法
公开(公告)号：WO2004051925A2
公开(公告)日：2004-06-17
申请号：PCT/EP2003/050868
申请日：2003-11-21
申请人： MOTOROLA INC , TEMPLE, Christopher , BOGENBERGER, Florian , RAUSCH, Mathias , THANNER, Manfred , WUERZ, Thomas , LINK, Leonard , POKORNY, Gregor
发明人： TEMPLE, Christopher , BOGENBERGER, Florian , RAUSCH, Mathias , THANNER, Manfred , WUERZ, Thomas , LINK, Leonard , POKORNY, Gregor
IPC分类号： H04L12/00
CPC分类号： H04L12/417 , H04L12/413 , H04L12/6418 , H04L2012/40241 , H04L2012/40273 , H04L2012/6435 , H04L2012/644
摘要： A multi-node communications system is provided with communications protocol using both static (11, 12, 13, 18) (pre-determined) and dynamic (51, 52, 53...) (run-time determined) consecutive communication slots is used. The system has a number of distributed communication nodes, each node being arranged for communicating frames of data with the other nodes during both the static (11, 12, 13...) and the dynamic (51, 52, 53...) communication slots. Each node includes a synchronized time base 5 made up of consecutive timeslots (11, 12, 13..., 51, 52, 53...) . The timebase 5 has substantially the same error tolerance in each node. For static communication (10), a predetermined number of timeslots (20) are utilized for each static communication slot. For dynamic communication a dynamically allocated number of timeslots (60) are utilized for each dynamic communication slot. In this way both static and dynamic media arbitration is provided within a periodically recurring communication pattern. Communication jitter is well defined and dealt with, and large oscillator drifts are compensated for.
摘要翻译：提供了具有使用静态（11,12,13,18）（预定）和动态（51,52,53 ...）（运行时确定的）连续通信时隙的通信协议的多节点通信系统用过的。该系统具有多个分布式通信节点，每个节点被布置用于在静态（11,12,13 ...）和动态（51,52,53 ...）期间与其他节点通信数据帧，通讯槽每个节点包括由连续时隙（11,12,13 ...，51,52,53 ...）组成的同步时基5。时基5在每个节点中具有基本上相同的误差容限。对于静态通信（10），对于每个静态通信时隙使用预定数量的时隙（20）。对于动态通信，动态分配数量的时隙（60）被用于每个动态通信时隙。以这种方式，在周期性循环通信模式中提供静态和动态媒体仲裁。通信抖动被很好地定义和处理，大的振荡器漂移被补偿。

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