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    • 12. 发明申请
    • VERTICAL CAVITY SURFACE EMITTING LASERS WITH CONSISTENT SLOPE EFFICIENCIES
    • 具有一致性斜率效应的垂直孔表面发射激光
    • WO0030226A8
    • 2000-07-06
    • PCT/US9926793
    • 1999-11-12
    • CIELO COMMUNICATIONS INCSCOTT JEFFREY W
    • SCOTT JEFFREY W
    • H01S5/00H01S5/02H01S5/028H01S5/183H01S5/10
    • H01S5/183H01S5/0042H01S5/0201H01S5/02284H01S5/0285H01S5/0427
    • A vertical cavity surface emitting laser, VCSEL, (2) with variable tuning layer (10) for adjusting the slope of the laser (2) and method for manufacturing the same are disclosed. In practice, a VCSEL wafer is grown by any conventional technique, and fabricated into discrete lasers (2) while maintained in wafer form. The initial lasers (2) are then tested to determine characteristics, such as the slope efficiency distribution to within a target specification by altering the phase of the top facet reflectivity of the initial lasers (2). The resulting change in transmission directly changes the laser slope in a predictable fashion. The tuning step may be repeated, if necessary, to further refine the slope to the desired value. The method produces VCSELs (2) with similar or consistent slopes from a plurality of wafers. Also disclosed are an optical subassembly (110) and optical transceiver (130) incorporating the improved VCSELs.
    • 公开了一种垂直腔面发射激光器,具有用于调节激光器斜率的可变调谐层(2)的VCSEL(2)及其制造方法。 实际上,通过任何常规技术生长VCSEL晶片,并将其制成分立激光器(2),同时保持晶片形式。 然后测试初始激光器(2),以通过改变初始激光器(2)的顶面反射率的相位来确定特征,例如目标规格内的斜率效率分布。 所产生的变化的变化直接以可预测的方式改变激光斜率。 如果需要,可以重复调整步骤,以进一步将斜率细化到期望值。 该方法产生具有与多个晶片相似或一致的斜率的VCSEL(2)。 还公开了结合有改进的VCSEL的光学子组件(110)和光收发器(130)。
    • 14. 发明申请
    • A METHOD OF OPERATING A MULTI-THREAD CAPABLE PROCESSOR SYSTEM, AN AUTOMOTIVE SYSTEM COMPRISING SUCH MULTI-THREAD CAPABLE PROCESSOR SYSTEM, AND A COMPUTER PROGRAM PRODUCT
    • 一种操作多线程能力处理器系统的方法,包括这种多线程能力处理器系统的汽车系统和计算机程序产品
    • WO2014125338A1
    • 2014-08-21
    • PCT/IB2013/051258
    • 2013-02-15
    • FREESCALE SEMICONDUCTOR, INC.ROBERTSON, AlistairSCOTT, Jeffrey W.
    • ROBERTSON, AlistairSCOTT, Jeffrey W.
    • G06F9/38G06F9/46
    • G06F9/30189G06F9/30185G06F9/3851
    • A method of operating a multi-thread capable processor system comprising a plurality of processor pipelines is described. The method comprises fetching an instruction comprising an address and selecting an operation mode based on the address of the fetched instruction, the operation mode being selected from at least a lock-step mode and a multi-thread mode. If the operation mode is selected to be the lock-step mode, the method comprises letting at least two processor pipelines of the multi-thread capable processor system execute the instruction in lock- step mode to obtain respective lock-step results, comparing the respective lock-step results against a comparison criterion for determining whether the respective lock-step results match, and, if the respective lock-step results match, determine a matching result from the respective lock-step results, and writing back the matching results. Further, a method of operating a multi-thread capable processor system, a multi-thread capable processor system, an automotive system comprising such multi-thread capable processor system, and a computer program product is described.
    • 描述了一种操作包括多个处理器管线的多线程处理器系统的方法。 该方法包括:获取包含地址的指令,并且基于所取出的指令的地址选择操作模式,所述操作模式至少从锁步模式和多线程模式中选择。 如果操作模式被选择为锁步模式,则该方法包括使多线程处理器系统的至少两个处理器管线以锁步模式执行指令以获得相应的锁步结果, 针对用于确定相应的锁定步骤结果是否匹配的比较准则的锁定步骤结果,以及如果相应的锁定步骤结果匹配,则确定来自相应锁定步骤结果的匹配结果,并且写回匹配结果。 此外,描述了一种操作多线程处理器系统,多线程处理器系统,包括这种多线程处理器系统的汽车系统和计算机程序产品的方法。
    • 15. 发明申请
    • SELECTIVE GUARDED MEMORY ACCESS ON A PER-INSTRUCTION BASIS
    • 在指令基础上选择性保护存储器访问
    • WO2008085648A2
    • 2008-07-17
    • PCT/US2007/087258
    • 2007-12-12
    • FREESCALE SEMICONDUCTOR INC.SCOTT, Jeffrey W.MOYER, William C.
    • SCOTT, Jeffrey W.MOYER, William C.
    • G06F12/00
    • G06F9/3834G06F9/30043G06F9/30181
    • A method includes receiving, at a processing device, a memory access instruction (402) comprising a guarded access specifier representative of a guarded access policy. The method further includes performing, at the processing device, a memory access represented by the memory access instruction in accordance with the guarded access policy (408). A processing device (100) includes a processor core (110) configured to determine a guarded access policy for a memory access instruction based on a guarded access specifier (310) of the memory access instruction (300). The processing device (100) further includes a memory management unit (112) configured to facilitate a memory access represented by the memory access instruction based on the guarded access policy.
    • 一种方法包括在处理设备处接收包括代表被保护的访问策略的保护访问说明符的存储器访问指令(402)。 该方法还包括在处理设备处根据保护的访问策略执行由存储器访问指令表示的存储器访问(408)。 处理设备(100)包括配置成基于存储器访问指令(300)的保护访问说明符(310)来确定用于存储器访问指令的保护访问策略的处理器内核(110)。 处理设备(100)还包括存储器管理单元(112),其被配置为基于被保护的访问策略来促进由存储器访问指令表示的存储器访问。