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1. 发明申请

WO2009134518A1 SELECTIVELY PERFORMING A SINGLE CYCLE WRITE OPERATION WITH ECC IN A DATA PROCESSING SYSTEM 审中-公开
标题翻译：在数据处理系统中选择性地执行ECC的单周期写操作
公开(公告)号：WO2009134518A1
公开(公告)日：2009-11-05
申请号：PCT/US2009/034871
申请日：2009-02-23
申请人： FREESCALE SEMICONDUCTOR INC. , MOYER, William C. , SCOTT, Jeffrey W.
发明人： MOYER, William C. , SCOTT, Jeffrey W.
IPC分类号： G11C29/42 , G06F11/14 , G11C7/00
CPC分类号： G06F11/1044 , G11C2029/0411
摘要： A circuit (10) includes a memory (28, 16, or 26) having error correction, circuitry (30) which initiates a write operation to memory. When error correction is enabled and the write operation to the memory has the width of N bits, the write operation to the memory is performed in one access to the memory, and when error correction is enabled and the write operation to the memory has the width of M bits, where M bits is less than N bits, the write operation to the memory is performed in more than one access to the memory. In one example, the one access to the memory includes a write access to the memory, and the more than one access to the memory includes a read access to the memory and a write access to the memory.
摘要翻译：电路（10）包括具有纠错的存储器（28,16或26），启动对存储器的写操作的电路（30）。当启用纠错并且对存储器的写操作具有N位的宽度时，对存储器的写入操作在对存储器的一次访问中执行，并且当使能错误校正并且对存储器的写入操作具有宽度的M位，其中M位小于N位，对存储器的写入操作在对存储器的多次访问中执行。在一个示例中，对存储器的一次访问包括对存储器的写访问，并且对存储器的多个访问包括对存储器的读访问和对存储器的写访问。

2. 发明申请

WO2007109395A3 DATA PROCESSOR HAVING DYNAMIC CONTROL OF INSTRUCTION PREFETCH BUFFER DEPTH AND METHOD THEREFOR 审中-公开
标题翻译：具有指令预留缓冲区深度的动态控制的数据处理器及其方法
公开(公告)号：WO2007109395A3
公开(公告)日：2008-10-30
申请号：PCT/US2007062651
申请日：2007-02-23
申请人： FREESCALE SEMICONDUCTOR INC , SCOTT JEFFREY W , MOYER WILLIAM C
发明人： SCOTT JEFFREY W , MOYER WILLIAM C
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3802 , G06F9/30149 , G06F9/3814 , G06F12/0862 , G06F2212/6022 , Y02D10/13
摘要： A data processor (102) includes a prefetch buffer (112) and a fetch control unit (116). The prefetch buffer (112) has a plurality of lines. The prefetch buffer (112) has a variable maximum depth that defines a number of lines of the plurality of lines that are capable of storing instructions. The fetch control unit (116) is coupled to the prefetch buffer to monitor at least one of the plurality of lines of the prefetch buffer (112) and to adjust the variable maximum depth of the prefetch buffer (112) in response to a state of the data processor (102).
摘要翻译：数据处理器（102）包括预取缓冲器（112）和获取控制单元（116）。预取缓冲器（112）具有多条线。预取缓冲器（112）具有可变的最大深度，其定义能够存储指令的多行的行数。取指控制单元（116）耦合到预取缓冲器以监视预取缓冲器（112）的多行中的至少一行并响应于预取缓冲器（112）的状态来调整预取缓冲器（112）的可变最大深度数据处理器（102）。

3. 发明申请

WO2008085648A3 SELECTIVE GUARDED MEMORY ACCESS ON A PER-INSTRUCTION BASIS 审中-公开
标题翻译：选择性的保护记忆访问在一个基本的基础上
公开(公告)号：WO2008085648A3
公开(公告)日：2008-10-16
申请号：PCT/US2007087258
申请日：2007-12-12
申请人： FREESCALE SEMICONDUCTOR INC , SCOTT JEFFREY W , MOYER WILLIAM C
发明人： SCOTT JEFFREY W , MOYER WILLIAM C
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/30043 , G06F9/30181
摘要： A method includes receiving, at a processing device, a memory access instruction (402) comprising a guarded access specifier representative of a guarded access policy. The method further includes performing, at the processing device, a memory access represented by the memory access instruction in accordance with the guarded access policy (408). A processing device (100) includes a processor core (110) configured to determine a guarded access policy for a memory access instruction based on a guarded access specifier (310) of the memory access instruction (300). The processing device (100) further includes a memory management unit (112) configured to facilitate a memory access represented by the memory access instruction based on the guarded access policy.
摘要翻译：一种方法包括在处理设备处接收包括代表受保护的访问策略的被保护的访问说明符的存储器访问指令（402）。该方法还包括在处理装置处执行根据被保护的访问策略（408）由存储器访问指令表示的存储器访问。处理设备（100）包括处理器核心（110），其被配置为基于存储器访问指令（300）的被保护的访问说明符（310）确定存储器访问指令的保护访问策略。处理装置（100）还包括存储器管理单元（112），被配置为基于被保护的访问策略来促进由存储器访问指令表示的存储器访问。

4. 发明申请

WO2008061141A1 SUB-PIXEL NBN DETECTOR 审中-公开
标题翻译：子像素NBN检测器
公开(公告)号：WO2008061141A1
公开(公告)日：2008-05-22
申请号：PCT/US2007/084674
申请日：2007-11-14
申请人： LOCKHEED MARTIN CORPORATION , CAINE, Ernie, J. , SCOTT, Jeffrey, W. , JONES, Colin, E. , COCKRUM, Charles, A.
发明人： CAINE, Ernie, J. , SCOTT, Jeffrey, W. , JONES, Colin, E. , COCKRUM, Charles, A.
IPC分类号： H01L27/146
CPC分类号： H01L31/035281 , H01L27/146 , H01L27/14601 , H01L27/14603 , H01L27/14638 , H01L27/14643 , H01L27/14694 , H01L31/0304 , H01L31/101 , H01L31/102 , Y02E10/50
摘要： A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AISb, AIAsSb, AIGaAsSb, AIPSb, AIGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area.
摘要翻译：制造二维检测器阵列（和这种阵列）的方法包括形成n掺杂半导体光吸收层的多行和多列单独检测器中的每一行，形成阻挡层，该阻挡层包括一个或多个AISb，AlAsSb，AIGaAsSb，AIPSb，AIGaPSb和HgZnTe，并形成n掺杂的半导体接触区域。

5. 发明申请

WO2008061141A9 SUB-PIXEL NBN DETECTOR 审中-公开
标题翻译：亚像素NBN探测器
公开(公告)号：WO2008061141A9
公开(公告)日：2008-07-03
申请号：PCT/US2007084674
申请日：2007-11-14
申请人： LOCKHEED CORP , CAINE ERNIE J , SCOTT JEFFREY W , JONES COLIN E , COCKRUM CHARLES A
发明人： CAINE ERNIE J , SCOTT JEFFREY W , JONES COLIN E , COCKRUM CHARLES A
IPC分类号： H01L27/146
CPC分类号： H01L31/035281 , H01L27/146 , H01L27/14601 , H01L27/14603 , H01L27/14638 , H01L27/14643 , H01L27/14694 , H01L31/0304 , H01L31/101 , H01L31/102 , Y02E10/50
摘要： A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AISb, AIAsSb, AIGaAsSb, AIPSb, AIGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area.
摘要翻译：一种制造二维检测器阵列（以及这种阵列）的方法，对于多个行和多列独立检测器中的每一个，形成n掺杂半导体光吸收层，形成阻挡层，该阻挡层包括一个或多个AISb，AIAsSb，AIGaAsSb，AIPSb，AIGaPSb和HgZnTe，并形成n掺杂的半导体接触区。

6. 发明申请

WO2007109395A2 DATA PROCESSOR HAVING DYNAMIC CONTROL OF INSTRUCTION PREFETCH BUFFER DEPTH AND METHOD THEREFOR 审中-公开
标题翻译：具有指令预留缓冲区深度的动态控制的数据处理器及其方法
公开(公告)号：WO2007109395A2
公开(公告)日：2007-09-27
申请号：PCT/US2007/062651
申请日：2007-02-23
申请人： FREESCALE SEMICONDUCTOR INC. , SCOTT, Jeffrey W. , MOYER, William C.
发明人： SCOTT, Jeffrey W. , MOYER, William C.
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/30149 , G06F9/3814 , G06F12/0862 , G06F2212/6022 , Y02D10/13
摘要： A data processor (102) includes a prefetch buffer (112) and a fetch control unit (116). The prefetch buffer (112) has a plurality of lines. The prefetch buffer (112) has a variable maximum depth that defines a number of lines of the plurality of lines that are capable of storing instructions. The fetch control unit (116) is coupled to the prefetch buffer to monitor at least one of the plurality of lines of the prefetch buffer (112) and to adjust the variable maximum depth of the prefetch buffer (112) in response to a state of the data processor (102).
摘要翻译：数据处理器（102）包括预取缓冲器（112）和获取控制单元（116）。预取缓冲器（112）具有多条线。预取缓冲器（112）具有可变的最大深度，其限定能够存储指令的多行的行数。获取控制单元（116）耦合到预取缓冲器以监视预取缓冲器（112）的多行中的至少一行并且响应于预取缓冲器（112）的状态来调整预取缓冲器（112）的可变最大深度数据处理器（102）。

7. 发明申请

WO2005060458A3 METHOD AND APPARATUS FOR ALLOCATING ENTRIES IN A BRANCH TARGET BUFFER 审中-公开
公开(公告)号：WO2005060458A3
公开(公告)日：2005-07-07
申请号：PCT/US2004/037627
申请日：2004-11-12
申请人： FREESCALE SEMICONDUCTOR, INC. , MOYER, William C. , SCOTT, Jeffrey W.
发明人： MOYER, William C. , SCOTT, Jeffrey W.
IPC分类号： G06F15/00
摘要： A method (200) and apparatus (100) for allocating entries in a branch target buffer (BTB) (144) in a pipelined data processing system includes: sequentially fetching instructions; determining that one of the instructions is a branch instruction (210, 215, 220); decoding the branch instruction to determine a branch target address; determining if the branch target address can be obtained without causing a stall condition in the pipelined data processing system; and selectively allocating an entry of the BTB (144) based on the determination. In one embodiment, an entry of the BTB (144) is allocated if the branch instruction is not loaded into a predetermined slot (S1) of a prefetch buffer (102) and no other stall condition will occur. The method (200) and apparatus (100) combine the advantages of using a BTB (144) and branch lookahead to reduce stall conditions in the data processing system.

8. 发明申请

WO2005060458A2 METHOD AND APPARATUS FOR ALLOCATING ENTRIES IN A BRANCH TARGET BUFFER 审中-公开
标题翻译：用于在分支目标缓冲器中分配入口的方法和设备
公开(公告)号：WO2005060458A2
公开(公告)日：2005-07-07
申请号：PCT/US2004037627
申请日：2004-11-12
申请人： FREESCALE SEMICONDUCTOR INC , MOYER WILLIAM C , SCOTT JEFFREY W
发明人： MOYER WILLIAM C , SCOTT JEFFREY W
IPC分类号： G06F9/00 , G06F9/38 , G06F15/00
CPC分类号： G06F9/382 , G06F9/3806
摘要： A method (200) and apparatus (100) for allocating entries in a branch target buffer (BTB) (144) in a pipelined data processing system includes: sequentially fetching instructions; determining that one of the instructions is a branch instruction (210, 215, 220); decoding the branch instruction to determine a branch target address; determining if the branch target address can be obtained without causing a stall condition in the pipelined data processing system; and selectively allocating an entry of the BTB (144) based on the determination. In one embodiment, an entry of the BTB (144) is allocated if the branch instruction is not loaded into a predetermined slot (S1) of a prefetch buffer (102) and no other stall condition will occur. The method (200) and apparatus (100) combine the advantages of using a BTB (144) and branch lookahead to reduce stall conditions in the data processing system.
摘要翻译：一种用于在流水线数据处理系统中分配分支目标缓冲器（BTB）（144）中的条目的方法（200）和装置（100）包括：顺序地取指令; 确定所述指令之一是分支指令（210,215,220）; 解码分支指令以确定分支目标地址; 确定在流水线数据处理系统中是否可以获得分支目标地址而不引起失速状况; 并且基于该确定来选择性地分配BTB（144）的条目。在一个实施例中，如果分支指令未被加载到预取缓冲器（102）的预定时隙（S1）中并且不会发生其他停顿条件，则分配BTB（144）的条目。方法（200）和设备（100）结合使用BTB（144）和分支先行的优点来减少数据处理系统中的停滞条件。

9. 发明申请

WO2014108747A1 INTEGRATED CIRCUIT PROCESSOR AND METHOD OF OPERATING A INTEGRATED CIRCUIT PROCESSOR 审中-公开
标题翻译：集成电路处理器和集成电路处理器的操作方法
公开(公告)号：WO2014108747A1
公开(公告)日：2014-07-17
申请号：PCT/IB2013/050213
申请日：2013-01-10
申请人： FREESCALE SEMICONDUCTOR, INC. , ROBERSTON, Alistair , SCOTT, Jeffrey, W.
发明人： ROBERSTON, Alistair , SCOTT, Jeffrey, W.
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/30189 , G06F9/3851 , G06F9/3891
摘要： A processor (10) comprising an instruction pipeline is described. The pipeline can be operated alternatively in a multi-thread mode and in a single-thread mode. In the multi-thread mode, the instruction pipeline processes multiple threads (T0, T1) in an interleaved or simultaneous manner. In the single-thread mode, the pipeline processes a single thread. The instruction pipeline comprises multiple functional units (12, 14), each of which is reserved for one thread among the multiple threads when the pipeline is in the multi-thread mode and reserved for one context layer among multiple context layers (C1, C2) when the instruction pipeline is in the single-thread mode. A method of operating a processor is also disclosed.
摘要翻译：描述包括指令流水线的处理器（10）。管道可以以多线程模式和单线程模式交替运行。在多线程模式中，指令流程以交错或同时的方式处理多个线程（T0，T1）。在单线程模式下，流水线处理单线程。指令流水线包括多个功能单元（12,14），当多个线程处于多线程模式并且为多个上下文层（C1，C2）中的一个上下文层保留时，多个功能单元（12,14）被保留用于多个线程中的一个线程，当指令流水线处于单线程模式时。还公开了一种操作处理器的方法。

10. 发明申请

WO2010014286A1 BRANCH TARGET BUFFER ALLOCATION 审中-公开
标题翻译：分支目标缓冲区分配
公开(公告)号：WO2010014286A1
公开(公告)日：2010-02-04
申请号：PCT/US2009/043452
申请日：2009-05-11
申请人： FREESCALE SEMICONDUCTOR INC. , MOYER, William, C. , SCOTT, Jeffrey, W.
发明人： MOYER, William, C. , SCOTT, Jeffrey, W.
IPC分类号： G06F9/32 , G06F9/38 , G06F9/42
CPC分类号： G06F9/3806 , G06F9/3844
摘要： A data processing system (10) and method are provided for allocating an entry in a branch target buffer (BTB) (14). The method comprises: receiving a branch instruction to be executed in a data processor(40); determining that the BTB does not include an entry corresponding to the branch instruction; identifying an entry in the BTB for allocation, the identified entry in the BTB comprising a target identifier (30) and a first prediction value (32) for a previously received branch instruction; determining whether to allocate the branch instruction to the identified entry in the BTB based on a comparison of the first prediction value to a second prediction value, wherein the second prediction value is generated from a branch history table (BHT) (20); and allocating the branch instruction to the identified entry if the second prediction value indicates a more strongly taken prediction than the first prediction value.
摘要翻译：提供了一种用于在分支目标缓冲器（BTB）中分配条目的数据处理系统（10）和方法（14）。该方法包括：接收要在数据处理器（40）中执行的分支指令; 确定BTB不包括对应于分支指令的条目; 识别BTB中用于分配的条目，BTB中的识别条目包括用于先前接收的分支指令的目标标识符（30）和第一预测值（32）; 基于所述第一预测值与第二预测值的比较，确定是否将所述分支指令分配给所述BTB中的所述识别的条目，其中，所述第二预测值是从分支历史表（BHT）（20）生成的。以及如果所述第二预测值指示比所述第一预测值更强烈地采取预测，则将所述分支指令分配给所识别的条目。

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