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11. 发明申请

WO2005094221A2 NANOSTRUCTURES WITH ELECTRODEPOSITED NANOPARTICLES 审中-公开
标题翻译：具有电沉积纳米颗粒的纳米结构
公开(公告)号：WO2005094221A2
公开(公告)日：2005-10-13
申请号：PCT/US2004030562
申请日：2004-09-17
申请人： NANOMIX INC , BRADLEY KEITH , DAVIS ALONA , GABRIEL JEAN-CHRISTOPHE P , HAN TZONG-RU , JOSHI VIKRAM , STAR ALEXANDER
发明人： BRADLEY KEITH , DAVIS ALONA , GABRIEL JEAN-CHRISTOPHE P , HAN TZONG-RU , JOSHI VIKRAM , STAR ALEXANDER
IPC分类号： G01N27/00 , G01N27/414 , G01N33/00
CPC分类号： B82Y30/00 , G01N27/4146 , G01N33/005 , Y10S977/72
摘要： A nanoelectronic device includes a nanostructure, such as a nanotube or network of nanotubes, disposed on a substrate. Nanoparticles are disposed on or adjacent to the nanostructure so as to operatively effect the electrical properties of the nanostructure. The nanoparticles may be composed of metals, metal oxides, or salts, and nanoparticles composed of different materials may be present. The amount of nanoparticles may be controlled to preserve semiconductive properties of the nanostructure, and the substrate immediately adjacent to the nanostructure may remain substantially free of nanoparticles. A method for fabricating the device includes electrodeposition of the nanoparticles using one or more solutions of dissolved ions while providing an electric current to the nanostructures but not to the surrounding substrate.
摘要翻译：纳米电子器件包括设置在衬底上的纳米结构，例如纳米管或纳米管网络。将纳米颗粒设置在纳米结构上或与纳米结构相邻，以便有效地影响纳米结构的电性能。纳米颗粒可以由金属，金属氧化物或盐组成，并且可能存在由不同材料组成的纳米颗粒。可以控制纳米颗粒的量以保持纳米结构的半导体性质，并且紧邻纳米结构的衬底可以基本上不含纳米颗粒。制造该器件的方法包括使用一种或多种溶解离子的溶液电沉积纳米颗粒，同时向纳米结构提供电流，而不向周围的衬底提供电流。

12. 发明申请

WO2005062031A1 NANOELECTRONIC CAPNOMETER ADAPTER 审中-公开
标题翻译：纳米电位计适配器
公开(公告)号：WO2005062031A1
公开(公告)日：2005-07-07
申请号：PCT/US2004/042998
申请日：2004-12-20
申请人： NANOMIX, INC. , STAR, Alexander , WYATT, Jeffrey , JOSHI, Vikram , STETTNER, Joseph, R. , GRUNER, George
发明人： STAR, Alexander , WYATT, Jeffrey , JOSHI, Vikram , STETTNER, Joseph, R. , GRUNER, George
IPC分类号： G01N27/12
CPC分类号： G01N33/497 , B82Y10/00 , G01N27/4141 , G01N27/4146 , Y10S977/72
摘要： A capnometer adaptor (10) includes a nanostructure sensor (12).
摘要翻译：电容表适配器（10）包括纳米结构传感器（12）。

13. 发明申请

WO2002091473A1 FERROELECTRIC COMPOSITE MATERIAL, METHOD OF MAKING SAME AND MEMORY UTILIZING SAME 审中-公开
标题翻译：电解复合材料，其制造方法和使用其的记忆体
公开(公告)号：WO2002091473A1
公开(公告)日：2002-11-14
申请号：PCT/US2002/014888
申请日：2002-05-09
申请人： SYMETRIX CORPORATION , MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. , UCHIYAMA, Kiyoshi , PAZ DE ARAUJO, Carlos, A. , JOSHI, Vikram , SOLAYAPPAN, Narayan , CELINSKA, Jolanta , MCMILLAN, Larry, D.
发明人： UCHIYAMA, Kiyoshi , PAZ DE ARAUJO, Carlos, A. , JOSHI, Vikram , SOLAYAPPAN, Narayan , CELINSKA, Jolanta , MCMILLAN, Larry, D.
IPC分类号： H01L29/51
CPC分类号： H01L27/11502 , H01L21/02197 , H01L21/02282 , H01L21/28291 , H01L21/31691 , H01L27/11507 , H01L28/55 , H01L29/516 , H01L29/6684
摘要： A ferroelectric memory (436) includes a plurality of memory cells (73, 82, 100) each containing a ferroelectric thin film (15) including a microscopically composite material having a ferroelectric component (18) and a dielectric component (19), the dielectric component being a different chemical compound than the ferroelectric component. The dielectric component is preferably a fluxor, i.e., a material having a higher crystallization velocity than the ferroelectric component. The addition of the fluxor permits a ferroelectric thin film to be crystallized at a temperature of between 400 °C and 550 °C.
摘要翻译：铁电存储器（436）包括多个存储单元（73,82,100），每个存储单元包含具有铁电元件（18）和电介质元件（19）的显微复合材料的铁电薄膜（15），所述电介质组分是与铁电体组分不同的化合物。电介质成分优选为磁通量，即具有比铁电体成分高的结晶速度的材料。添加助熔剂可使铁电薄膜在400〜550℃的温度下结晶。

14. 发明申请

WO2011109231A3 CMP PROCESS FLOW FOR MEMS 审中-公开
标题翻译： MEMS的CMP工艺流程
公开(公告)号：WO2011109231A3
公开(公告)日：2011-12-29
申请号：PCT/US2011026167
申请日：2011-02-25
申请人： CAVENDISH KINETICS INC , LACEY JOSEPH DAMIAN GORDON , MAGUIRE THOMAS L , JOSHI VIKRAM , YOST DENNIS J
发明人： LACEY JOSEPH DAMIAN GORDON , MAGUIRE THOMAS L , JOSHI VIKRAM , YOST DENNIS J
IPC分类号： B81C1/00
CPC分类号： B81C1/00095 , B81B2203/04 , B81B2207/07 , B81C1/00611 , B81C2201/0104
摘要： The present invention generally relates to the formation of a micro-electromechanical system (MEMS) cantilever switch in a complementary metal oxide semiconductor (CMOS) back end of the line (BEOL) process. The cantilever switch is formed in electrical communication with a lower electrode in the structure. The lower electrode may be either blanket deposited and patterned or simply deposited in vias or trenches of the underlying structure. The excess material used for the lower electrode is then planarized by chemical mechanical polishing or planarization (CMP). The cantilever switch is then formed over the planarized lower electrode.
摘要翻译：本发明总体上涉及在互补金属氧化物半导体（CMOS）线后端（BEOL）工艺中形成微机电系统（MEMS）悬臂开关。悬臂开关形成为与该结构中的下电极电连通。下电极可以被毯式沉积并被图案化或者简单地沉积在下面的结构的通孔或沟槽中。然后通过化学机械抛光或平坦化（CMP）将用于下电极的多余材料平坦化。然后在平面化的下电极上形成悬臂开关。

15. 发明申请

WO2011079110A1 CARBON-BASED ELECTRODES WITH GRAPHENE MODIFICATION 审中-公开
标题翻译：具有石墨改性的碳基电极
公开(公告)号：WO2011079110A1
公开(公告)日：2011-06-30
申请号：PCT/US2010/061503
申请日：2010-12-21
申请人： BRIMAN, Mikhail , JOSHI, Vikram
发明人： BRIMAN, Mikhail , JOSHI, Vikram
IPC分类号： H01B1/20
CPC分类号： G01N27/308 , G01N27/3275 , H01B1/04
摘要： Certain embodiments of the present application describe a carbon-based electrode with graphene platelets. The addition of graphene platelets is intended to improve properties of the electrode. These properties include, but are not limited to, physical, electrical, and biochemical properties of the electrode. Enhanced reproducibility of these properties can also result from the addition of the graphene platelets.
摘要翻译：本申请的某些实施方案描述了具有石墨烯片晶的碳基电极。石墨烯血小板的添加旨在改善电极的性质。这些性质包括但不限于电极的物理，电学和生化特性。这些性质的增强的再现性也可以由添加石墨烯血小板引起。

16. 发明申请

WO2009134838A2 SYSTEM AND METHOD OF ENCAPSULATION 审中-公开
标题翻译：系统和封装方法
公开(公告)号：WO2009134838A2
公开(公告)日：2009-11-05
申请号：PCT/US2009/042028
申请日：2009-04-29
申请人： CAVENDISH KINETICS, LTD. , LACEY, Joseph, Damian Gordon , RENAULT, Mickael , JOSHI, Vikram , BOBEY, James, F. , VAN KAMPEN, Robertus, P.
发明人： LACEY, Joseph, Damian Gordon , RENAULT, Mickael , JOSHI, Vikram , BOBEY, James, F. , VAN KAMPEN, Robertus, P.
IPC分类号： B81C1/00
CPC分类号： B81C1/00333 , B81C2203/0145 , B81C2203/0154
摘要： Embodiments discussed herein generally include methods of fabricating MEMS devices within a structure. The MEMS device may be formed in a cavity above the structure, and additional metallization may occur above the MEMS device. The cavity may be formed by depositing an encapsulating layer over the sacrificial layers that enclose the MEMS device. The encapsulating layer may then be etched to expose portions of the sacrificial layers. The sacrificial layers are exposed because they extend through the sidewalls of the encapsulating layer. Therefore, no release holes are etched through the top of the encapsulating layer. An etchant then removes the sacrificial layers to free the MEMS device and form the cavity and an opening through the sidewall of the encapsulating layer. Another encapsulating layer may then be deposited to seal the cavity and the opening.
摘要翻译：本文讨论的实施例通常包括在结构内制造MEMS器件的方法。 MEMS器件可以形成在结构上方的空腔中，并且可以在MEMS器件上方发生额外的金属化。空腔可以通过在包围MEMS器件的牺牲层上沉积封装层来形成。然后可以蚀刻封装层以暴露部分牺牲层。牺牲层被暴露，因为它们延伸穿过封装层的侧壁。因此，没有通过封装层的顶部蚀刻释放孔。然后，蚀刻剂去除牺牲层以释放MEMS器件并形成空腔和通过封装层的侧壁的开口。然后可以沉积另外的封装层以密封空腔和开口。

17. 发明申请

WO02073669A3 METHOD OF MAKING LAYERED SUPERLATTICE MATERIAL WITH IMPROVED MICROSTRUCTURE 审中-公开
标题翻译：使用改进的微结构制备层状超导材料的方法
公开(公告)号：WO02073669A3
公开(公告)日：2003-03-20
申请号：PCT/US0145392
申请日：2001-10-30
申请人： SYMETRIX CORP , SEIKO EPSON CORP , KARASAWA JUNICHI , JOSHI VIKRAM
发明人： KARASAWA JUNICHI , JOSHI VIKRAM
IPC分类号： H01L27/105 , H01L21/02 , H01L21/311 , H01L21/314 , H01L21/316 , H01L21/8246
CPC分类号： H01L28/56 , H01L21/31122 , H01L21/31691
摘要： In the manufacture of an integrated circuit, a first electrode (48) is formed on a substrate (28). In a first embodiment, a strontium bismuth tantalate layer (50) and a second electrode (52) are formed on top of the first electrode (48). Prior to the final crystallization anneal, the first electrode (48), the strontium bismuth tantalate layer (50) and the second electrode (52) are patterned. The final crystallization anneal is then performed on the substrate (28). In a second embodiment, a second layer (132) of strontium bismuth tantalate is deposited on top of the strontium bismuth tantalate layer (50) prior to the forming of the second electrode (52) on top of the first and second layers (50), (132). In a third embodiment, a carefully controlled UV baking process is performed on the strontium bismuth tantalate layer (50). In a fourth embodiment, an additional rapid thermal annealing process is performed on a substrate subsequent to the patterning process and prior to the final crystallization annealing process.
摘要翻译：在集成电路的制造中，在基板（28）上形成第一电极（48）。在第一实施例中，在第一电极（48）的顶部上形成钽酸铋铋层（50）和第二电极（52）。在最终结晶退火之前，对第一电极（48），钽酸锶锶层（50）和第二电极（52）进行图案化。然后在衬底（28）上进行最终的结晶退火。在第二实施例中，在第一和第二层（50）的顶部形成第二电极（52）之前，将钽酸铋锶的第二层（132）沉积在钽酸锶钽酸盐层（50）的顶部上，，（132）。在第三实施例中，对钽酸锶钽酸钡层（50）进行仔细控制的UV烘烤工艺。在第四实施例中，在图案化工艺之后并且在最终结晶退火工艺之前，对衬底进行附加的快速热退火工艺。

18. 发明申请

WO2002073680A3 METHOD OF MAKING LAYERED SUPERLATTICE MATERIAL WITH ULTRA-THIN TOP LAYER 审中-公开
公开(公告)号：WO2002073680A3
公开(公告)日：2002-09-19
申请号：PCT/US2002/006980
申请日：2002-03-07
申请人： SYMETRIX CORPORATION , SEIKO EPSON CORPORATION , KARASAWA, Junichi , JOSHI, Vikram
发明人： KARASAWA, Junichi , JOSHI, Vikram
IPC分类号： H01L21/316
摘要： In the manufacture of an integrated circuit memory cell, a strontium bismuth tantalate or strontium bismuth tantalum niobate thin film layer (50) is deposited on a substrate (28, 49) and a carefully controlled UV baking process is performed on the strontium bismuth tantalate layer (50) prior to the deposition of an ultra-thin bismuth tantalate layer (51). A second electrode (52) is formed on top of the ultra-thin bismuth tantalate layer (51).

19. 发明申请

WO2012162420A3 MANAGING DATA INPUT/OUTPUT OPERATIONS 审中-公开
标题翻译：管理数据输入/输出操作
公开(公告)号：WO2012162420A3
公开(公告)日：2013-03-28
申请号：PCT/US2012039189
申请日：2012-05-23
申请人： IO TURBINE LLC , JOSHI VIKRAM , LUAN YANG , APTE MANISH R , VIDWANS HRISHIKESH A , BROWN MICHAEL F
发明人： JOSHI VIKRAM , LUAN YANG , APTE MANISH R , VIDWANS HRISHIKESH A , BROWN MICHAEL F
IPC分类号： G06F9/06 , G06F9/44 , G06F12/08
CPC分类号： G06F9/45558 , G06F12/084 , G06F12/0871 , G06F2009/45579 , G06F2009/45583 , G06F2212/152 , G06F2212/601 , G06F2212/6042
摘要： Systems and methods for managing data input/output operations are described that include virtual machines operating with a shared storage within a host. In such a system, a computer-implemented method is provided for dynamically provisioning cache storage while operating system applications continue to operate, including stalling the virtual machine's local cache storage operations, changing the provision of cache storage size; and resuming the operations of the virtual machine.
摘要翻译：描述了用于管理数据输入/输出操作的系统和方法，其包括在主机内与共享存储器一起操作的虚拟机。在这样的系统中，提供了一种计算机实现的方法，用于在操作系统应用程序继续运行的同时动态配置高速缓存存储，包括停止虚拟机的本地高速缓存存储操作，改变高速缓存存储大小的提供; 并恢复虚拟机的操作。

20. 发明申请

WO2012112710A3 SYSTEMS AND METHODS FOR MANAGING DATA INPUT/OUTPUT OPERATIONS 审中-公开
标题翻译：用于管理数据输入/输出操作的系统和方法
公开(公告)号：WO2012112710A3
公开(公告)日：2013-01-03
申请号：PCT/US2012025295
申请日：2012-02-15
申请人： IO TURBINE LLC , JOSHI VIKRAM , LUAN YANG , APTE MANISH , VIDWANS HRISHIKESH , BROWN MICHAEL
发明人： JOSHI VIKRAM , LUAN YANG , APTE MANISH , VIDWANS HRISHIKESH , BROWN MICHAEL
IPC分类号： G06F12/08 , G06F9/44 , G06F13/14
CPC分类号： G06F12/0246 , G06F9/455 , G06F9/45558 , G06F12/0802 , G06F12/084 , G06F12/0875 , G06F2009/45579 , G06F2212/1021 , G06F2212/452 , G06F2212/604 , G06F2212/7209
摘要： Systems and methods for managing data input/output operations are described. In one aspect, a device driver (218) identifies a data read operation generated by a virtual machine (206-210, 308) in a virtual environment (300). The device driver (218) is located in the virtual machine (206-210, 308) and the data read operation identifies a physical cache address associated with the data requested in the data read operation. A determination is made regarding whether data associated with the data read operation is available in a cache (216, 314, 600) associated with the virtual machine (206-210, 308).
摘要翻译：描述用于管理数据输入/输出操作的系统和方法。在一个方面，设备驱动器（218）识别由虚拟环境（300）中的虚拟机（206-210,308）生成的数据读取操作。设备驱动器（218）位于虚拟机（206-210,308）中，并且数据读取操作识别与在数据读取操作中请求的数据相关联的物理高速缓存地址。确定与与虚拟机（206-210,308）相关联的高速缓存（216,314,600）中与数据读取操作相关联的数据是否可用。

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