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101. 发明申请

WO2014069839A1 차동 입력 방식 통신의 종단 저항 발생 장치 및 차동 입력 방식 통신 장치 审中-公开
标题翻译：用于差分输入模式通信和差分输入模式通信设备的终止电阻产生装置
公开(公告)号：WO2014069839A1
公开(公告)日：2014-05-08
申请号：PCT/KR2013/009536
申请日：2013-10-24
申请人： 주식회사 엘지화학
发明人： 이현철 , 허진석
IPC分类号： H04L29/02 , H04L29/12
CPC分类号： H03K19/0005 , G06F13/4086 , H04L25/0272 , H04L25/0278 , H04L25/0298
摘要： 차동 입력 방식 통신의 종단 저항 발생 장치 및 차동 입력 방식 통신 장치가 개시된다. 본 발명에 따른 차동 입력 방식 통신의 종단 저항 발생 장치는, 제1 그라운드 단자를 포함하고, 상기 제1 그라운드 단자가 그라운드에 연결되었을 때만 동작하는 제1 회로부; 제2 그라운드 단자를 포함하고, 상기 제2 그라운드 단자가 그라운드에 연결되었을 때만 동작하는 제2 회로부; 및 상기 제1 그라운드 단자 및 상기 제2 그라운드 단자 중 하나가 연결되지 않아서 상기 제1 회로부 및 상기 제2 회로부 중 하나만 동작하는 경우, 종단 저항을 발생시키는 종단 저항 발생부를 포함한다.
摘要翻译：公开了一种用于差分输入模式通信的终端电阻产生装置和差分输入模式通信装置。根据本发明的用于差分输入模式通信的终端电阻产生装置包括：第一电路单元，其包括第一接地端子，并且仅当第一接地端子连接到地面时操作; 第二电路单元，其包括第二接地端子，并且仅当所述第二接地端子连接到地面时操作; 以及端接电阻产生单元，仅在第一电路单元或第二电路单元从第一接地端子或第二接地端子未连接起动作时产生终端电阻。

102. 发明申请

WO2013042976A2 유에스비 주변 장치 및 그의 송신 전력 감소 방법 审中-公开
标题翻译： USBR外设和降低其发射功率的方法
公开(公告)号：WO2013042976A2
公开(公告)日：2013-03-28
申请号：PCT/KR2012/007579
申请日：2012-09-21
申请人： 포항공과대학교 산학협력단 , 박홍준 , 성기환
发明人： 박홍준 , 성기환
IPC分类号： G06F1/00 , G06F1/32 , G06F13/14
CPC分类号： G06F1/3253 , G06F3/045 , G06F11/3051 , G06F13/4086 , G06F2213/3854 , H04L25/0264 , H04L25/028 , H04L25/0298 , Y02D10/151 , Y02D50/20
摘要： 본 발명은 송신단 회로 및 수신단 회로에 구비된 종단 저항 값을 전송선로의 특정 임피던스 값보다 크게 함으로써, 송신단 회로의 전력 소모를 감소시킬 수 있는 유에스비 주변 장치 및 그의 송신 전력 감소 방법에 관한 것이다.
摘要翻译：
本发明发送器电路和接收器电路是由电阻值比所述传输线的特性阻抗更大的终止，yueseubi周和其发射功率，以减少的具有发送器电路的功率消耗还原法。

103. 发明申请

WO2012121891A1 CAN BUS AUTOMATIC LINE TERMINATION 审中-公开
标题翻译： CAN总线自动线路终端
公开(公告)号：WO2012121891A1
公开(公告)日：2012-09-13
申请号：PCT/US2012/026252
申请日：2012-02-23
申请人： AMERICAN POWER CONVERSION CORPORATION , DOZIER, Ross, E. , BEAM, Jeffrey, Stephen , TOPP, Eric
发明人： DOZIER, Ross, E. , BEAM, Jeffrey, Stephen , TOPP, Eric
IPC分类号： G06F13/40 , H04L25/02
CPC分类号： G06F13/4086 , H04L25/0298
摘要： A network interface includes a receptacle configured to receive a plug, a first contact and a second contact each disposed in the receptacle, and a combination of a resistive element and a normally closed switch arranged in series with each other. The combination is coupled between the first contact and the second contact, and has a first configuration in which the switch is opened responsive to a presence of the plug within the receptacle, and a second configuration in which the switch is closed responsive to an absence of the plug from the receptacle.
摘要翻译：网络接口包括被配置为接收插头的插座，每个设置在插座中的第一触点和第二触点，以及彼此串联布置的电阻元件和常闭开关的组合。该组合件联接在第一接触件和第二接触件之间，并且具有第一配置，其中开关响应于插头在插座内的存在而打开，以及第二配置，其中开关被关闭，响应于不存在插头从插座。

104. 发明申请

WO2012037086A1 DYNAMIC RAM PHY INTERFACE WITH CONFIGURABLE POWER STATES 审中-公开
标题翻译：具有可配置电源状态的动态RAM PHY接口
公开(公告)号：WO2012037086A1
公开(公告)日：2012-03-22
申请号：PCT/US2011/051345
申请日：2011-09-13
申请人： ADVANCED MICRO DEVICES, INC. , SEARLES, Shawn , HUMPHRIES, Nicholas, T. , AMICK, Brian, W. , REEVES, Richard, W. , CHO, Hanwoo , PETTYJOHN, Ronald, L.
发明人： SEARLES, Shawn , HUMPHRIES, Nicholas, T. , AMICK, Brian, W. , REEVES, Richard, W. , CHO, Hanwoo , PETTYJOHN, Ronald, L.
IPC分类号： G06F13/42 , G06F13/40
CPC分类号： G06F12/00 , G06F1/3275 , G06F13/1689 , G06F13/4072 , G06F13/4086 , Y02D10/14
摘要： A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.
摘要翻译：公开了物理存储器接口（Phy）和操作方法。 Phy接口包括被配置为接收第一功率上下文和第二功率上下文的命令和状态寄存器（CSR）。选择电路被配置为在第一和第二电源上下文之间切换。提供了多个可调延迟元件，每个延迟元件具有响应于所选功率上下文的延迟时间。配置的第一组CSR可以存储第一功率上下文，并且配置的第二组CSR可以存储第二功率上下文。 Phy接口还可以包括多个驱动器，每个驱动器响应于所选择的功率上下文具有可选择的驱动强度。 Phy接口还可以包括多个接收器，每个接收器具有响应于所选择的功率上下文的可选择的终端阻抗。在功率上下文之间切换可导致延迟元件的调整，一个或多个驱动器/接收器的驱动强度和/或终端阻抗。

105. 发明申请

WO2012009068A1 FRDY PULL -UP RESISTOR ACTIVATION 审中-公开
标题翻译： FRDY PULLUP电阻启动
公开(公告)号：WO2012009068A1
公开(公告)日：2012-01-19
申请号：PCT/US2011/039421
申请日：2011-06-07
申请人： SANDISK TECHNOLOGIES INC. , CHENG, Steven, S. , HWANG, Peter , CHANG, Annie, C.
发明人： CHENG, Steven, S. , HWANG, Peter , CHANG, Annie, C.
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4239 , G06F13/4086 , Y02D10/14 , Y02D10/151
摘要： A method and apparatus for reducing power consumption during an operation in a non-volatile storage device is disclosed. A non-volatile storage device controller that is in communication with a non-volatile memory in the non-volatile storage device receives a characteristic corresponding to a time duration required for the non-volatile memory to complete an operation. The controller disables a circuit that indicates when an operation by the non-volatile memory is complete. The controller then initiates the operation in the non-volatile memory, and maintains the circuit in a disabled state for a first predetermined time that is a portion of the time duration. The controller enables the circuit upon expiration of the first predetermined time and prior to the completion of the operation. The controller receives an indication of the completion of the operation via the circuit.
摘要翻译：公开了一种用于在非易失性存储装置中的操作期间降低功耗的方法和装置。与非易失性存储设备中的非易失性存储器通信的非易失性存储设备控制器接收与非易失性存储器完成操作所需的持续时间相对应的特性。控制器禁用指示非易失性存储器的操作何时完成的电路。然后，控制器在非易失性存储器中启动操作，并且将电路保持在禁用状态，作为持续时间的一部分的第一预定时间。控制器在第一预定时间到期并且在完成操作之前启用该电路。控制器通过电路接收完成操作的指示。

106. 发明申请

WO2010144624A1 PROGRAMMING OF DIMM TERMINATION RESISTANCE VALUES 审中-公开
标题翻译： DIMM终止电阻值的编程
公开(公告)号：WO2010144624A1
公开(公告)日：2010-12-16
申请号：PCT/US2010/038041
申请日：2010-06-09
申请人： GOOGLE INC. , FEROLITO, Philip Arnold , ROSENBAND, Daniel L. , WANG, David T. , SMITH, Michael John Sebastian
发明人： FEROLITO, Philip Arnold , ROSENBAND, Daniel L. , WANG, David T. , SMITH, Michael John Sebastian
IPC分类号： G06F13/40
CPC分类号： G06F13/4086 , Y02D10/14 , Y02D10/151
摘要： Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the plurality of memory circuits and to communicate with a memory controller; and a transmission line electrically coupling the interface circuit to a memory controller, wherein the interface circuit is operable to terminate the transmission line with a single termination resistance that is selected based on a plurality of resistance-setting commands received from the memory controller.
摘要翻译：提供了用于在存储器模块中提供终端电阻的系统，方法和装置，包括计算机程序产品。提供了一种包括多个存储电路的装置; 接口电路，其可操作以与所述多个存储器电路通信并与存储器控制器通信; 以及将接口电路电耦合到存储器控制器的传输线，其中所述接口电路可操作以基于从所述存储器控制器接收的多个电阻设置命令而选择的单个终端电阻终止所述传输线。

107. 发明申请

WO2009085417A2 MULTI-BAND, MULTI-DROP CHIP TO CHIP SIGNALING 审中-公开
标题翻译：多带，多芯片切片信号
公开(公告)号：WO2009085417A2
公开(公告)日：2009-07-09
申请号：PCT/US2008083231
申请日：2008-11-12
申请人： RAMBUS INC , ZERBE JARED L , STOJANOVIC VLADIMIR M , KOLLIPARA RAVINDRANATH , BEYENE WENDEMAGEGNEHU , AMIRKHANY AMIR , GARLEPP BRUNO
发明人： ZERBE JARED L , STOJANOVIC VLADIMIR M , KOLLIPARA RAVINDRANATH , BEYENE WENDEMAGEGNEHU , AMIRKHANY AMIR , GARLEPP BRUNO
IPC分类号： H04L25/08 , G06F13/40 , H04L5/06
CPC分类号： H04L5/06 , G06F13/4086 , H04L25/085
摘要： A multi-band, multi-drop signaling system. First, second and third integrated circuit devices are coupled to one another via a common signaling link. The first integrated circuit device includes a first transmitter to transmit a baseband signal via the signaling link and a second transmitter to transmit a signal centered around a non-zero frequency via the signaling link.
摘要翻译：一个多频段，多点信号系统。首先，第二和第三集成电路器件通过公共信令链路相互耦合。第一集成电路装置包括经由信令链路发送基带信号的第一发射机和经由信令链路发送以非零频率为中心的信号的第二发射机。

108. 发明申请

WO2005119471A3 BUS CONTROLLER 审中-公开
标题翻译：总线控制器
公开(公告)号：WO2005119471A3
公开(公告)日：2006-04-20
申请号：PCT/US2005019026
申请日：2005-06-01
申请人： HEWLETT PACKARD DEVELOPMENT CO , ATKINSON LEE W
发明人： ATKINSON LEE W
IPC分类号： G06F13/40 , H03K19/003
CPC分类号： G06F13/4072 , G06F13/4086 , Y02D10/14 , Y02D10/151
摘要： A bus has two power consumption modes. A variable bus termination impedance is controlled to provide different bus termination impedances. A controller is coupled to the bus and includes a variable clock having different frequencies that are selectively provided to the controller. The impedance is increased or decreased responsive to the frequency being provided to the controller.
摘要翻译：总线有两种功耗模式。控制可变总线终端阻抗以提供不同的总线端接阻抗。控制器耦合到总线并且包括可选择地提供给控制器的具有不同频率的可变时钟。响应于提供给控制器的频率，阻抗增加或减小。

109. 发明申请

WO2006011974A2 HIGH SPEED MEMORY MODULES 审中-公开
标题翻译：高速内存模块
公开(公告)号：WO2006011974A2
公开(公告)日：2006-02-02
申请号：PCT/US2005/020653
申请日：2005-06-09
申请人： INTEL CORPORATION , CHANG, Ge
发明人： CHANG, Ge
IPC分类号： G11C7/00
CPC分类号： G06F13/4086
摘要： Apparatus and method for producing memory modules having a plurality of branches connected to a memory bus, each branch containing at least one dynamic random access memory (DRAM) device or synchronous random access memory (SDRAM) device connected to the memory bus via at least one transmission signal (TS) line and/or at least one sub-transmission signal (STS) line. The memory modules include at least one branch containing a resistor connected to the TS line or STS line and connected series with the DRAM device or SDRAM device and connected to the memory bus. A computing system implementing the memory modules is also discussed.
摘要翻译：用于产生具有连接到存储器总线的多个分支的存储器模块的设备和方法，每个分支包含连接到存储器总线的至少一个动态随机存取存储器（DRAM）设备或同步随机存取存储器（SDRAM）设备经由至少一个传输信号（TS）线和/或至少一个子传输信号（STS）线连接到存储器总线。存储器模块包括至少一个分支，该分支包含连接到TS线或STS线并与DRAM装置或SDRAM装置串联并连接到存储器总线的电阻器。还讨论了实现存储器模块的计算系统。

110. 发明申请

WO2005119471A2 BUS CONTROLLER 审中-公开
标题翻译：总线控制器
公开(公告)号：WO2005119471A2
公开(公告)日：2005-12-15
申请号：PCT/US2005/019026
申请日：2005-06-01
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , ATKINSON, Lee, W.
发明人： ATKINSON, Lee, W.
IPC分类号： G06F13/40
CPC分类号： G06F13/4072 , G06F13/4086 , Y02D10/14 , Y02D10/151
摘要： A bus has two power consumption modes. A variable bus termination impedance is controlled to provide different bus termination impedances. A controller is coupled to the bus and includes a variable clock having different frequencies that are selectively provided to the controller. The impedance is increased or decreased responsive to the frequency being provided to the controller.
摘要翻译：总线有两种功耗模式。控制可变总线终端阻抗以提供不同的总线端接阻抗。控制器耦合到总线并且包括可选择地提供给控制器的具有不同频率的可变时钟。响应于提供给控制器的频率，阻抗增加或减小。

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