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91. 发明申请

WO1997004546A1 METHOD AND APPARATUS FOR REDUCING INFORMATION LOSS IN A COMMUNICATIONS NETWORK 审中-公开
标题翻译：减少通信网络信息丢失的方法和装置
公开(公告)号：WO1997004546A1
公开(公告)日：1997-02-06
申请号：PCT/US1996011947
申请日：1996-07-18
申请人： ASCOM NEXION INC.
发明人： ASCOM NEXION INC. , McCLURE, Robert, B. , CALDARA, Stephen, A. , HAUSER, Stephen, A. , MANNING, Thomas, A.
IPC分类号： H04J03/24
CPC分类号： H04L49/253 , G06F15/17375 , H04J3/0682 , H04J3/0685 , H04L7/046 , H04L12/4608 , H04L12/5601 , H04L12/5602 , H04L41/0896 , H04L47/10 , H04L47/11 , H04L47/18 , H04L47/26 , H04L47/266 , H04L47/29 , H04L47/30 , H04L47/621 , H04L49/106 , H04L49/107 , H04L49/153 , H04L49/1553 , H04L49/1576 , H04L49/203 , H04L49/255 , H04L49/256 , H04L49/3081 , H04L49/309 , H04L49/455 , H04L49/552 , H04L49/555 , H04L69/32 , H04L69/324 , H04L2012/5614 , H04L2012/5616 , H04L2012/5627 , H04L2012/5628 , H04L2012/5629 , H04L2012/5631 , H04L2012/5632 , H04L2012/5634 , H04L2012/5635 , H04L2012/5642 , H04L2012/5643 , H04L2012/5647 , H04L2012/5648 , H04L2012/5649 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/5681 , H04L2012/5682 , H04L2012/5683 , H04L2012/5685 , H04Q11/0478 , H04W28/14
摘要： The invention reduces information loss in a communications network (10). A plurality of virtual connections are sent over a first link from a first node in the communications network (10) to a second node. The nodes comprise a plurality of input queues coupled to a switching network, which is coupled to a plurality of output queues. Each virtual connection is associated with a first output queue in the first node, a second input queue in the second node, and a second output queue in the second node. A connection feedback signal is provided from the second node to the first node with status of the second input queue so as to control the flow of information between the nodes. A switch feedback signal is provided between from the second output queue to the second input queue with status of the second output queue to control the flow of information through the switch of the second mode.
摘要翻译：本发明减少通信网络（10）中的信息丢失。多个虚拟连接通过第一链路从通信网络（10）中的第一节点发送到第二节点。节点包括耦合到交换网络的多个输入队列，其耦合到多个输出队列。每个虚拟连接与第一节点中的第一输出队列，第二节点中的第二输入队列和第二节点中的第二输出队列相关联。从第二节点向具有第二输入队列状态的第一节点提供连接反馈信号，以便控制节点之间的信息流。在从第二输出队列到具有第二输出队列的状态的第二输入队列之间提供开关反馈信号，以控制通过第二模式的切换的信息流。

92. 发明申请

WO1997004545A1 METHOD OF DETERMINING A RECEIVER TIME AT THE MOMENT OF RECEPTION OF A TRANSMISSION TIME MARK IN RECEIVED DATA ELEMENTS 审中-公开
标题翻译：用于确定接收器时间，用于接收在时间法所接收的数据元素手册包含的传输时间BRAND
公开(公告)号：WO1997004545A1
公开(公告)日：1997-02-06
申请号：PCT/DE1995000969
申请日：1995-07-24
申请人： SIEMENS AKTIENGESELLSCHAFT , HÜBL, Markus
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H04J03/06
CPC分类号： H04N21/4302 , H04J3/0632 , H04J3/0685 , H04L7/04 , H04N21/242
摘要： The invention concerns a method of determining a receiver time at the moment of reception of a transmisison time mark in received data elements, the method comprising the following steps: storage of a plurality of data elements received in succession; storage of a receiver time corresponding to a data element reception moment; searching of the stored data elements for a transmisison time mark; and determining the receiver time corresponding to the reception moment of the transmisison time mark by means of the stored reception time(s). The method is characterized in that only the receiver time corresponding to the reception moment of a single data element is stored for a given or indeterminate number of stored data elements; and in that the receiver time corresponding to the reception moment of the transmission time mark is determined by extrapolation or interpolation on the basis of the stored receiver time(s).
摘要翻译：我们将描述一种方法，用于确定在包含在接收的数据元素的传输时间标记的接收定时的接收机时钟时间，包括以下步骤：存储多个连续接收的数据元素的，存储对应于接收器的时钟时间的数据元素接收时间，搜索的传输时间标记在存储的数据元素，并且所述确定的所存储的接收机时钟时间（s）的基础上对应的接收机时钟时间的传输时间标记的接收定时。所描述的方法的特征在于，每确定或不确定的多个存储的数据元素的唯一对应的接收机时钟时间被存储在单个数据元素的接收时间，并且所述传输时间标记的所存储的接收机时钟时间（s）通过基于相应的接收机时钟时间接收定时的确定发生细胞外或内插。

93. 发明申请

WO1997004544A1 NETWORK SWITCH UTILIZING CENTRALIZED AND PARTITIONED MEMORY FOR CONNECTION TOPOLOGY INFORMATION STORAGE 审中-公开
标题翻译：网络开关利用集中和分离的存储器进行连接拓扑信息存储
公开(公告)号：WO1997004544A1
公开(公告)日：1997-02-06
申请号：PCT/US1996011932
申请日：1996-07-18
申请人： ASCOM NEXION INC. , MANNING, Thomas, A. , CALDARA, Stephen, A. , HAUSER, Stephen, A. , SHERMAN, Alan, D.
发明人： ASCOM NEXION INC.
IPC分类号： H04J03/02
CPC分类号： H04L47/18 , G06F15/17375 , H04J3/0682 , H04J3/0685 , H04L7/046 , H04L12/4608 , H04L12/5601 , H04L12/5602 , H04L41/0896 , H04L47/10 , H04L47/11 , H04L47/26 , H04L47/266 , H04L47/29 , H04L47/30 , H04L47/621 , H04L49/106 , H04L49/107 , H04L49/153 , H04L49/1553 , H04L49/1576 , H04L49/203 , H04L49/253 , H04L49/255 , H04L49/256 , H04L49/3081 , H04L49/309 , H04L49/455 , H04L49/552 , H04L49/555 , H04L69/32 , H04L69/324 , H04L2012/5614 , H04L2012/5616 , H04L2012/5627 , H04L2012/5628 , H04L2012/5629 , H04L2012/5631 , H04L2012/5632 , H04L2012/5634 , H04L2012/5635 , H04L2012/5642 , H04L2012/5643 , H04L2012/5647 , H04L2012/5648 , H04L2012/5649 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/5681 , H04L2012/5682 , H04L2012/5683 , H04L2012/5685 , H04Q11/0478
摘要： A network switch utilizing centralized and partitioned memory for storing connection topology information. The switch includes at least one input port (14), at least one output port (18) and a central switch fabric (28) interconnecting the input port and output port, with the connection topology memory centralized at the switch fabric. The central switch fabric includes at least one input side translator (24) associated with a predetermined number of input ports and at least one output port side translator (40) associated with a predetermined number of output ports. The connection topology memory (26, 44) is distributed among the at least one input side translator and the at least one output side translator. With this arrangement, memory bandwidth requirements associated with connection topology look-up operations are distributed and scaling the number of ports is facilitated.
摘要翻译：一种利用集中式和分区式存储器存储连接拓扑信息的网络交换机。交换机包括至少一个输入端口（14），将输入端口和输出端口互连的至少一个输出端口（18）和中央交换结构（28）与连接拓扑存储器集中在交换结构处。中央交换结构包括与预定数量的输入端口相关联的至少一个输入侧转换器（24）和与预定数量的输出端口相关联的至少一个输出端口侧转换器（40）。连接拓扑存储器（26,44）分布在至少一个输入侧转换器和至少一个输出侧转换器中。通过这种安排，与连接拓扑查找操作相关联的存储器带宽需求被分配并且缩短了端口数量。

94. 发明申请

WO9704543A2 ALLOCATED AND DYNAMIC SWITCH FLOW CONTROL 审中-公开
标题翻译：分配和动态开关流量控制
公开(公告)号：WO9704543A2
公开(公告)日：1997-02-06
申请号：PCT/US9611942
申请日：1996-07-18
申请人： ASCOM NEXION INC , CALDARA STEPHEN A , HAUSER STEPHEN A , MANNING THOMAS A
发明人： CALDARA STEPHEN A , HAUSER STEPHEN A , MANNING THOMAS A
IPC分类号： G06F12/02 , G06F9/46 , G06F15/173 , H04J3/06 , H04L1/22 , H04L7/04 , H04L12/18 , H04L12/24 , H04L12/46 , H04L12/54 , H04L13/08 , H04L29/06 , H04L29/08 , H04M3/00 , H04M3/08 , H04M3/22 , H04Q3/00 , H04Q3/545 , H04Q11/04 , H04J
CPC分类号： H04L47/18 , G06F15/17375 , H04J3/0682 , H04J3/0685 , H04L7/046 , H04L12/4608 , H04L12/5601 , H04L12/5602 , H04L41/0896 , H04L47/10 , H04L47/11 , H04L47/26 , H04L47/266 , H04L47/29 , H04L47/30 , H04L47/621 , H04L49/106 , H04L49/107 , H04L49/153 , H04L49/1553 , H04L49/1576 , H04L49/203 , H04L49/253 , H04L49/255 , H04L49/256 , H04L49/3081 , H04L49/309 , H04L49/455 , H04L49/552 , H04L49/555 , H04L69/32 , H04L69/324 , H04L2012/5614 , H04L2012/5616 , H04L2012/5627 , H04L2012/5628 , H04L2012/5629 , H04L2012/5631 , H04L2012/5632 , H04L2012/5634 , H04L2012/5635 , H04L2012/5642 , H04L2012/5643 , H04L2012/5647 , H04L2012/5648 , H04L2012/5649 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/5681 , H04L2012/5682 , H04L2012/5683 , H04L2012/5685 , H04Q11/0478
摘要： A method and apparatus are disclosed for eliminating cell loss in a network switch through the use of flow control of both allocated and dynamic bandwidth. When output buffers in the switch become filled to a predetermined threshold level a feedback message is provided to input buffers to prevent transmission of cells from the input buffers to the output buffers. In order to provide connection and traffic type isolation the buffers are grouped into queues and flow control may be implemented on a per queue basis. The feedback message is a digital signal including an ACCEPT/REJECT message and a NO-OP/XOFF message. An XOFF message can be received while transmitting via allocated bandwith or dynamic bandwidth. In particular, an XOFF (allocated) message may be received with regard to allocated bandwidth and an XOFF (dynamic) message may be received with regard to dynamic bandwidth. An optional tagging technique may be employed to distinguish between requests for dynamic and allocated bandwidth. When ACCEPT is received by the requesting input queue the cell is transferred to the output queue. When REJECT is received by the requesting queue the cell is not transferred. When XOFF (dynamic) is received by the requesting input queue further requests to transfer to that output queue by the requesting input queue using dynamic bandwidth are halted until receipt of an XON message from that output queue. When XOFF (allocated) is received by the requesting input queue further requests to transfer to that output queue by the requesting input queue using allocated bandwidth are halted until receipt of an XON message from that output queue.
摘要翻译：公开了一种通过使用分配和动态带宽的流量控制来消除网络交换机中的信元丢失的方法和装置。当交换机中的输出缓冲器被填充到预定阈值电平时，将反馈消息提供给输入缓冲器以防止将单元从输入缓冲器传输到输出缓冲器。为了提供连接和流量类型隔离，缓冲区被分组成队列，并且流控制可以在每个队列的基础上实现。反馈消息是包括ACCEPT / REJECT消息和NO-OP / XOFF消息的数字信号。在通过分配的带宽或动态带宽发送时可以接收XOFF消息。特别地，可以针对分配的带宽接收XOFF（分配）消息，并且可以关于动态带宽接收XOFF（动态）消息。可以采用可选的标记技术来区分对动态和分配带宽的请求。当请求输入队列接收到ACCEPT时，单元被传送到输出队列。当请求队列接收到REJECT时，单元不被传送。当请求输入队列接收到XOFF（动态）时，停止通过请求输入队列使用动态带宽传送到该输出队列的请求，直到从该输出队列接收到XON消息。当请求输入队列接收到XOFF（分配））时，暂停使用分配带宽的请求输入队列向该输出队列传送的请求，直到从该输出队列接收到XON消息。

95. 发明申请

WO1997003549A2 PRIORITIZED ACCESS TO SHARED BUFFERS 审中-公开
标题翻译：优先访问共享缓冲区
公开(公告)号：WO1997003549A2
公开(公告)日：1997-02-06
申请号：PCT/US1996011920
申请日：1996-07-18
申请人： ASCOM NEXION INC. , HAUSER, Stephen, A. , CALDARA, Stephen, A. , MANNING, Thomas, A.
发明人： ASCOM NEXION INC.
IPC分类号： G06F12/02 , G06F9/46 , G06F15/173 , H04J3/06 , H04L1/22 , H04L7/04 , H04L12/18 , H04L12/24 , H04L12/46 , H04L12/54 , H04L13/08 , H04L29/06 , H04L29/08 , H04M3/00 , H04M3/08 , H04M3/22 , H04Q3/00 , H04Q3/545 , H04Q11/04
CPC分类号： H04L49/253 , G06F15/17375 , H04J3/0682 , H04J3/0685 , H04L7/046 , H04L12/4608 , H04L12/5601 , H04L12/5602 , H04L41/0896 , H04L47/10 , H04L47/11 , H04L47/18 , H04L47/26 , H04L47/266 , H04L47/29 , H04L47/30 , H04L47/621 , H04L49/106 , H04L49/107 , H04L49/153 , H04L49/1553 , H04L49/1576 , H04L49/203 , H04L49/255 , H04L49/256 , H04L49/3081 , H04L49/309 , H04L49/455 , H04L49/552 , H04L49/555 , H04L69/32 , H04L69/324 , H04L2012/5614 , H04L2012/5616 , H04L2012/5627 , H04L2012/5628 , H04L2012/5629 , H04L2012/5631 , H04L2012/5632 , H04L2012/5634 , H04L2012/5635 , H04L2012/5642 , H04L2012/5643 , H04L2012/5647 , H04L2012/5648 , H04L2012/5649 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/5681 , H04L2012/5682 , H04L2012/5683 , H04L2012/5685 , H04Q11/0478 , H04W28/14
摘要： In a link-level flow controlled system, a method and apparatus providing the ability to partition a buffer resource among multiple prioritized buffer subsets through definition of at least one threshold, the buffer resource being shared by a plurality of connections. Different categories of service levels, in terms of delay bounds, are thus enabled. The presently disclosed link-level flow controlled system provides for zero cell loss. The shared buffer resource is divided among N priority pools, defined by N-1 threshold levels, each priority pool attributable to a respective category of service. Link-level counters and registers, disposed in a transmit element, as well as an indication of priority level associated with each connection, are employed in realizing the shared buffer resource.
摘要翻译：在链路级流控制系统中，提供通过定义至少一个阈值在多个优先化缓冲器子集中划分缓冲器资源的能力的方法和装置，所述缓冲器资源由多个连接共享。因此，在延迟范围方面，可以实现不同类别的服务级别。目前公开的链路级流控制系统提供零信元丢失。共享缓冲区资源划分为N个优先级池，由N-1个阈值级别定义，每个优先级池归因于各自的服务类别。布置在发送元件中的链路级计数器和寄存器以及与每个连接相关联的优先级的指示被用于实现共享缓冲器资源。

96. 发明申请

WO1996035275A1 RETIMING ARRANGEMENT FOR SDH DATA TRANSMISSION SYSTEM 审中-公开
标题翻译： SDH数据传输系统的撤销安排
公开(公告)号：WO1996035275A1
公开(公告)日：1996-11-07
申请号：PCT/GB1996001071
申请日：1996-05-03
申请人： GPT LIMITED , SLATER, Iain, James
发明人： GPT LIMITED
IPC分类号： H04J03/07
CPC分类号： H04J3/0685 , H04J3/076
摘要： A retiming arrangement for use in a demultiplexer in an SDH data transmission system uses Bit Justification data, and not Pointer data, to modify a recovered clock signal and generate a clock signal for retiming purposes. The invention is especially for use in enabling third party users to carry primary rate timing data across an SDH network.
摘要翻译：在SDH数据传输系统中用于解复用器的重定时装置使用位对齐数据而不是指针数据来修改恢复的时钟信号并产生用于重定时目的的时钟信号。本发明特别用于使第三方用户能够跨SDH网络传送主速率定时数据。

97. 发明申请

WO1996005559A1 INTELLIGENT COMMUNICATIONS COPROCESSOR 审中-公开
标题翻译：智能通信协调员
公开(公告)号：WO1996005559A1
公开(公告)日：1996-02-22
申请号：PCT/US1995010065
申请日：1995-08-09
申请人： APPLE COMPUTER, INC. , LYNCH, John , NICHOLS, James, B. , DEVON, Mark , SOESBE, Jeff
发明人： APPLE COMPUTER, INC.
IPC分类号： G06F13/38
CPC分类号： G06F13/385 , H04J3/0685 , H04L7/02
摘要： An intelligent communications coprocessor connects computer workstations to moderate-bandwidth (up to 2 megabits/second) digital communications services. In particular, such communications services include but are not limited to Integrated Services Digital Network (ISDN) or Private-Branch Exchange (PBX) communications facilities. The communications coprocessor takes advantage of certain host resources including, preferably, signal processing capabilities of the computer, the computer's power supply and a generalized, high-speed computer/peripheral serial interface. System cost for digital communications over such communications facilities is therefore reduced. Furthermore, the communications coprocessor can be used to support the transmission of arbitrary real-time, synchronous data streams as encountered in voice and video transmission services. This capability is required for many applications including voice recognition, text-to-speech, and videoconferencing. The communications coprocessor is tightly coupled to the host computer so as to allow real-time digital signal processing of the real-time data stream conveyed by the coprocessor. Finally, the invention can be dynamically reconfigured using an associated host-coprocessor protocol, allowing software upgrades and adaptation to special communications requirements.
摘要翻译：智能通信协处理器将计算机工作站连接到中等带宽（高达2兆比特/秒）的数字通信服务。特别地，这样的通信服务包括但不限于综合业务数字网（ISDN）或私交交换（PBX）通信设施。通信协处理器利用某些主机资源，优选地包括计算机的信号处理能力，计算机的电源和广义的高速计算机/外围串行接口。因此减少了在这种通信设施上进行数字通信的系统成本。此外，通信协处理器可以用于支持在语音和视频传输服务中遇到的任意实时的同步数据流的传输。该功能对于包括语音识别，文本到语音和视频会议在内的许多应用是必需的。通信协处理器紧密耦合到主计算机，以允许由协处理器传送的实时数据流的实时数字信号处理。最后，本发明可以使用关联的主机 - 协处理器协议进行动态重新配置，允许软件升级和适应特殊的通信要求。

98. 发明申请

WO1995030318A2 ATM SWITCHING SYSTEM 审中-公开
标题翻译：自动柜员机切换系统
公开(公告)号：WO1995030318A2
公开(公告)日：1995-11-09
申请号：PCT/CA1995000248
申请日：1995-04-28
申请人： NEWBRIDGE NETWORKS CORPORATION , CHOW, Henry , GASSEWITZ, Michael , GHADBANE, Jim , MITCHELL, Charles , BISSON, Germain , BEWS, Steve
发明人： NEWBRIDGE NETWORKS CORPORATION
IPC分类号： H04Q11/04
CPC分类号： H04L12/5601 , H04J3/0685 , H04L12/56 , H04L49/107 , H04L49/153 , H04L49/203 , H04L49/255 , H04L49/256 , H04L49/309 , H04L2012/561 , H04L2012/5627 , H04L2012/5651 , H04L2012/5652 , H04L2012/5674 , H04Q11/0478
摘要： A communication system comprising a hub slot adapted to receive any one of a plurality of hub cards for receiving and transmitting data cells; a plurality of universal card slots; a plurality of interface cards insertable into any one of said plurality of universal card slots for receiving incoming ones of said data cells containing data and transmitting outgoing ones of said data cells containing data; an add bus having respective data links connected between individual ones of said universal card slots and said hub slot for receiving said outgoing ones of said data cells from said plurality of interface cards and transmitting said outgoing ones of said data cells to said hub slot; a drop bus having a single data link connected between all of said universal card slots and said hub slot for transmitting said incoming ones of said data cells from said hub slot to said plurality of interface cards; and means within each of said interface cards for filtering said incoming ones of said data cells from said drop bus and thereby routing said data cells to an appropriate one or more of said plurality of interface cards.
摘要翻译：一种通信系统，包括适于接收用于接收和发送数据信元的多个集线器卡中的任何一个的集线器槽; 多个通用卡槽; 多个接口卡可插入到所述多个通用卡插槽中的任何一个，用于接收包含数据的所述数据单元的输入信号，并发送包含数据的所述数据单元的输出信号; 一个添加总线，其具有连接在所述通用卡槽中的各个数据链路和所述集线器插槽之间的数据链路，用于从所述多个接口卡接收所述数据信元中的所述输出数据信元，并将所述数据信元中的所述数据信元发送到所述集线器槽; 连接在所有所述通用卡槽和所述集线器槽之间的单个数据链路的总线，用于将所述数据信元中的所述数据信元从所述集线器槽传输到所述多个接口卡; 以及每个所述接口卡内的装置，用于从所述下拉总线过滤所述数据信元中的所述输入的一个，从而将所述数据信元路由到所述多个接口卡中的一个或多个接口卡。

99. 发明申请

WO1995027351A1 ADAPTIVE BOUNDARY BUFFERS 审中-公开
标题翻译：自适应边界缓冲区
公开(公告)号：WO1995027351A1
公开(公告)日：1995-10-12
申请号：PCT/GB1995000695
申请日：1995-03-28
申请人： GPT LIMITED , CHOPPING, Geoffrey
发明人： GPT LIMITED
IPC分类号： H04J03/06
CPC分类号： H04J3/0685 , H04J2203/005 , H04J2203/0089
摘要： The fitting of boundary buffers on the exit from a telecommunications network can greatly reduce the relative wander. Adaptive boundary buffers have a phase adjusting means, having means for determining the phase error between a recovered line clock and a recovered return clock from receiving equipment of a telecommunications system, the phase of the recovered return clock being advanced or retarded by the value of the phase error and the phase of the recovered line clock being retarded or advanced respectively by less than the value of the phase error, so as to produce a phase adjusted Output Line Clock.
摘要翻译：在电信网络出口处的边界缓冲器的拟合可以大大减少相对漂移。自适应边界缓冲器具有相位调整装置，具有用于确定恢复的线路时钟与来自电信系统的接收设备的恢复的返回时钟之间的相位误差的装置，恢复的返回时钟的相位被提前或延迟的值相位误差和恢复的线路时钟的相位分别被延迟或提前小于相位误差的值，以产生相位调整的输出线时钟。

100. 发明申请

WO1995018493A1 INTEGRATED MUTLI-FABRIC DIGITAL CROSS-CONNECT TIMING ARCHITECTURE 审中-公开
标题翻译：集成的MULLI-FABRIC数字交叉连接时序架构
公开(公告)号：WO1995018493A1
公开(公告)日：1995-07-06
申请号：PCT/US1994014738
申请日：1994-12-21
申请人： DSC COMMUNICATIONS CORPORATION
发明人： DSC COMMUNICATIONS CORPORATION , READ, E., Lawrence , HANSON, Gary, D. , SENSEL, Steven, D. , SCHRODER, Richard
IPC分类号： H04J03/06
CPC分类号： H04L49/104 , H04J3/0685 , H04J3/1611 , H04J2203/0041 , H04J2203/0089 , H04L49/3081 , H04Q11/04 , H04Q11/0478
摘要： A timing architecture for integrating broadband, wideband, and narrowband subsystems (14-18) employs a broadland time base (100) having a first frequency, a wideband time base (102) having a second frequency, and a narrowband time base (104) having a third frequency. The broadband, wideband and narrowband time bases (100-104) are independent from one another when the intergrated subsystems (14-18) are not co-located. Frequency justification is provided at the interfaces between the broadband and wideband time bases (100, 102), and between the wideband and narrowband time bases (102, 104). Phase alignment circuitry and methods are used to adjust the phases of signals wherever signal multiplexing and redundant equipment switching are provided within the time bases (100-104).
摘要翻译：用于集成宽带，宽带和窄带子系统（14-18）的定时架构采用具有第一频率，具有第二频率的宽带时基（102）和窄带时基（104）的宽带时基（100）具有第三频率。当整合子系统（14-18）不在同一地点时，宽带，宽带和窄带时基（100-104）彼此独立。在宽带和宽带时基（100,102）之间以及宽带和窄带时基（102,104）之间的接口处提供频率调整。相位对准电路和方法用于调整在时基（100-104）内提供信号复用和冗余设备切换的信号的相位。

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