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91. 发明申请

WO2010120685A8 SCRUBBER CLEAN BEFORE OXIDE CHEMICAL MECHANICAL POLISH (CMP) FOR REDUCED MICROSCRATCHES AND IMPROVED YIELDS 审中-公开
标题翻译：氧化物化学机械抛光（CMP）之前的清洁清洁用于减少微阵列和改进的YIELDS
公开(公告)号：WO2010120685A8
公开(公告)日：2011-08-18
申请号：PCT/US2010030734
申请日：2010-04-12
申请人： MICROCHIP TECH INC , WILLIAMS JACOB L
发明人： WILLIAMS JACOB L
IPC分类号： H01L21/02 , H01L21/3105
CPC分类号： H01L21/02065
摘要： A method for fabricating semiconductors is provided that includes an oxide chemical mechanical polish (CMP) step. Prior to performing the CMP of an integrated circuit semiconductor silicon wafer, a number of steps are performed. The silicon wafer is scrubbed with a brush using a liquid cleaner. The silicon wafer is rinsed with deionized water (DIW). Finally, the silicon wafer is dried.
摘要翻译：提供一种制造半导体的方法，其包括氧化物化学机械抛光（CMP）步骤。在进行集成电路半导体硅晶片的CMP之前，进行多个步骤。使用液体清洁器用刷子擦洗硅晶片。用去离子水（DIW）漂洗硅晶片。最后，将硅晶片干燥。

92. 发明申请

WO2009151904A3 CAPACITIVE VOLTAGE DIVIDER TOUCH SENSOR 审中-公开
标题翻译：电容式分路器触摸传感器
公开(公告)号：WO2009151904A3
公开(公告)日：2010-11-25
申请号：PCT/US2009044694
申请日：2009-05-20
申请人： MICROCHIP TECH INC , IRKLIY ALEX
发明人： IRKLIY ALEX
IPC分类号： H03K17/96 , G06F3/044
CPC分类号： G06F3/044 , G01D5/24 , G01R27/2605 , H03K17/955 , H03K2217/960725
摘要： A system for measuring capacitance has a measurement circuit with a first reference capacitor connected to a first node and to a second node. Each of the nodes is connected to a unit operable to apply a reference voltage or ground to one of the nodes. Each node has a first pad connected to the first node and a unit operable to measure voltage between the first node and second node.
摘要翻译：用于测量电容的系统具有连接到第一节点和第二节点的第一参考电容器的测量电路。每个节点连接到可操作以将参考电压或接地施加到节点之一的单元。每个节点具有连接到第一节点的第一焊盘和可操作以测量第一节点和第二节点之间的电压的单元。

93. 发明申请

WO2010056719A3 MICROCONTROLLER WITH CONFIGURABLE LOGIC ARRAY 审中-公开
标题翻译：具有可配置逻辑阵列的微控制器
公开(公告)号：WO2010056719A3
公开(公告)日：2010-07-08
申请号：PCT/US2009063990
申请日：2009-11-11
申请人： MICROCHIP TECH INC , LAHTI GREGG , DAWSON STEVEN
发明人： LAHTI GREGG , DAWSON STEVEN
IPC分类号： G06F13/24 , G06F15/78
CPC分类号： G06F13/24
摘要： A microcontroller may have a central processing unit (CPU); a programmable logic device receiving input signals and having input/outputs coupled with external pins, and an interrupt control unit receiving at least one of the internal input signals or being coupled with at least one of the input/outputs and generating an interrupt signal fed to the CPU.
摘要翻译：微控制器可以具有中央处理单元（CPU）; 可编程逻辑器件，其接收输入信号并具有与外部引脚耦合的输入/输出;以及中断控制单元，其接收所述内部输入信号中的至少一个或与所述输入/输出中的至少一个耦合，并产生馈送到 CPU。

94. 发明申请

WO2010027997A3 HIGH SPEED I2C BUS 审中-公开
标题翻译：高速I2C总线
公开(公告)号：WO2010027997A3
公开(公告)日：2010-05-20
申请号：PCT/US2009055660
申请日：2009-09-02
申请人： MICROCHIP TECH INC , STEPHENS VERN , WALTERS BRET
发明人： STEPHENS VERN , WALTERS BRET
IPC分类号： G06F13/42 , G06F13/40
CPC分类号： G06F13/4286 , G06F2213/0016 , Y02D10/14 , Y02D10/151
摘要： An I2C-bus compatible device when functioning as a clock master comprises a transient active pull-up I2C ("TAP-I2C") logic module having high side driver transistors, e.g., P-channel field effect transistors (FETs), coupled between a positive supply voltage and respective serial data ("SDA") and serial clock ("SCL") lines on the I2C bus. The high side output driver transistors for the SDA and SCL lines are sequentially pulsed on by the TAP I2C logic module for brief periods to first precharge the capacitance of the SDA line and then prechargc the capacitance of the SCL line during low to high logic level transitions thereof. Precharging the capacitances of the I2C bus lines will also accelerate bus transfer operations for all I2C compatible devices since the capacitances of the I2C bus lines will be charged much faster through the low impedance active pull-up driver transistors then through the passive pull-up resistors.
摘要翻译：作为时钟主器件的I2C总线兼容器件包括具有高侧驱动器晶体管的瞬态有源上拉I2C（“TAP-I2C”）逻辑模块，例如P沟道场效应晶体管（FET） I2C总线上的正电源电压和相应的串行数据（“SDA”）和串行时钟（“SCL”）线路。用于SDA和SCL线的高边输出驱动晶体管由TAP I2C逻辑模块顺序地脉冲施加短暂时间，以首先对SDA线的电容进行预充电，然后在低电平至高逻辑电平转换期间预充电SCL线的电容它们。预充电I2C总线的电容也将加速所有I2C兼容设备的总线传输操作，因为I2C总线线路的电容将通过低阻抗有源上拉驱动器晶体管充电得更快，然后通过无源上拉电阻。

95. 发明申请

WO2009094352A3 EXTERNALLY SYNCHRONIZING MULTIPHASE PULSE WIDTH MODULATION SIGNALS 审中-公开
标题翻译：外部同步脉冲宽度调制信号的异步同步
公开(公告)号：WO2009094352A3
公开(公告)日：2009-10-08
申请号：PCT/US2009031500
申请日：2009-01-21
申请人： MICROCHIP TECH INC , KRIS BRYAN
发明人： KRIS BRYAN
IPC分类号： H02M7/5387 , H03K7/08
CPC分类号： H03K7/08
摘要： Waveform errors between multiphase PWM signals caused by external synchronization signals is solved by providing a capture register in a master time base circuit. The capture register is triggered by the external sync signal so as to 'capture' the value of the master time base counter at the occurrence of the rising edge of the external sync signal. This captured counter value is then provided to the local time bases of each of the phase PMW signal generators as the effective PWM period instead of locally stored PWM period values of each PWM signal generator. The captured time base value provided to the individual PWM generator time bases insures that the individual PWM generators remain properly synchronized to the master time base throughout the PWM cycles of all of the phases.
摘要翻译：通过在主时基电路中提供捕获寄存器来解决由外部同步信号引起的多相PWM信号之间的波形误差。捕获寄存器由外部同步信号触发，以便在外部同步信号的上升沿出现时捕获主时基计数器的值。然后将该捕获的计数器值提供给每个相位PMW信号发生器的本地时基作为有效PWM周期，而不是每个PWM信号发生器的本地存储的PWM周期值。提供给各个PWM发生器时基的捕获时基值确保各个PWM发生器在所有相的整个PWM周期内保持与主时基的正确同步。

96. 发明申请

WO2008088986A2 INTEGRATED TIME AND/OR CAPACITANCE MEASUREMENT SYSTEM, METHOD AND APPARATUS 审中-公开
标题翻译：集成时间和/或电容测量系统，方法和设备
公开(公告)号：WO2008088986A2
公开(公告)日：2008-07-24
申请号：PCT/US2008050563
申请日：2008-01-09
申请人： MICROCHIP TECH INC , BARTLING JAMES E
发明人： BARTLING JAMES E
IPC分类号： G01R27/26 , G01R29/02 , G01R31/28 , G04F10/00
CPC分类号： G01R27/2605 , G01R29/023 , G01R31/2884 , G01R31/3167 , G01R31/31725 , G01R31/31727 , G04F10/04 , G04F10/105
摘要： A time period of an event is determined by charging a known value capacitor from a constant current source during the event. The resultant voltage on the capacitor is proportional to the event time period and may be calculated from the resultant voltage and known capacitance value. Capacitance is measured by charging a capacitor from a constant current source during a known time period. The resultant voltage on the capacitor is proportional to the capacitance thereof and may be calculated from the resultant voltage and known time period. A long time period event may be measured by charging a first capacitor at the start of the event and a second capacitor at the end of the event, while counting clock times therebetween. Delay of an event is done by charging voltages on first and second capacitors at beginning and end of event, while comparing voltages thereon with a reference voltage.
摘要翻译：事件的时间段是通过在事件期间从恒流源充电已知值的电容器来确定的。电容器上的合成电压与事件时间周期成比例，并且可以从合成电压和已知电容值计算。通过在已知时间段内从恒流源向电容器充电来测量电容。电容器上所得到的电压与其电容成正比，并且可以由所得电压和已知时间段来计算。可以通过在事件开始时对第一电容器充电并且在事件结束时对第二电容器充电来测量长时间段事件，同时对其间的时钟时间进行计数。通过在事件开始和结束时在第一和第二电容器上充电电压，同时将其上的电压与参考电压进行比较来完成事件的延迟。

97. 发明申请

WO2008024670A3 DIRECT MEMORY ACCESS CONTROLLER 审中-公开
标题翻译：直接存储器访问控制器
公开(公告)号：WO2008024670A3
公开(公告)日：2008-05-29
申请号：PCT/US2007076103
申请日：2007-08-16
申请人： MICROCHIP TECH INC , RAJBHARTI NILESH
发明人： RAJBHARTI NILESH
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A direct memory access controller may comprise a data register for transferring data from a source to a destination address, a pattern register, a data comparator coupled with the data register and the pattern register, and a control unit coupled with the comparator operable to stop a data transfer if the comparator detects a match of the data register and the pattern register.
摘要翻译：直接存储器访问控制器可以包括用于将数据从源传送到目的地地址的数据寄存器，模式寄存器，与数据寄存器和模式寄存器耦合的数据比较器，以及与比较器耦合的控制单元，其可操作地停止数据传输如果比较器检测到数据寄存器和模式寄存器的匹配。

98. 发明申请

WO2008014370A3 MICROCONTROLLER WITH LOW NOISE PERIPHERAL 审中-公开
标题翻译：低噪声外设的微控制器
公开(公告)号：WO2008014370A3
公开(公告)日：2008-04-17
申请号：PCT/US2007074405
申请日：2007-07-26
申请人： MICROCHIP TECH INC , WOJEWODA IGOR , LOURENS RUAN
发明人： WOJEWODA IGOR , LOURENS RUAN
IPC分类号： G06F13/40 , H01L23/48
CPC分类号： G06F13/4072 , H01L2224/05554
摘要： A microcontroller may have at least a first and second output port coupled with external first and second pins, respectively, a programmable switching arrangement operable in a first mode to provide for a first and second output signal at the first and second pins, respectively, and in a second mode to provide for a first output signal at the first pin and an inverted first output signal at the second pin.
摘要翻译：微控制器可以具有至少第一和第二输出端口，分别与外部第一和第二引脚耦合，可编程开关装置可在第一模式下操作以分别在第一和第二引脚处提供第一和第二输出信号，以及在第二模式中提供第一引脚处的第一输出信号和第二引脚处的反相第一输出信号。

99. 发明申请

WO2007143424A3 A METHOD FOR PROGRAMMING AND ERASING AN ARRAY OF NMOS EEPROM CELLS THAT MINIMIZE BIT DISTURBANCES AND VOLTAGE WITHSTAND REQUIREMENTS FOR THE MEMORY ARRAY AND SUPPORTING CIRCUITS 审中-公开
标题翻译：一种用于对存储器阵列和支持电路最小化位冲突和电压耐受要求的NMOS EEPROM电池阵列进行编程和擦除的方法
公开(公告)号：WO2007143424A3
公开(公告)日：2008-04-10
申请号：PCT/US2007069726
申请日：2007-05-25
申请人： MICROCHIP TECH INC , HEWITT KENT , GERBER DONALD , SHIELDS JEFFREY A
发明人： HEWITT KENT , GERBER DONALD , SHIELDS JEFFREY A
IPC分类号： G11C16/00
CPC分类号： G11C16/0416 , G11C16/12 , G11C16/16 , G11C16/3427 , H01L27/0207 , H01L27/115 , H01L27/11803
摘要： A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.
摘要翻译：一种用于编程和擦除NMOS电可擦除可编程只读存储器（EEPROM）单元的阵列的方法，其最小化存储器阵列单元和支持电路的位干扰和高电压要求。此外，N沟道存储单元的阵列可以通过产生多个电隔离的P阱来分离成独立可编程的存储器段，在其上制造存储器段。多个电隔离的P阱可以例如通过p-n结隔离或电介质隔离来产生。

100. 发明申请

WO2008005984A3 LIQUID CRYSTAL DISPLAY BIAS GENERATOR 审中-公开
标题翻译：液晶显示偏差发生器
公开(公告)号：WO2008005984A3
公开(公告)日：2008-03-13
申请号：PCT/US2007072750
申请日：2007-07-03
申请人： MICROCHIP TECH INC , BARTLING JAMES E , ASIF IQBAL , RAMAN MURUGESAN
发明人： BARTLING JAMES E , ASIF IQBAL , RAMAN MURUGESAN
IPC分类号： G09G3/36 , H02M3/07
CPC分类号： G09G3/3696 , G09G2330/02 , H02M3/07 , H02M2001/009
摘要： A liquid crystal display (LCD) bias generator generates a plurality of bias voltages, e.g., four bias voltages, needed to drive a segmented LCD. The LCD bias generator has a voltage generator, e.g., charge pump, that may generate a most positive voltage, e.g., substantially equal to or more positive than VDD, on the integrated circuit that may also be used for maintaining proper reverse bias operation of well ties and analog switches of the integrated circuit. Other necessary LCD bias voltages, e.g., three voltages, may also be derived from the LCD bias generator to provide bias and contrast control voltages required by the LCD. Having a more positive bias voltage than the power supply voltage, VDD, allows VDD to cover a wider range of voltages, e.g., powered from a battery, by eliminating the need for complex analog switch and pad designs for the integrated circuit.
摘要翻译：液晶显示器（LCD）偏压发生器产生驱动分段LCD所需的多个偏置电压，例如四个偏置电压。 LCD偏置发生器具有电压发生器，例如电荷泵，其可以在集成电路上产生最大正电压，例如基本上等于或大于VDD的正电压，其也可用于保持阱的适当的反向偏压操作系列和模拟开关的集成电路。也可以从LCD偏置发生器导出其它必需的LCD偏置电压，例如三个电压，以提供LCD所需的偏置和对比度控制电压。具有比电源电压VDD更正的偏置电压，VDD可以通过消除对集成电路的复杂模拟开关和焊盘设计的需要来覆盖更宽范围的电压，例如由电池供电。

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