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1. 发明申请

WO2010062727A3 LOW DROP OUT (LDO) BYPASS VOLTAGE REGULATOR 审中-公开
标题翻译：低压降（LDO）旁路电压稳压器
公开(公告)号：WO2010062727A3
公开(公告)日：2010-07-22
申请号：PCT/US2009063026
申请日：2009-11-03
申请人： MICROCHIP TECH INC , LOURENS RUAN , ENACHESCU RAZVAN , TIU MARC
发明人： LOURENS RUAN , ENACHESCU RAZVAN , TIU MARC
IPC分类号： G05F1/575
CPC分类号： G05F1/575
摘要： A power element bypass and voltage regulation circuit shutdown is used in a low drop out (LDO) bypass voltage regulator to minimize current drawn by the voltage regulator circuit when the supply input voltage approaches the regulated output voltage of the voltage regulation circuit. Two modes of operation are used in the low drop out (LDO) bypass voltage regulator. A regulate mode is used when the supply input voltage is greater than the reference voltage input, and a track mode is used when the supply input voltage is less than or equal to approximately the regulated output voltage of the voltage regulation circuit. Hysteresis may be introduced when switching between the regulate and track modes of operation.
摘要翻译：在低压降（LDO）旁路电压调节器中使用电源元件旁路和电压调节电路关断，以最小化当电源输入电压接近电压调节电路的稳压输出电压时由电压调节器电路汲取的电流。低压降（LDO）旁路电压调节器采用两种工作模式。当电源输入电压大于参考电压输入时，使用调节模式，当电源输入电压小于或等于电压调节电路的稳压输出电压时，使用轨迹模式。在调节和跟踪操作模式之间切换时可能会引入迟滞。

2. 发明申请

WO2005104006A3 REDUCING FALSE WAKE-UP IN A LOW FREQUENCY TRANSPONDER 审中-公开
标题翻译：减少在低频传输器中的假冒唤醒
公开(公告)号：WO2005104006A3
公开(公告)日：2006-03-30
申请号：PCT/US2005012934
申请日：2005-04-14
申请人： MICROCHIP TECH INC , NOLAN JAMES B , LEE THOMAS YOUBOK , LAMPHIER ALAN , LOURENS RUAN , VERNIER STEVE
发明人： NOLAN JAMES B , LEE THOMAS YOUBOK , LAMPHIER ALAN , LOURENS RUAN , VERNIER STEVE
IPC分类号： G06K7/00 , G06K19/07 , G07C9/00 , H04Q5/22
CPC分类号： G06K19/0705 , G06K19/0723 , G07C9/00309 , G07C2009/0038
摘要： A bidirectional remote keyless entry (RKE) transponder comprises an analog front-end (AFE) having a programmable wake-up filter that predefines the waveform timing of the desired input signal, minimum modulation depth requirement of input signal, and independently controllable channel gain reduction of each of its three channels, X, Y, and Z. The wake-up filter parameters are the length of high and low durations of wake-up pulses that may be programmed in a configuration register. The wake-up filter allows the AFE to output demodulated data if the input signal meets its wake-up filter requirement, but does not output the demodulated data otherwise. The AFE output pin is typically connected to an eternal device for control, such as a microcontroller (MCU). The external device typically stays in low current sleep (or standby) mode when the AFE has no output and switches to high current wake-up (or active) mode when the AFE has output. Therefore, in order to keep the eternal control device in the low current sleep mode when there is no desired input signal, it is necessary to keep no output at the AFE output pin. This can be achieved by controlling the wake-up filter parameters, minimum modulation depth requirement of input signal, and. channel gains of the AFE device. These features can reduce false-wake up of the bidirectional RKE transponder due to undesired input signals such as noise signals.
摘要翻译：双向远程无钥匙进入（RKE）转发器包括具有可编程唤醒滤波器的模拟前端（AFE），其预定义所需输入信号的波形定时，输入信号的最小调制深度要求以及独立可控的信道增益减小的三个通道中的每一个，X，Y和Z.唤醒滤波器参数是可以在配置寄存器中编程的唤醒脉冲的高和低持续时间的长度。唤醒滤波器允许AFE在输入信号满足唤醒滤波器要求时输出解调数据，否则不输出解调数据。 AFE输出引脚通常连接到用于控制的永久性设备，例如微控制器（MCU）。当AFE没有输出时，外部设备通常保持在低电流休眠（或待机）模式，并且当AFE输出时，外部设备切换到高电流唤醒（或有效）模式。因此，为了在不需要输入信号的情况下将永久控制装置保持在低电流睡眠模式，需要在AFE输出引脚处不输出。这可以通过控制唤醒滤波器参数，输入信号的最小调制深度要求来实现。 AFE设备的通道增益。这些功能可以减少由于不期望的输入信号（如噪声信号）引起的双向RKE转发器的假唤醒。

3. 发明申请

WO2005109328A1 DYNAMIC CONFIGURATION OF A RADIO FREQUENCY TRANSPONDER 审中-公开
标题翻译：无线电频率传感器的动态配置
公开(公告)号：WO2005109328A1
公开(公告)日：2005-11-17
申请号：PCT/US2005/012789
申请日：2005-04-15
申请人： MICROCHIP TECHNOLOGY INCORPORATED , LEE, Thomas, Youbok , NOLAN, James, B. , VERNIER, Steve , LOURENS, Ruan , DELPORT, Vivien , LAMPHIER, Alan , SULLIVAN, Glen, Allen
发明人： LEE, Thomas, Youbok , NOLAN, James, B. , VERNIER, Steve , LOURENS, Ruan , DELPORT, Vivien , LAMPHIER, Alan , SULLIVAN, Glen, Allen
IPC分类号： G06K19/07
CPC分类号： G06K19/0723 , G06K19/0726 , G06K19/07767
摘要： A multi-channel remote keyless entry (RKE) transponder having dynamically reconfigurable input channel selection, channel disable, settable sensitivity for each channel, wake-up filter timing parameters, automatic gain control hold, internal tuning capacitor selection for each channel's antenna, minimum modulation depth requirement for input signal and bi-directional talk-back. Programmable minimum modulation depth requirement reduces false wake-up of the RKE transponder. An antenna for each channel of the RKE transponder may be tuned with internal tuning capacitors for improved range and receiver sensitivity. The internal tuning capacitor parameters may be stored in a configuration register. Gain of the channel may be fixed while the antenna is tuned. The antennas may be de-queued for talk-back to a base station for low frequency bidirectional communications. An external control device may dynamically read from and write to the configuration registers via a serial communications interface.
摘要翻译：具有动态可重配置输入通道选择，通道禁用，每个通道的可设置灵敏度，唤醒滤波器定时参数，自动增益控制保持，每个通道天线的内部调谐电容选择的多通道遥控无钥匙进入（RKE）转发器，最小调制输入信号和双向对讲的深度要求。可编程的最小调制深度要求可减少RKE转发器的假唤醒。可以使用内部调谐电容器调整RKE应答器的每个通道的天线，以提高范围和接收机灵敏度。内部调谐电容参数可以存储在配置寄存器中。天线调谐时，通道的增益可能会固定。天线可以被排队，用于与基站通话用于低频双向通信。外部控制设备可以通过串行通信接口动态地读取和写入配置寄存器。

4. 发明申请

WO2005060115A1 A TIME SIGNAL RECEIVER AND DECODER 审中-公开
标题翻译：时间信号接收器和解码器
公开(公告)号：WO2005060115A1
公开(公告)日：2005-06-30
申请号：PCT/US2004/041604
申请日：2004-12-13
申请人： MICROCHIP TECHNOLOGY INCORPORATED , LOURENS, Ruan , EAGAR, Layton, W. , COOPER, Russell, Eugene
发明人： LOURENS, Ruan , EAGAR, Layton, W. , COOPER, Russell, Eugene
IPC分类号： H04B1/24
CPC分类号： H04B1/24 , G04R20/10 , H03H11/1252 , H03H11/1291
摘要： A time signal receiver and decoder receives, detects and stores time information from time signals, e.g ., WWV, WWVH, WWVB (USA), JJY (Japan), MSF (UK) and the like. The time information may be used for a self setting clock, and the clock may be used as a reference in time sensitive applications, devices and systems. The time signal receiver may use a high-Q state variable bandpass filter or an anti-notch filter circuit for selectivity at the time signal frequency of interest. The decoder is coupled to the time signal receiver, decodes the time information in the received time signal and may store the decoded time information.
摘要翻译：时间信号接收器和解码器接收，检测和存储来自时间信号的时间信息，例如WWV，WWVH，WWVB（USA），JJY（Japan），MSF（UK）等。时间信息可以用于自设置时钟，并且时钟可以用作时间敏感应用，设备和系统中的参考。时间信号接收机可以在感兴趣的时间信号频率下使用高Q状态可变带通滤波器或抗陷波滤波器电路用于选择性。解码器耦合到时间信号接收器，对接收的时间信号中的时间信息进行解码，并且可以存储解码的时间信息。

5. 发明申请

WO2005031994A1 Q-QUENCHING SUPER-REGENERATIVE RECEIVER 审中-公开
标题翻译： Q-QUENCHING超再生接收器
公开(公告)号：WO2005031994A1
公开(公告)日：2005-04-07
申请号：PCT/US2004/030627
申请日：2004-09-20
申请人： MICROCHIP TECHNOLOGY INCORPORATED , LOURENS, Ruan
发明人： LOURENS, Ruan
IPC分类号： H04B1/30
CPC分类号： H03D11/06 , H03D11/02 , H04B1/30
摘要： A super-regenerative receiver uses controlled Q-quenching and may limit the resonant tank circuit amplitude by loading the tank circuit as soon as regenerative oscillation is detected. An amplitude detector is coupled to the regenerative amplifier and controls a Q loading circuit coupled to the tank circuit of the regenerative amplifier. The amplitude detector turns on the Q loading circuit which then stops the regenerative amplifier from oscillating, and the Q-loading remains on for a brief time to insure that the regenerative amplifier has stopped oscillating. After the brief time, the Q loading circuit is turned off and the regenerative amplifier goes into oscillation again. This cycle repeats controllably over and over, resulting in a lower self-induced noise floor and improved received signal sensitivity. The super-regenerative receiver may be used in the very low frequency (VLF), low frequency (LF), medium frequency (MF), high frequency (HF), very high frequency (VHF) and super high frequency (SHF) ranges to receive continuous wave (CW), amplitude modulated (AM) and frequency modulated (FM) radio signals.
摘要翻译：超再生接收机采用受控制的Q-淬火，并且一旦检测到再生振荡，就通过加载油箱回路来限制共振回路振幅。振幅检测器耦合到再生放大器并且控制耦合到再生放大器的电路的Q加载电路。振幅检测器打开Q加载电路，然后停止再生放大器的振荡，并且Q加载保持打开一段短暂的时间，以确保再生放大器已停止振荡。短暂时间后，Q加载电路关闭，再生放大器再次进入振荡状态。该循环可重复地反复重复，导致较低的自感噪声基底和改善的接收信号灵敏度。超再生接收机可以用于极低频（VLF），低频（LF），中频（MF），高频（HF），超高频（VHF）和超高频（SHF）接收连续波（CW），幅度调制（AM）和调频（FM）无线电信号。

6. 发明申请

WO2010062727A2 LOW DROP OUT (LDO) BYPASS VOLTAGE REGULATOR 审中-公开
标题翻译：低压差（LDO）旁路稳压器
公开(公告)号：WO2010062727A2
公开(公告)日：2010-06-03
申请号：PCT/US2009/063026
申请日：2009-11-03
申请人： MICROCHIP TECHNOLOGY INCORPORATED , LOURENS, Ruan , ENACHESCU, Razvan , TIU, Marc
发明人： LOURENS, Ruan , ENACHESCU, Razvan , TIU, Marc
IPC分类号： G05F1/10
CPC分类号： G05F1/575
摘要： A power element bypass and voltage regulation circuit shutdown is used in a low drop out (LDO) bypass voltage regulator to minimize current drawn by the voltage regulator circuit when the supply input voltage approaches the regulated output voltage of the voltage regulation circuit. Two modes of operation are used in the low drop out (LDO) bypass voltage regulator. A regulate mode is used when the supply input voltage is greater than the reference voltage input, and a track mode is used when the supply input voltage is less than or equal to approximately the regulated output voltage of the voltage regulation circuit. Hysteresis may be introduced when switching between the regulate and track modes of operation.
摘要翻译：在低压降（LDO）旁路电压调节器中使用功率元件旁路和电压调节电路关断，以在电源输入电压接近调节后的输出电压时最小化由电压调节器电路汲取的电流电压调节电路。低压差（LDO）旁路电压调节器使用两种工作模式。当电源输入电压大于参考电压输入时使用调节模式，并且当电源输入电压小于或等于电压调节电路的调节输出电压时使用跟踪模式。在调节和跟踪操作模式之间切换时，可能会引入滞后现象。

7. 发明申请

WO2008137707A1 REGULATOR BYPASS START-UP IN AN INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：集成电路设备中的调节器旁路启动
公开(公告)号：WO2008137707A1
公开(公告)日：2008-11-13
申请号：PCT/US2008/062455
申请日：2008-05-02
申请人： MICROCHIP TECHNOLOGY INCORPORATED , STEEDMAN, Sean , DELPORT, Vivien , ZDENEK, Jerrold, S. , LOURENS, Ruan , CHARLES, Michael , JULICHER, Joseph , SCHROEDER, Eric
发明人： STEEDMAN, Sean , DELPORT, Vivien , ZDENEK, Jerrold, S. , LOURENS, Ruan , CHARLES, Michael , JULICHER, Joseph , SCHROEDER, Eric
IPC分类号： G11C5/14 , G05F1/46
CPC分类号： G11C5/147
摘要： An internal' voltage regulator (108) in an integrated circuit device (102) is always active upon initial start-up and/or power-on-reset operations. The internal voltage regulator (108) protects the low voltage core logic circuits (104, 106) of the integrated circuit device (102) from excessively high voltages that may be present in a particular application. In addition, nonvolatile memory (104) may be part of and operational with the low voltage core logic circuits (104, 106) for storing device operating parameters. Therefore, the internal voltage regulator (108) also protects the low voltage nonvolatile memory (104) from excessive high voltages. Once the integrated circuit device (102) has stabilized and all logic circuits therein fully function, a bit(s) in the nonvolatile memory (104) may be read to determine if the internal voltage regulator (108) should remain active, e.g., power operation with a high voltage source, or be placed into a bypass mode for low power operation when the integrated circuit device (102) is powered by a low voltage.
摘要翻译：在初始启动和/或上电复位操作时，集成电路器件（102）中的内部“稳压器（108）”总是有效。内部电压调节器（108）保护集成电路器件（102）的低电压核心逻辑电路（104,106）免受可能存在于特定应用中的过高的电压。此外，非易失性存储器（104）可以是用于存储设备操作参数的低电压核心逻辑电路（104,106）的一部分并且可操作。因此，内部稳压器（108）也保护低压非易失性存储器（104）免受过高的高电压的影响。一旦集成电路器件（102）已经稳定并且其中的所有逻辑电路完全起作用，则可以读取非易失性存储器（104）中的位以确定内部稳压器（108）是否应该保持有效，例如功率当集成电路器件（102）由低电压供电时，用高电压源操作或被置于旁路模式以进行低功率操作。

8. 发明申请

WO2005067155A1 A TIME SIGNAL PERIPHERAL 审中-公开
标题翻译：时间信号外围
公开(公告)号：WO2005067155A1
公开(公告)日：2005-07-21
申请号：PCT/US2004/042004
申请日：2004-12-15
申请人： MICROCHIP TECHNOLOGY INCORPORATED , LOURENS, Ruan , CHAFFEE, Douglas, LeRoy
发明人： LOURENS, Ruan , CHAFFEE, Douglas, LeRoy
IPC分类号： H04B1/24
CPC分类号： H04B1/24
摘要： A time signal peripheral may include a radio receiver, decoder/demodulator and time registers. The time signal peripheral may receive, detect and store time information from time signals, e.g ., WWV, WWVH, WWVB (USA), JJY (Japan), MSF (UK) and the like. The time information may be used for a self setting clock, and the clock may be used as a reference in time sensitive applications, devices and systems. A digital processor may be coupled to and control the time signal peripheral. The digital processor may be used to decode the time information in the received time signal, store the decoded time information and make the time information available for use by a device and/or system, or the time signal peripheral may do these functions, allowing the digital processor to be used for higher level applications. The time signal peripheral may be fabricated on an integrated circuit die with or without the digital processor. The time signal peripheral and the digital process may be on a separate integrated circuit dice and be packaged together in a signal integrated circuit package.
摘要翻译：时间信号外围设备可以包括无线电接收机，解码器/解调器和时间寄存器。时间信号外围设备可以接收，检测和存储来自时间信号的时间信息，例如WWV，WWVH，WWVB（USA），JJY（Japan），MSF（UK）等。时间信息可以用于自设置时钟，并且时钟可以用作时间敏感应用，设备和系统中的参考。数字处理器可以耦合到并控制时间信号外围设备。数字处理器可以用于解码所接收的时间信号中的时间信息，存储解码的时间信息并使得时间信息可供设备和/或系统使用，或者时间信号外设可以执行这些功能，从而允许数字处理器用于更高级别的应用。时间信号外围设备可以在具有或不具有数字处理器的集成电路管芯上制造。时间信号外围设备和数字处理器可以在单独的集成电路芯片上并且封装在信号集成电路封装中。

9. 发明申请

WO2004111662A2 ULTRA-LOW POWER PROGRAMMABLE TIMER AND LOW VOLTAGE DETECTION CIRCUITS 审中-公开
标题翻译：超低功耗可编程定时器和低电压检测电路
公开(公告)号：WO2004111662A2
公开(公告)日：2004-12-23
申请号：PCT/US2004/017570
申请日：2004-06-03
申请人： MICROCHIP TECHNOLOGY INCORPORATED , LOURENS, Ruan , MORENO, Miguel
发明人： LOURENS, Ruan , MORENO, Miguel
IPC分类号： G01R19/00
CPC分类号： G01K3/005 , G01K2215/00 , G01R19/16542 , G01R31/3648 , H03K5/06 , H03K5/08
摘要： An Ultra-low power voltage detection circuit is implemented in a digital integrated circuit to device to provide a basic timer, programmable timer and programmable low voltage detection (PLVD) using a single connection of the digital integrated circuit device and a passive component(s) external to the digital integrated circuit device. An internal low current source may be enabled so as to discharge an external timing capacitor connected to the output connection, thus eliminating the need for an external resistor. However, timing accuracy may be improved by adding an external discharging resistor and/or charging resistor. The output connection may be configured as a tri-state output and may be driven high to charge and low to discharge the timing capacitor. A voltage reference may be used in determining a voltage trip point for timing and low voltage detection purposes. Temperature may be determined from either a trip voltage compared to a known voltage determined at a known temperature, or a current value of the current source compared to a known current value determined at a known temperature, times a constant.
摘要翻译：在数字集成电路中实现超低功率电压检测电路以提供基本定时器，可编程定时器和使用数字集成电路器件的单一连接的可编程低电压检测（PLVD）和无源部件，在数字集成电路设备外部。可以使能内部低电流源，以便连接到输出连接的外部定时电容器放电，从而不需要外部电阻器。然而，通过添加外部放电电阻器和/或充电电阻器可以提高定时精度。输出连接可以被配置为三态输出，并且可以被驱动为高电荷并且将其降低以对定时电容器进行放电。电压参考可用于确定用于定时和低电压检测目的的电压跳变点。温度可以由与在已知温度下确定的已知电压相比较的跳闸电压或电流源的电流值与在已知温度下确定的已知电流值乘以常数来确定。

10. 发明申请

WO2008137718A1 VARIABLE POWER AND RESPONSE TIME BROWN-OUT-RESET CIRCUIT 审中-公开
标题翻译：可变功率和响应时间欠压复位电路
公开(公告)号：WO2008137718A1
公开(公告)日：2008-11-13
申请号：PCT/US2008/062470
申请日：2008-05-02
申请人： MICROCHIP TECHNOLOGY INCORPORATED , STEEDMAN, Sean , LOURENS, Ruan , HULL, Richard
发明人： STEEDMAN, Sean , LOURENS, Ruan , HULL, Richard
IPC分类号： H03K17/22 , G06F1/28 , G06F1/32 , G01R19/165 , H03K17/00
CPC分类号： H03K17/22 , G01R19/16552 , G06F1/24 , G06F1/30 , H03K2217/0036
摘要： A brown-out-reset circuit having programmable power and response time characteristics. These characteristics may be programmed over an n-bit wide bus for 2n different characteristics ranging from very low power consumption and slower response time to very fast response time and higher power consumption. A serial one wire bus may be used instead of the n-bit wide bus.
摘要翻译：具有可编程功率和响应时间特性的欠压复位电路。这些特性可以通过n位宽的总线编程，用于2n种不同的特性，从非常低的功耗和较慢的响应时间到非常快的响应时间和更高的功耗。可以使用串行一线总线来代替n位宽的总线。

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