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1. 发明申请

WO2009052494A3 WIRELESS TRANSMIT/RECEIVE UNIT 审中-公开
标题翻译：无线发射/接收单元
公开(公告)号：WO2009052494A3
公开(公告)日：2009-06-04
申请号：PCT/US2008080500
申请日：2008-10-20
申请人： INTERDIGITAL TECH CORP , CASTOR DOUGLAS R , HEPLER EDWARD L , STARSINIC MICHAEL F , HACKETT WILLIAM C , BASS DAVID S , GREDONE JOSEPH W , RUSSELL PAUL L JR , GORMAN RICHARD P
发明人： CASTOR DOUGLAS R , HEPLER EDWARD L , STARSINIC MICHAEL F , HACKETT WILLIAM C , BASS DAVID S , GREDONE JOSEPH W , RUSSELL PAUL L JR , GORMAN RICHARD P
IPC分类号： H04W52/02 , G06F1/32 , H04M1/73
CPC分类号： G06F1/325 , G06F1/3215 , G06F1/3278 , G06F1/3287 , H04W52/00 , H04W52/02 , Y02D10/157 , Y02D10/171 , Y02D70/12 , Y02D70/124 , Y02D70/20
摘要： A method and apparatus for optimization of a modem for high data rate applications comprise a plurality of hardware accelerators which are configured to perform data processing functions, wherein the hardware accelerators are parameterized, a processor is configured to selectively activate accelerators according to the desired function to conserve power requirements and a shared memory configured for communication between the plurality of hardware accelerators.
摘要翻译：用于优化用于高数据速率应用的调制解调器的方法和装置包括被配置为执行数据处理功能的多个硬件加速器，其中硬件加速器被参数化，处理器被配置为根据期望的功能选择性地激活加速器，节省功率需求和配置用于在多个硬件加速器之间进行通信的共享存储器。

2. 发明申请

WO2006020283A3 HIGH SPEED DOWNLINK PACKET ACCESS CO-PROCESSOR FOR UPGRADING THE CAPABILITIES OF AN EXISTING MODEM HOST 审中-公开
标题翻译：用于升级现有调制解调器主机能力的高速下行链路分组接入协同处理器
公开(公告)号：WO2006020283A3
公开(公告)日：2007-05-10
申请号：PCT/US2005025540
申请日：2005-07-19
申请人： INTERDIGITAL TECH CORP , HACKETT WILLIAM C , DIFAZIO ROBERT A , HEPLER EDWARD L , REZNIK ALEXANDER , CASTOR DOUGLAS R , ZEIRA ARIELA , GAZDA ROBERT G , KAEWELL JOHN DAVID JR
发明人： HACKETT WILLIAM C , DIFAZIO ROBERT A , HEPLER EDWARD L , REZNIK ALEXANDER , CASTOR DOUGLAS R , ZEIRA ARIELA , GAZDA ROBERT G , KAEWELL JOHN DAVID JR
IPC分类号： H04B7/216 , H03H7/30 , H04B1/00 , H04B1/38 , H04B1/707 , H04L12/66 , H04W88/02
CPC分类号： H04B1/707 , H04B1/406 , H04B2201/70707 , H04B2201/709727 , H04L2025/03509 , H04W88/02
摘要： A wireless transmit/receive unit (WTRU 250, Figure 1) for processing code division multiple access (CDMA) signals. The WTRU includes modem host (300) and a high speed downlink packet access (HSDPA) co-processor (400) , which communicate over a plurality of customizable interfaces. The modem host operates in accordance with third generation partnership project (3GPP) Release 4 (R4) standards, and the HSDPA co-processor enhances the wireless communication capabilities of the WTRU as a whole such that the WTRU operates in accordance with 3GPP Release 5 (S3) standards.
摘要翻译：用于处理码分多址（CDMA）信号的无线发射/接收单元（WTRU 250，图1）。 WTRU包括调制解调器主机（300）和通过多个可定制接口进行通信的高速下行链路分组接入（HSDPA）协处理器（400）。调制解调器主机根据第三代合作伙伴计划（3GPP）版本4（R4）标准进行操作，并且HSDPA协处理器整体上增强了WTRU的无线通信能力，使得WTRU根据3GPP版本5（ S3）标准。

3. 发明申请

WO2004080087A3 RECEIVED SIGNAL PROCESSING FOR WIRELESS COMMUNICATIONS 审中-公开
标题翻译：接收信号处理无线通信
公开(公告)号：WO2004080087A3
公开(公告)日：2004-12-23
申请号：PCT/US2004007049
申请日：2004-03-05
申请人： INTERDIGITAL TECH CORP , HEPLER EDWARD L , FERRANTE STEVEN , HACKETT WILLIAM C , REZNIK ALEXANDER , BOHNHOFF PETER , MEYER JAN
发明人： HEPLER EDWARD L , FERRANTE STEVEN , HACKETT WILLIAM C , REZNIK ALEXANDER , BOHNHOFF PETER , MEYER JAN
IPC分类号： G09G3/28 , H04B1/707 , H04B7/08 , H04B17/00 , H04J3/06 , H04L25/02 , H04B7/216
CPC分类号： H04B1/7113 , H04B1/70735 , H04B1/70755 , H04B1/708 , H04B1/7083 , H04B1/7117 , H04B7/08 , H04B17/364 , H04J13/10 , H04L25/0212
摘要： A wireless transmit receive unit (WTRU) and methods are used in a wireless communication system to process sampled received signals to establish and/or maintain wireless communications (Fig 9 & 10). A selectively controllable coherent accumulation unit produces power delay profiles. A selectively controllable post processing unit passes threshold qualified magnitude approximation values and PDP positions to a device such as a rake receiver to determine receive signal paths.
摘要翻译：在无线通信系统中使用无线发射接收单元（WTRU）和方法来处理采样的接收信号以建立和/或维持无线通信（图9和10）。选择性可控相干累加单元产生功率延迟分布。有选择地可控的后处理单元将阈值限幅值近似值和PDP位置传送到诸如瑞克接收机的设备以确定接收信号路径。

4. 发明申请

WO2007005381A2 PROTOCOL ENGINE FOR PROCESSING DATA IN A WIRELESS TRANSMIT/RECEIVE UNIT 审中-公开
标题翻译：用于处理无线发送/接收单元中的数据的协议引擎
公开(公告)号：WO2007005381A2
公开(公告)日：2007-01-11
申请号：PCT/US2006024843
申请日：2006-06-27
申请人： INTERDIGITAL TECH CORP , HEPLER EDWARD L , GAZDA ROBERT G , REZNIK ALEXANDER
发明人： HEPLER EDWARD L , GAZDA ROBERT G , REZNIK ALEXANDER
IPC分类号： H04J11/00 , H04W88/02
CPC分类号： G06F13/1663 , H04L49/90 , H04L49/901 , H04L49/9057 , H04L49/9094 , H04L67/04 , H04L69/12 , H04L69/22 , H04L69/324 , H04W88/02
摘要： A protocol engine (PE) for processing data within a protocol stack in a wireless transmit/receive unit (WTRU) is disclosed. The protocol stack executes decision and control operations. The data processing and re-formatting which was performed in a conventional protocol stack is removed from the protocol stack and performed by the PE. The protocol stack issues a control word for processing data and the PE processes the data based on the control word. Preferably, the WTRU includes a shared memory and a second memory. The shared memory is used as a data block place holder to transfer the data amongst processing entities. For transmit processing, the PE retrieves source data from the second memory and processed the data while moving the data to the shared memory based on the control word. For receive processing, the PE retrieves received data from the shared memory and processes it while moving the data to the second memory.
摘要翻译：公开了用于处理无线发射/接收单元（WTRU）中的协议栈内的数据的协议引擎（PE）。协议栈执行决策和控制操作。在传统协议栈中执行的数据处理和重新格式化从协议栈中移除并由PE执行。协议栈为处理数据发出控制字，PE根据控制字处理数据。优选地，WTRU包括共享存储器和第二存储器。共享内存用作数据块占位符来在处理实体之间传输数据。为了进行发送处理，PE基于控制字从第二存储器检索源数据并处理数据，同时将数据移动到共享存储器。对于接收处理，PE从共享存储器中检索接收到的数据，并在将数据移动到第二个存储器时对其进行处理。

5. 发明申请

WO2004077722A3 PROCESSING WIRELESS COMMUNICATION DATA IN PRESENCE OF FORMAT UNCERTAINTY 审中-公开
标题翻译：处理格式不确定性的无线通信数据
公开(公告)号：WO2004077722A3
公开(公告)日：2006-06-08
申请号：PCT/US2004004658
申请日：2004-02-18
申请人： INTERDIGITAL TECH CORP , REZNIK ALEXANDER , HEPLER EDWARD L
发明人： REZNIK ALEXANDER , HEPLER EDWARD L
IPC分类号： H04B1/707 , H04L1/00 , H04L1/18
CPC分类号： H04L1/1829 , H04B1/707 , H04L1/0006 , H04L1/0025 , H04L1/0032 , H04L1/0071
摘要： Components and method are provided to efficiently process wireless communications data where prior knowledge of the specific format of the communication data is unavailable. A wireless transmit receive unit (WTRU) is configured for use in a wireless communication system where communication data for selected channels is transmitted in system time frames. The WTRU has a receiver, a received chip rate processor (RCRP) to despread each wireless signal of spread data received in each time frame using a minimum spreading code or other appropriate key sequence, a memory storing despread data for each time frame, a format detector to determine the number of physical channels and respective spreading factor for each physical channel for the wireless signal of spread data received in each time frame, and a de-interleaver for de-interleaving stored data despread by the RCPR for each time frame into the number of physical channels determined by the format detector.
摘要翻译：提供组件和方法以有效地处理无线通信数据，其中通信数据的特定格式的先前知识不可用。无线发射接收单元（WTRU）被配置为在无线通信系统中使用，其中所选择的信道的通信数据以系统时间帧传输。 WTRU具有接收机，接收到的码片速率处理器（RCRP），以使用最小扩展码或其他适当的密钥序列来解扩每个时间帧中接收的扩展数据的每个无线信号，存储每个时间帧的解扩数据的存储器，格式检测器，以确定用于每个时间帧中接收的扩展数据的无线信号的每个物理信道的物理信道数量和相应的扩展因子，以及解交织器，用于将由每个时间帧被RCPR解扩的存储数据解交织成由格式检测器确定的物理通道数。

6. 发明申请

WO2008008512A3 SYMBOL RATE HARDWARE ACCELERATOR 审中-公开
标题翻译：符号速率硬件加速器
公开(公告)号：WO2008008512A3
公开(公告)日：2008-04-10
申请号：PCT/US2007016031
申请日：2007-07-12
申请人： INTERDIGITAL TECH CORP , HEPLER EDWARD L
发明人： HEPLER EDWARD L
IPC分类号： H04L1/00 , G06F11/00
CPC分类号： H04L1/0043 , H04L1/0065 , H04L1/0071
摘要： A hardware accelerator includes a first buffer, a second buffer, address generator(s), a translation read-only memory (ROM), a cyclic redundancy check (CRC) generator, a convolutional encoder and a controller. The first and second buffers store information bits. The address generator(s) generate(s) an address for accessing the first buffer, the second buffer and a shared memory architecture (SMA). The translation ROM is used in generating a translated address for accessing the first buffer and the second buffer. The controller sets parameters for the CRC generator, the convolutional encoder and the address generator, and performs a predefined sequence of control commands for channel processing, such as reordering, block coding, parity tailing, puncturing, convolutional encoding, and interleaving, on the information bits by manipulating the information bits while moving the information bits among the first buffer, the second buffer, the SMA, the CRC generator, and the convolutional encoder.
摘要翻译：硬件加速器包括第一缓冲器，第二缓冲器，地址生成器，转换只读存储器（ROM），循环冗余校验（CRC）发生器，卷积编码器和控制器。第一和第二缓冲器存储信息位。地址生成器生成用于访问第一缓冲器，第二缓冲器和共享存储器体系结构（SMA）的地址。翻译ROM用于生成用于访问第一缓冲器和第二缓冲器的翻译地址。控制器设置CRC发生器，卷积编码器和地址生成器的参数，并且对信息执行诸如重新排序，块编码，奇偶校验拖尾，删截，卷积编码和交织等信道处理的预定义的控制命令序列在第一缓冲器，第二缓冲器，SMA，CRC发生器和卷积编码器中移动信息位的同时操纵信息位。

7. 发明申请

WO2007002202A3 METHOD AND APPARATUS FOR EFFICIENT OPERATION OF AN ENHANCED DEDICATED CHANNEL 审中-公开
标题翻译：增强专用通道有效运行的方法和装置
公开(公告)号：WO2007002202A3
公开(公告)日：2007-11-29
申请号：PCT/US2006024154
申请日：2006-06-20
申请人： INTERDIGITAL TECH CORP , REZNIK ALEXANDER , HEPLER EDWARD L , ZHANG GUODONG , SMITH HARRY SETH , PAN JUNG-LIN , WANG PETER SHAOMIN , RACHA RENUKA , GAZDA ROBERT , TERRY STEPHEN E
发明人： REZNIK ALEXANDER , HEPLER EDWARD L , ZHANG GUODONG , SMITH HARRY SETH , PAN JUNG-LIN , WANG PETER SHAOMIN , RACHA RENUKA , GAZDA ROBERT , TERRY STEPHEN E
IPC分类号： H04J3/14
CPC分类号： H04W72/0406 , H04L1/1812 , H04L1/1854 , H04L1/1887 , H04L1/1896
摘要： A method and apparatus for efficient operation of an enhanced dedicated channel (E-DCH) are disclosed. A physical layer processing includes computation of various control parameters followed by actual processing of the data to be transmitted. In accordance with the present invention, the computation of the control parameters is performed asynchronously from the associated data operation. A medium access control (MAC) layer provides information needed for computation of the control parameters to the physical layer as early as possible, while the data is being processed in parallel. The provided data includes a hybrid automatic repeat request (H-ARQ) profile, a transport block size, power offset, or the like. By sending this data to the physical layer before MAC-e processing is complete, the latency constraint can be significantly relaxed.
摘要翻译：公开了一种用于增强专用信道（E-DCH）的有效操作的方法和装置。物理层处理包括各种控制参数的计算，随后实际处理要发送的数据。根据本发明，控制参数的计算是从关联的数据操作中异步执行的。介质访问控制（MAC）层在数据被并行处理的同时尽可能早地向物理层提供控制参数的计算所需的信息。提供的数据包括混合自动重传请求（H-ARQ）简档，传输块大小，功率偏移等。通过在MAC-e处理完成之前将该数据发送到物理层，可以显着放宽等待时间约束。

8. 发明申请

WO2005117329A3 DATA-MOVER CONTROLLER WITH PLURAL REGISTERS FOR SUPPORTING CIPHERING OPERATIONS 审中-公开
标题翻译：数据移动控制器，具有多个用于支持操作的寄存器
公开(公告)号：WO2005117329A3
公开(公告)日：2007-01-11
申请号：PCT/US2005016026
申请日：2005-05-06
申请人： INTERDIGITAL TECH CORP , HEPLER EDWARD L , GAZDA ROBERT G
发明人： HEPLER EDWARD L , GAZDA ROBERT G
IPC分类号： H04L9/18 , G06F12/00 , G06F13/00 , G06F21/00 , H04L9/00 , H04L9/28 , H04L29/06
CPC分类号： H04L63/0428 , G06F21/72 , G06F21/85 , H04W12/02
摘要： A data processing system ciphers and transfers data between a first memory unit and a second memory unit, such as, for example, between a share memory architecture (SMA) static random access memory (SRAM) and a double data rate (DDR) synchronous dynamic random access memory (SDRAM). The system includes a ciphering engine and a data-mover controller. The data-mover controller includes at least one register having a field that specifies whether or not the transferred data should be ciphered. If the field specifies that the transferred data should be ciphered, the field also specifies the type of ciphering that is to be performed, such as a third generation partnership project (3GPP) standardized confidentially cipher algorithm "f8" or integrity cipher algorithm "f9".
摘要翻译：数据处理系统在第一存储器单元和第二存储器单元之间加密和传输数据，例如在共享存储器架构（SMA）静态随机存取存储器（SRAM）和双倍数据速率（DDR）同步动态随机存取存储器（SDRAM）。该系统包括加密引擎和数据移动器控制器。数据移动器控制器包括至少一个具有字段的寄存器，该字段指定所传输的数据是否应被加密。如果该字段指定传输的数据应该被加密，则该字段还指定要执行的加密类型，例如第三代合作伙伴计划（3GPP）标准化的机密密码算法“f8”或完整性密码算法“f9” 。

9. 发明申请

WO2009062066A3 METHODS AND APPARATUSES FOR COMBINED MEDIUM ACCESS CONTROL (MAC) AND RADIO LINK CONTROL (RLC) PROCESSING 审中-公开
标题翻译：用于组合中访问控制（MAC）和无线链路控制（RLC）处理的方法和装置
公开(公告)号：WO2009062066A3
公开(公告)日：2009-10-15
申请号：PCT/US2008082844
申请日：2008-11-07
申请人： INTERDIGITAL TECH CORP , PRAGADA RAVIKUMAR V , HEPLER EDWARD L , GAUVREAU JEAN-LOUIS , MARINIER PAUL , DAVIS JEFFREY T , WANG SHIEHLIE T
发明人： PRAGADA RAVIKUMAR V , HEPLER EDWARD L , GAUVREAU JEAN-LOUIS , MARINIER PAUL , DAVIS JEFFREY T , WANG SHIEHLIE T
IPC分类号： H04W28/06
CPC分类号： H04W28/06 , H04L49/90 , H04L49/901 , H04L69/12 , H04W80/02 , H04W88/02
摘要： A method and apparatus for combined medium access control (MAC) and radio link control (RLC) processing are disclosed. For uplink processing, a combined MAC/RLC (CMR) entity generates an SDU descriptor and allocates protocol data unit (PDU) descriptor resources. A protocol engine (PE) populates a PDU descriptor for each PDU carrying at least a portion of the SDU and generates a MAC PDU in a physical layer shared memory based on the SDU descriptor and the PDU descriptor. The MAC PDU is generated while moving RLC SDU data from the bulk memory to the physical layer shared memory. For downlink processing, received MAC PDUs are stored in the physical layer shared memory. The PE reads MAC and RLC headers in the MAC PDU and populates an SDU segment descriptor (SD) and corresponding PDU descriptors for each SDU segment. The CMR entity merges SDU SDs that comprise a same RLC SDU.
摘要翻译：公开了一种用于组合介质访问控制（MAC）和无线电链路控制（RLC）处理的方法和装置。对于上行链路处理，组合MAC / RLC（CMR）实体生成SDU描述符并分配协议数据单元（PDU）描述符资源。协议引擎（PE）为携带至少一部分SDU的每个PDU填充PDU描述符，并且基于SDU描述符和PDU描述符在物理层共享存储器中生成MAC PDU。在将RLC SDU数据从大容量存储器移动到物理层共享存储器的同时产生MAC PDU。对于下行链路处理，接收到的MAC PDU被存储在物理层共享存储器中。 PE读取MAC PDU中的MAC和RLC头，并为每个SDU段填充SDU段描述符（SD）和相应的PDU描述符。 CMR实体合并构成相同RLC SDU的SDU SD。

10. 发明申请

WO2007005381A8 PROTOCOL ENGINE FOR PROCESSING DATA IN A WIRELESS TRANSMIT/RECEIVE UNIT 审中-公开
标题翻译：无线传输/接收单元处理数据的协议引擎
公开(公告)号：WO2007005381A8
公开(公告)日：2007-05-18
申请号：PCT/US2006024843
申请日：2006-06-27
申请人： INTERDIGITAL TECH CORP , HEPLER EDWARD L , GAZDA ROBERT G , REZNIK ALEXANDER
发明人： HEPLER EDWARD L , GAZDA ROBERT G , REZNIK ALEXANDER
IPC分类号： H04J11/00 , H04W88/02
CPC分类号： G06F13/1663 , H04L49/90 , H04L49/901 , H04L49/9057 , H04L49/9094 , H04L67/04 , H04L69/12 , H04L69/22 , H04L69/324 , H04W88/02
摘要： A protocol engine (PE) for processing data within a protocol stack in a wireless transmit/receive unit (WTRU) is disclosed. The protocol stack executes decision and control operations. The data processing and re-formatting which was performed in a conventional protocol stack is removed from the protocol stack and performed by the PE. The protocol stack issues a control word for processing data and the PE processes the data based on the control word. Preferably, the WTRU includes a shared memory and a second memory. The shared memory is used as a data block place holder to transfer the data amongst processing entities. For transmit processing, the PE retrieves source data from the second memory and processed the data while moving the data to the shared memory based on the control word. For receive processing, the PE retrieves received data from the shared memory and processes it while moving the data to the second memory.
摘要翻译：公开了一种用于处理无线发射/接收单元（WTRU）中的协议栈内的数据的协议引擎（PE）。协议栈执行决策和控制操作。在传统协议栈中执行的数据处理和重新格式化从协议栈中删除，并由PE执行。协议栈发出处理数据的控制字，PE根据控制字处理数据。优选地，WTRU包括共享存储器和第二存储器。共享存储器用作数据块占位符以在处理实体之间传送数据。对于发送处理，PE从第二个存储器检索源数据，并根据该控制字将数据移动到共享存储器处理数据。对于接收处理，PE从共享存储器中检索接收到的数据，并在将数据移动到第二个存储器的同时进行处理。

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