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1. 发明申请

WO2014133705A1 A METHOD, APPARATUS, SYSTEM FOR REPRESENTING, SPECIFYING AND USING DEADLINES 审中-公开
标题翻译：一种用于表示，指定和使用死刑的方法，装置，系统
公开(公告)号：WO2014133705A1
公开(公告)日：2014-09-04
申请号：PCT/US2014/013555
申请日：2014-01-29
申请人： INTEL CORPORATION
发明人： CUTTER, Daniel F. , FANNING, Blaise , NAGARAJAN, Ramadass , IYER, Ravishankar , LE, Quang T. , KOLAGOTLA, Ravi , SCHOINAS, Ioannis T. , NIELL, Jose S.
IPC分类号： G06F13/14 , G06F12/00
CPC分类号： G06F13/00 , G06F9/00 , G06F13/1626 , Y02D10/14
摘要： In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated order identifier and a deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，共享存储器结构被配置为从多个代理接收存储器请求，其中至少一些请求具有相关联的顺序标识符和在完成存储器请求之前指示最大延迟的期限值。响应于请求，结构是至少部分地基于期限值来在请求之间进行仲裁。描述和要求保护其他实施例。

2. 发明申请

WO2014158744A1 A METHOD, APPARATUS, SYSTEM FOR QUALIFYING CPU TRANSACTIONS WITH SECURITY ATTRIBUTES 审中-公开
标题翻译：一种用于对具有安全属性的CPU交易进行质量评估的方法，装置
公开(公告)号：WO2014158744A1
公开(公告)日：2014-10-02
申请号：PCT/US2014/019791
申请日：2014-03-03
申请人： INTEL CORPORATION , SASTRY, Manoj R. , SCHOINAS, Ioannis T. , CERMAK, Daniel M.
发明人： SASTRY, Manoj R. , SCHOINAS, Ioannis T. , CERMAK, Daniel M.
IPC分类号： G06F9/06 , G06F13/14 , G06F21/00
CPC分类号： G06F21/74 , G06F21/57 , G06F21/78
摘要： Method, apparatus, and system for qualifying CPU transactions with security attributes. Immutable security attributes are generated for transactions initiator by a CPU or processor core that identifying the execution mode of the CPU/core being trusted or untrusted. The transactions may be targeted to an Input/Output (I/O) device or system memory via which a protected asset may be accessed. Policy enforcement logic blocks are implemented at various points in the apparatus or system that allow or deny transactions access to protected assets based on the immutable security attributes generated for the transactions. In one aspect, a multiple-level security scheme is implemented under which a mode register is updated via a first transaction to indicate the CPU/core is operating in a trusted execution mode, and security attributes are generated for a second transaction using execution mode indicia in the mode register to verify the transaction is from a trusted initiator.
摘要翻译：用于对具有安全属性的CPU事务进行限定的方法，设备和系统。由CPU或处理器核心为事务发起者生成不可变的安全属性，用于识别CPU /核心被信任或不可信任的执行模式。这些事务可以被定向到可被访问受保护资产的输入/输出（I / O）设备或系统存储器。策略执行逻辑块在设备或系统中的不同点实现，其允许或拒绝事务基于为事务生成的不可变安全属性而访问被保护资产。在一个方面，实现多级安全方案，在该级别下，通过第一事务来更新模式寄存器以指示CPU /核心以可信执行模式运行，并且使用执行模式标记为第二事务生成安全属性在模式寄存器中验证事务来自可信发起者。

3. 发明申请

WO2019066918A1 CRYPTOGRAPHIC MEMORY OWNERSHIP 审中-公开
公开(公告)号：WO2019066918A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/054383
申请日：2017-09-29
申请人： INTEL CORPORATION
发明人： DURHAM, David M. , SAHITA, Ravi , SHANBHOGUE, Vedvyas , HUNTLEY, Barry E. , PATEL, Baiju V. , GERZON, Gideon , SCHOINAS, Ioannis T. , KHOSRAVI, Hormuzd M. , CHHABRA, Siddhartha , ROZAS, Carlos V.
IPC分类号： G06F21/60 , G06F21/62 , H04L9/08 , H04L9/06
摘要： There is disclosed a microprocessor, including : a processing core; and a total memory encryption (TME) engine to provide TME for a first trust domain (TD), and further to: allocate a block of physical memory to the first TD and a first cryptographic key to the first TD; map within an extended page table (EPT) a host physical address (HPA) space to a guest physical address (GPA) space of the TD; create a memory ownership table (MOT) entry for a memory page within the block of physical memory, wherein the MOT table comprises a GPA reverse mapping; encrypt the MOT entry using the first cryptographic key; and append to the MOT entry verification data, wherein the MOT entry verification data enables detection of an attack on the MOT entry.

4. 发明申请

WO2013081589A1 SECURING INPUTS FROM MALWARE 审中-公开
标题翻译：从恶意软件保护输入
公开(公告)号：WO2013081589A1
公开(公告)日：2013-06-06
申请号：PCT/US2011/062498
申请日：2011-11-30
申请人： INTEL CORPORATION , GROBMAN, Steven L. , SCHOINAS, Ioannis T.
发明人： GROBMAN, Steven L. , SCHOINAS, Ioannis T.
IPC分类号： G06F21/24 , G06F21/00
CPC分类号： G06F21/602 , G06F21/83
摘要： A series of touch panel key entries may be secured by shuffling touch entry coordinates. In one embodiment, the entries may be secured by applying a shuffling algorithm that replaces the true coordinates with other incorrect coordinates. Then the correct data may be reassembled in a secure environment.
摘要翻译：可以通过混洗触摸入口坐标来确保一系列触摸面板键入口。在一个实施例中，可以通过应用用其他不正确坐标代替真实坐标的混洗算法来保护条目。然后可以在安全的环境中重新组合正确的数据。

5. 发明申请

WO2014113225A1 ARBITRATING MEMORY ACCESSES VIA A SHARED MEMORY FABRIC 审中-公开
标题翻译：通过一个共享的记忆织物记录存储器
公开(公告)号：WO2014113225A1
公开(公告)日：2014-07-24
申请号：PCT/US2014/010275
申请日：2014-01-06
申请人： INTEL CORPORATION
发明人： CUTTER, Daniel F. , FANNING, Blaise , NAGARAJAN, Ramadass , NIELL, Jose S. , BERNSTEIN, Debra , LIMAYE, Deepak , SCHOINAS, Ioannis T. , IYER, Ravishankar
IPC分类号： G06F13/14 , G06F12/00
CPC分类号： G06F13/1663 , G06F13/1605 , G06F13/161 , G06F2212/1024 , G06F2213/0064 , Y02D10/14
摘要： In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，共享存储器结构被配置为从多个代理接收存储器请求，其中至少一些请求具有关联的最终期限值，以在完成存储器请求之前指示最大等待时间。响应于请求，结构是至少部分地基于期限值来在请求之间进行仲裁。描述和要求保护其他实施例。

6. 发明申请

WO2013095411A1 INCORPORATING ACCESS CONTROL FUNCTIONALITY INTO A SYSTEM ON A CHIP (SoC) 审中-公开
标题翻译：将访问控制功能纳入芯片系统（SoC）
公开(公告)号：WO2013095411A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066355
申请日：2011-12-21
申请人： INTEL CORPORATION , SASTRY, Manoj R. , SCHOINAS, Ioannis T. , TOEPFER, Robert J. , TRIVEDI, Alpa T. Narendra , LONG, Men
发明人： SASTRY, Manoj R. , SCHOINAS, Ioannis T. , TOEPFER, Robert J. , TRIVEDI, Alpa T. Narendra , LONG, Men
IPC分类号： G06F21/22 , G06F13/14
CPC分类号： G06F21/76 , G06F13/385
摘要： In one embodiment, the present invention includes a system on a chip (SoC) that has a first agent with an intellectual property (IP) logic, an interface to a fabric including a target interface, a master interface and a sideband interface, and an access control plug-in unit to handle access control policy for the first agent with respect to incoming and outgoing transactions. This access control plug-in unit can be incorporated into the SoC at integration time and without any modification to the IP logic. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有知识产权（IP）逻辑的第一代理的芯片系统（SoC），包括目标接口，主接口和边带接口的结构的接口，以及访问控制插件单元来处理关于传入和传出事务的第一代理的访问控制策略。该访问控制插件单元可以集成在SoC中，并且不对IP逻辑进行任何修改。描述和要求保护其他实施例。

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