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1. 发明授权

US11923850B2 Parasitic pulse cancelation circuit 有权
公开(公告)号：US11923850B2
公开(公告)日：2024-03-05
申请号：US17715223
申请日：2022-04-07
申请人： INTEVA PRODUCTS, LLC
发明人： François Breynaert
IPC分类号： H03K5/00 , H02P7/00 , H02P7/18 , H02P27/08 , H03K5/1252 , H03K23/58
CPC分类号： H03K23/58 , H02P7/0094 , H02P7/18 , H02P27/08 , H03K5/1252
摘要： A motor control system includes a DC motor and a ripple count circuit. The DC motor includes a rotor that rotates in response to a drive current. The rotation of the rotor generates a mechanical force that drives a component. The ripple count circuit includes an active filter circuit and a parasitic pulse cancellation circuit. The active filter circuit is configured to filter the drive current and to generate a pulsed signal. The parasitic pulse cancelation circuit is in signal communication with the ripple count circuit to receive the pulsed signal and generates a ripple count signal that excludes parasitic pulses included in the pulsed signal having a parasitic voltage level that exceeds a voltage level of a voltage threshold. The parasitic pulse cancelation circuit actively adjusts the voltage level of the voltage threshold based at least in part on a rotational direction of the rotor.

2. 发明授权

US11754442B2 Light-receiving apparatus with cycle setting according to photon count determinations 有权
公开(公告)号：US11754442B2
公开(公告)日：2023-09-12
申请号：US17428408
申请日：2020-03-06
申请人： Sony Semiconductor Solutions Corporation
发明人： Hongbo Zhu , Kazuki Hizu , Takafumi Takatsuka , Yusuke Oike , Jun Ogi , Yoshiaki Tashiro
IPC分类号： G01J1/44 , G01J11/00 , H03K23/58 , H01L31/02 , G02B5/20
CPC分类号： G01J1/44 , G01J11/00 , H01L31/02027 , H03K23/58 , G01J2001/448 , G02B5/20
摘要： A light-receiving apparatus (1a) includes a counting unit (11), a setting unit (12), and an acquiring unit (13). The counting unit is configured to measure a detection number of times that represents the number of times incidence of a photon to a light-receiving element has been detected within an exposure period and to output a counted value. The setting unit is configured to set a cycle of updating time information in accordance with an elapsed time during the exposure period. The acquiring unit is configured to acquire the time information indicating a time at which the counted value reaches a threshold before the exposure period elapses.

3. 发明申请

US20220368331A1 PARASITIC PULSE CANCELATION CIRCUIT 有权
公开(公告)号：US20220368331A1
公开(公告)日：2022-11-17
申请号：US17715223
申请日：2022-04-07
申请人： INTEVA PRODUCTS, LLC
发明人： François Breynaert
IPC分类号： H03K23/58 , H02P7/18 , H02P7/00 , H02P27/08
摘要： A motor control system includes a DC motor and a ripple count circuit. The DC motor includes a rotor that rotates in response to a drive current. The rotation of the rotor generates a mechanical force that drives a component. The ripple count circuit includes an active filter circuit and a parasitic pulse cancellation circuit. The active filter circuit is configured to filter the drive current and to generate a pulsed signal. The parasitic pulse cancelation circuit is in signal communication with the ripple count circuit to receive the pulsed signal and generates a ripple count signal that excludes parasitic pulses included in the pulsed signal having a parasitic voltage level that exceeds a voltage level of a voltage threshold. The parasitic pulse cancelation circuit actively adjusts the voltage level of the voltage threshold based at least in part on a rotational direction of the rotor.

4. 发明授权

US11496080B2 Ripple count circuit including varying ripple threshold detection 有权
公开(公告)号：US11496080B2
公开(公告)日：2022-11-08
申请号：US16960414
申请日：2019-01-09
申请人： INTEVA PRODUCTS FRANCE SAS
发明人： François Breynaert , Simon Herpin
IPC分类号： H02P7/00 , H02P7/285 , H03K23/58
摘要： A motor control system includes a variable voltage supply in signal communication with a direct current (DC) motor. The DC motor includes a rotor induced to rotate in response to a drive current generated by a variable supply voltage delivered by the voltage supply. The rotation of the rotor (103) generates a mechanical force that drives a component. A ripple count circuit (104) is configured to filter the drive current based on a rotational speed (ω) of the rotor (103) to generate a filtered drive current signal, and to generate a varying threshold based on the filtered drive current signal. Based on a comparison between the filtered drive current signal and the varying threshold, the ripple count circuit (104) generates a pulsed output signal indicative of the rotational speed (ω) of the rotor and a rotational position (θ) of the rotor.

5. 发明授权

US09900012B2 Multi-modulus divider with power-of-2 boundary condition support 有权
公开(公告)号：US09900012B2
公开(公告)日：2018-02-20
申请号：US15099753
申请日：2016-04-15
申请人： BAE Systems Information and Electronic Systems Integration Inc.
发明人： Joseph D. Cali , Curtis M. Grens , Lawrence J. Kushner , Steven E. Turner
IPC分类号： H03K21/00 , H03K23/00 , H03K21/02 , H03K21/38 , H03L7/197 , G06F7/68 , H03K23/40 , G06F1/08 , H03K23/64 , H03K21/40 , H03K23/58 , H03K23/68 , H03K21/10
CPC分类号： H03K21/026 , G06F1/08 , G06F7/68 , H03K21/00 , H03K21/10 , H03K21/38 , H03K21/40 , H03K23/00 , H03K23/40 , H03K23/58 , H03K23/64 , H03K23/68 , H03L7/1974
摘要： Frequency divider techniques are disclosed which can be used to address two problems: when an incorrect division occurs if the modulus control changes before the divide cycle is complete, and when an incorrect division occurs due to a boundary crossing (e.g., power-of-2 boundary crossing in a fractional-N PLL application). In one embodiment, a frequency divider is provided comprising a plurality of flip-flops operatively coupled to carry out division of an input frequency, and configured to generate a modulus output and receive a divided clock signal of a previous cell. An additional flip-flop is selectively clocked off one of the modulus output or the divided clock of the previous stage, depending at least in part on a Skip control signal applied to a data input of the additional flip-flop, and is further configured to selectively reset the plurality of flip-flops to a state that will result in a correct divide ratio.

6. 发明授权

US09674471B1 Digital unit cell with bidirectional ripple counter 有权
公开(公告)号：US09674471B1
公开(公告)日：2017-06-06
申请号：US15079631
申请日：2016-03-24
申请人： RAYTHEON COMPANY
发明人： Christian M. Boemler
IPC分类号： H04N5/374 , H04N5/335 , H04N5/378 , H03K23/58 , H04N5/3745
CPC分类号： H04N5/37455 , H03K23/58 , H04N5/378
摘要： Aspects and embodiments are directed to a digital unit cell comprising an integrator circuit, a dynamic comparator configured to compare an integration voltage of the integrator circuit with a reference voltage, provide a first pulse signal each time the integration voltage is less than the reference voltage, and provide a second pulse signal each time the integration voltage exceeds the reference voltage, a multiplexer configured to receive a count direction control signal, and a counter element configured to increment a count value each time the first pulse signal or the second pulse signal is received, wherein the multiplexer is configured to couple a first output of the dynamic comparator to the counter element when the count direction control signal is in a first state, and to couple a second output of the dynamic comparator to the counter element when the count direction control signal is in a second state.

7. 发明授权

US09564904B2 Asynchronous high-speed programmable divider 有权
标题翻译：异步高速可编程分频器
公开(公告)号：US09564904B2
公开(公告)日：2017-02-07
申请号：US14691738
申请日：2015-04-21
申请人： STMicroelectronics International N.V.
发明人： Jeet Narayan Tiwari , Nitin Gupta
IPC分类号： H03K21/00 , H03K23/00 , H03K21/02 , H03K23/68 , H03K23/58 , H03K23/66
CPC分类号： H03K21/026 , H03K21/00 , H03K23/00 , H03K23/58 , H03K23/667 , H03K23/68
摘要： A method of dividing a clock signal by an input signal of N bits with M most significant bits is described herein. The method includes dividing the clock signal by the most significant bits of the input signal 2N-M−1 times out of 2N-M divisions of the clock signal, using a divider. The clock signal is divided by a sum of the most significant bits and the least significant bits one time out of 2N-M divisions of the clock signal, using the divider. The clock signal is also divided by 2N-M, 2N-M times, using the divider.
摘要翻译：本文描述了将时钟信号除以具有M个最高有效位的N位的输入信号的方法。该方法包括使用分频器将时钟信号除以时钟信号的2N-M分频之外的输入信号2N-M-1的最高有效位。使用分频器，将时钟信号除以时钟信号的2N-M分频之外的最高有效位和最低有效位之和。使用分频器也可以将时钟信号除以2N-M，2N-M次。

8. 发明授权

US09438248B2 Low power digital self-gated binary counter 有权
标题翻译：低功率数字自门控二进制计数器
公开(公告)号：US09438248B2
公开(公告)日：2016-09-06
申请号：US14568115
申请日：2014-12-12
申请人： Naman Gupta , Amol Agarwal , Gaurav Goyal
发明人： Naman Gupta , Amol Agarwal , Gaurav Goyal
IPC分类号： H03K21/00 , H03K23/40 , H03K21/12 , H03K21/38 , H03K23/58 , H03K23/00
CPC分类号： H03K23/40 , H03K21/00 , H03K21/12 , H03K21/38 , H03K23/00 , H03K23/58
摘要： An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower-order counter sub-module. The control logic includes a clock-gating integrated cell arranged to clock gate at least one higher-order counter sub-module dependent on a logical combination of outputs of the lower-order counter sub-module and to provide a multi-cycle path for resolution of a logical combination of outputs of any subsequent cascaded counter sub-modules. The control logic does not include any intervening memory device between the lower-order counter sub-module and the clock-gating integrated cell for use in determining a later control logic output.
摘要翻译： n位计数器由级联计数器子模块形成。计数器包括耦合到低阶计数器子模块的组合控制逻辑。控制逻辑包括时钟门控集成单元，其布置成根据低阶计数器子模块的输出的逻辑组合对至少一个高阶计数器子模块进行时钟门控，并提供用于分辨率的多循环路径任何后续级联计数器子模块的输出的逻辑组合。控制逻辑不包括在低阶计数器子模块和时钟门控集成单元之间的任何中间存储器件，用于确定稍后的控制逻辑输出。

9. 发明申请

US20050151594A1 Programmable bandwidth during start-up for phase-lock loop 失效
标题翻译：启动期间的可编程带宽用于锁相环路
公开(公告)号：US20050151594A1
公开(公告)日：2005-07-14
申请号：US10825326
申请日：2004-04-16
申请人： Shyng Chen
发明人： Shyng Chen
IPC分类号： H03K23/58 , H03L7/00 , H03L7/089 , H03L7/107
CPC分类号： H03K23/58 , H03L7/0891 , H03L7/107
摘要： A phase lock loop PLL which includes an oscillator having an oscillator signal whose frequency is related to a received error correction signal and phase frequency detector receiving and comparing the oscillator signal and a reference signal from a master circuit and generating the error correction signal based on the phase difference of the oscillator signal and the reference signal. A filter, including a capacitor, connects the error correction signal from the phase-frequency detector to the oscillator. A rate selector monitors a charge on the capacitor and controls the rate of error connection signals as a function of the charge on the capacitor.
摘要翻译：一种锁相环PLL，其包括具有振荡器信号的振荡器，该振荡器的频率与接收到的纠错信号相关，相位频率检测器接收并比较来自主电路的振荡器信号和参考信号，并基于振荡器信号和参考信号的相位差。包括电容器的滤波器将来自相位频率检测器的纠错信号连接到振荡器。速率选择器监视电容器上的电荷，并根据电容器上的电荷来控制误差连接信号的速率。

10. 发明授权

US5309494A Circuit configuration for generating logical butterfly structures 失效
标题翻译：用于生成逻辑蝶形结构的电路配置
公开(公告)号：US5309494A
公开(公告)日：1994-05-03
申请号：US967680
申请日：1992-10-26
申请人： Udo Grehl
发明人： Udo Grehl
IPC分类号： G06F7/50 , G06F7/505 , G06F7/62 , G11C19/00 , H03K21/14 , H03K23/58 , H03M13/41 , H03K21/02 , H03K21/08 , H03M13/00
CPC分类号： G06F7/5055 , G06F7/62 , G11C19/00 , H03K21/14 , H03K23/58 , H03M13/41
摘要： A circuit configuration includes k linking cells each generating one of k output states from two of k input states. Each of the linking cells have two counters. Each of the counters have a serial data input, a serial data output, and a serial counting width input. The counters increase a counter state loaded through the data input and represent the respectively assigned input state by a value input through the counting width input. Comparators are each connected to the data outputs of two of the counters for serially comparing the two counter states with one another. Multiplexers are each connected to the data outputs of two of the counters for outputting one of the two counter states as an output state under the control of the comparator. Each two further multiplexers are connected upstream of the respective counters and are switched through for loading the counter states with the respectively assigned input states and for comparing the counter states at the data outputs with the counter states at the data inputs of the respective counters.
摘要翻译：电路配置包括k个链路单元，每个链路单元从k个输入状态中的两个产生k个输出状态之一。每个链接单元都有两个计数器。每个计数器都有串行数据输入，串行数据输出和串行计数宽度输入。计数器增加通过数据输入加载的计数器状态，并通过计数宽度输入输入的值表示分配的输入状态。比较器各自连接到两个计数器的数据输出，用于将两个计数器状态彼此串行比较。多路复用器各自连接到两个计数器的数据输出，用于在比较器的控制下输出两个计数器状态之一作为输出状态。每两个进一步的多路复用器连接在相应计数器的上游，并被切换以加载具有分配的输入状态的计数器状态，并用于将数据输出处的计数器状态与各个计数器的数据输入处的计数器状态进行比较。

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