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1. 发明授权

US09306576B2 Modular gray code counter 有权
标题翻译：模块化灰色代码计数器
公开(公告)号：US09306576B2
公开(公告)日：2016-04-05
申请号：US14495876
申请日：2014-09-24
申请人： Naman Gupta , Gaurav Goyal , Rohit Goyal
发明人： Naman Gupta , Gaurav Goyal , Rohit Goyal
IPC分类号： H03K21/00 , H03K23/00
CPC分类号： H03K23/005
摘要： A Gray code counter has multiple two-bit Gray code counter modules, clock gated integrated cells (CGICs), and a parity bit generator. The CGICs gate clock signals provided to the two-bit counter modules, which reduces dynamic power consumption. The parity bit generator generates a parity bit that indicates a count of binary ones in a counting state.
摘要翻译：格雷码计数器具有多个两位格雷码计数器模块，时钟门控集成单元（CGIC）和奇偶校验位发生器。提供给两位计数器模块的CGIC门控时钟信号降低了动态功耗。奇偶校验位产生器产生一个奇偶校验位，它表示计数状态下的二进制计数。

2. 发明授权

US08983023B2 Digital self-gated binary counter 有权
标题翻译：数字自门二进制计数器
公开(公告)号：US08983023B2
公开(公告)日：2015-03-17
申请号：US13935552
申请日：2013-07-04
申请人： Naman Gupta , Amol Agarwal , Gaurav Goyal
发明人： Naman Gupta , Amol Agarwal , Gaurav Goyal
IPC分类号： H03K23/00 , H03K23/40 , H03K21/12 , H03K21/38 , H03K23/58
CPC分类号： H03K23/40 , H03K21/00 , H03K21/12 , H03K21/38 , H03K23/00 , H03K23/58
摘要： An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower order counter sub-module. The control logic is arranged to clock gate at least one higher order counter sub-module dependent on a logical combination of outputs of the lower order counter sub-module and where the control logic uses pipelining to store at least one previous control logic output for use in determining a later control logic output.
摘要翻译： n位计数器由级联计数器子模块形成。计数器包括耦合到低阶计数器子模块的组合控制逻辑。控制逻辑被配置为根据低阶计数器子模块的输出的逻辑组合对至少一个更高阶计数器子模块进行时钟门控，并且其中控制逻辑使用流水线存储至少一个先前控制逻辑输出以供使用在确定稍后的控制逻辑输出时。

3. 发明申请

US20140253215A1 BINARY ADDER AND MULTIPLIER CIRCUIT 有权
标题翻译：二进制和多路复用电路
公开(公告)号：US20140253215A1
公开(公告)日：2014-09-11
申请号：US14077198
申请日：2013-11-11
申请人： Rohit Goyal , Amit Kumar Dey , Naman Gupta
发明人： Rohit Goyal , Amit Kumar Dey , Naman Gupta
IPC分类号： G06G7/32
CPC分类号： G06F7/5272 , G06F7/507
摘要： An adder circuit includes first through fourth two-bit adder modules, and first through third result mux blocks for receiving and adding first and second binary values to generate a final sum. A multiplier circuit that multiplies a multiplier and a multiplicand includes a multiplexer, an encoder connected to the multiplexer, a shifter connected to the encoder, and an accumulator connected to the encoder for receiving the multiplier and multiplicand and generating a multiplication product.
摘要翻译：加法器电路包括第一至第四二位加法器模块，以及第一至第三结果多路复用块，用于接收和添加第一和第二二进制值以产生最终和。乘法器和乘法器的乘法器电路包括复用器，连接到多路复用器的编码器，连接到编码器的移位器和连接到编码器的累加器，用于接收乘法器并被乘法并产生乘积。

4. 发明授权

US09438248B2 Low power digital self-gated binary counter 有权
标题翻译：低功率数字自门控二进制计数器
公开(公告)号：US09438248B2
公开(公告)日：2016-09-06
申请号：US14568115
申请日：2014-12-12
申请人： Naman Gupta , Amol Agarwal , Gaurav Goyal
发明人： Naman Gupta , Amol Agarwal , Gaurav Goyal
IPC分类号： H03K21/00 , H03K23/40 , H03K21/12 , H03K21/38 , H03K23/58 , H03K23/00
CPC分类号： H03K23/40 , H03K21/00 , H03K21/12 , H03K21/38 , H03K23/00 , H03K23/58
摘要： An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower-order counter sub-module. The control logic includes a clock-gating integrated cell arranged to clock gate at least one higher-order counter sub-module dependent on a logical combination of outputs of the lower-order counter sub-module and to provide a multi-cycle path for resolution of a logical combination of outputs of any subsequent cascaded counter sub-modules. The control logic does not include any intervening memory device between the lower-order counter sub-module and the clock-gating integrated cell for use in determining a later control logic output.
摘要翻译： n位计数器由级联计数器子模块形成。计数器包括耦合到低阶计数器子模块的组合控制逻辑。控制逻辑包括时钟门控集成单元，其布置成根据低阶计数器子模块的输出的逻辑组合对至少一个高阶计数器子模块进行时钟门控，并提供用于分辨率的多循环路径任何后续级联计数器子模块的输出的逻辑组合。控制逻辑不包括在低阶计数器子模块和时钟门控集成单元之间的任何中间存储器件，用于确定稍后的控制逻辑输出。

5. 发明申请

US20160173106A1 LOW POWER DIGITAL SELF-GATED BINARY COUNTER 有权
标题翻译：低功率数字自选二进制计数器
公开(公告)号：US20160173106A1
公开(公告)日：2016-06-16
申请号：US14568115
申请日：2014-12-12
申请人： Naman Gupta , Amol Agarwal , Gaurav Goyal
发明人： Naman Gupta , Amol Agarwal , Gaurav Goyal
IPC分类号： H03K23/40 , H03K21/00
CPC分类号： H03K23/40 , H03K21/00 , H03K21/12 , H03K21/38 , H03K23/00 , H03K23/58
摘要： An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower-order counter sub-module. The control logic includes a clock-gating integrated cell arranged to clock gate at least one higher-order counter sub-module dependent on a logical combination of outputs of the lower-order counter sub-module and to provide a multi-cycle path for resolution of a logical combination of outputs of any subsequent cascaded counter sub-modules. The control logic does not include any intervening memory device between the lower-order counter sub-module and the clock-gating integrated cell for use in determining a later control logic output.
摘要翻译： n位计数器由级联计数器子模块形成。计数器包括耦合到低阶计数器子模块的组合控制逻辑。控制逻辑包括时钟门控集成单元，其布置成根据低阶计数器子模块的输出的逻辑组合对至少一个高阶计数器子模块进行时钟门控，并提供用于分辨率的多循环路径任何后续级联计数器子模块的输出的逻辑组合。控制逻辑不包括在低阶计数器子模块和时钟门控集成单元之间的任何中间存储器件，用于确定稍后的控制逻辑输出。

6. 发明授权

US09201116B1 Method of generating test patterns for detecting small delay defects 有权
标题翻译：生成用于检测小延迟缺陷的测试模式的方法
公开(公告)号：US09201116B1
公开(公告)日：2015-12-01
申请号：US14340572
申请日：2014-07-25
申请人： Anurag Jindal , Naman Gupta , Sagar Kataria , Pragya Shukla
发明人： Anurag Jindal , Naman Gupta , Sagar Kataria , Pragya Shukla
IPC分类号： G01R31/28 , G01R31/3177
CPC分类号： G01R31/318328
摘要： A method of generating test patterns for testing a semiconductor processor for small delay defects (SDD) includes modifying interconnect delay values of interconnect paths by introducing values corresponding to (i) set-up and clock to Q delays of elements in the paths and (ii) latencies of associated clock networks. Critical nodes are selected and test patterns targeting the selected critical nodes are generated using timing slack resulting from the modified interconnect delays. A first selection of nodes that are critical in at-speed scan mode testing and a second selection of nodes that are critical in functional mode testing are made by static timing analysis (STA). Only the nodes featuring in both the first and second selections are selected for targeting small delay defects using at-speed scan test patterns.
摘要翻译：产生用于测试用于小延迟缺陷（SDD）的半导体处理器的测试图案的方法包括通过将对应于（i）设置和时钟的值引入到路径中的元素的Q延迟来修改互连路径的互连延迟值，）相关时钟网络的延迟。选择关键节点，并使用由修改的互连延迟导致的定时松弛来生成针对所选关键节点的测试模式。在速度扫描模式测试中关键的节点的第一选择和在功能模式测试中关键的节点的第二选择是通过静态时序分析（STA）进行的。选择在第一和第二选择中特征的节点，以使用高速扫描测试图案来瞄准小的延迟缺陷。

7. 发明申请

US20150188546A1 HYBRID SYNCHRONOUS/ASYNCHRONOUS COUNTER 有权
标题翻译：混合同步/异步计数器
公开(公告)号：US20150188546A1
公开(公告)日：2015-07-02
申请号：US14141458
申请日：2013-12-27
申请人： Rohit Goyal , Deepak Kumar Behera , Naman Gupta
发明人： Rohit Goyal , Deepak Kumar Behera , Naman Gupta
IPC分类号： H03K23/58 , H03K3/012 , H03K21/10
CPC分类号： H03K23/588 , H03K19/0008 , H03K21/10 , H03K21/12 , H03K23/58
摘要： A hybrid counter generates a multi-bit hybrid counter value. The hybrid counter includes two or more asynchronous counters, each configured to generate a subset of the bits of the multi-bit hybrid counter value. The asynchronous counters are interconnected by a logic gate and a clock gating circuit. The logic gate generates an asynchronous logic value based on the bits generated by the previous asynchronous counters. The clock gating circuit re-times the asynchronous logic value to generate a synchronous logic value that is used to toggle the next asynchronous counter. The hybrid counter functions more accurately than conventional asynchronous counters and with less power than conventional synchronous counters.
摘要翻译：混合计数器产生多位混合计数器值。混合计数器包括两个或多个异步计数器，每个异步计数器被配置为生成多比特混合计数器值的比特的子集。异步计数器由逻辑门和时钟门控电路互连。逻辑门根据以前的异步计数器产生的位产生异步逻辑值。时钟门控电路重新计时异步逻辑值以产生用于切换下一个异步计数器的同步逻辑值。混合计数器的功能比传统的异步计数器更精确，功耗比传统的同步计数器少。

8. 发明申请

US20150010124A1 DIGITAL SELF-GATED BINARY COUNTER 有权
标题翻译：数字自选二进制计数器
公开(公告)号：US20150010124A1
公开(公告)日：2015-01-08
申请号：US13935552
申请日：2013-07-04
申请人： Naman Gupta , Amol Agarwal , Gaurav Goyal
发明人： Naman Gupta , Amol Agarwal , Gaurav Goyal
IPC分类号： H03K23/40
CPC分类号： H03K23/40 , H03K21/00 , H03K21/12 , H03K21/38 , H03K23/00 , H03K23/58
摘要： An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower order counter sub-module. The control logic is arranged to clock gate at least one higher order counter sub-module dependent on a logical combination of outputs of the lower order counter sub-module and where the control logic uses pipelining to store at least one previous control logic output for use in determining a later control logic output.
摘要翻译： n位计数器由级联计数器子模块形成。计数器包括耦合到低阶计数器子模块的组合控制逻辑。控制逻辑被配置为根据低阶计数器子模块的输出的逻辑组合对至少一个更高阶计数器子模块进行时钟门控，并且其中控制逻辑使用流水线存储至少一个先前控制逻辑输出以供使用在确定稍后的控制逻辑输出时。

9. 发明授权

US08867694B1 Modular gray code counter 有权
标题翻译：模块化灰色代码计数器
公开(公告)号：US08867694B1
公开(公告)日：2014-10-21
申请号：US13945937
申请日：2013-07-19
申请人： Naman Gupta , Gaurav Goyal , Rohit Goyal
发明人： Naman Gupta , Gaurav Goyal , Rohit Goyal
IPC分类号： H03K21/00 , H03K23/00
CPC分类号： H03K23/005
摘要： A Gray code counter has multiple two-bit Gray code counter modules, clock gated integrated cells (CGICs), and a parity bit generator. The CGICs gate clock signals provided to the two-bit counter modules, which reduces dynamic power consumption. The parity bit generator generates a parity bit that indicates a count of binary ones in a counting state.
摘要翻译：格雷码计数器具有多个两位格雷码计数器模块，时钟门控集成单元（CGIC）和奇偶校验位发生器。提供给两位计数器模块的CGIC门控时钟信号降低了动态功耗。奇偶校验位产生器产生一个奇偶校验位，它表示计数状态下的二进制计数。

10. 发明授权

US09294099B2 Hybrid synchronous/asynchronous counter 有权
标题翻译：混合同步/异步计数器
公开(公告)号：US09294099B2
公开(公告)日：2016-03-22
申请号：US14141458
申请日：2013-12-27
申请人： Rohit Goyal , Deepak Kumar Behera , Naman Gupta
发明人： Rohit Goyal , Deepak Kumar Behera , Naman Gupta
IPC分类号： H03K21/00 , H03K23/58 , H03K19/00 , H03K21/10 , H03K21/12
CPC分类号： H03K23/588 , H03K19/0008 , H03K21/10 , H03K21/12 , H03K23/58
摘要： A hybrid counter generates a multi-bit hybrid counter value. The hybrid counter includes two or more asynchronous counters, each configured to generate a subset of the bits of the multi-bit hybrid counter value. The asynchronous counters are interconnected by a logic gate and a clock gating circuit. The logic gate generates an asynchronous logic value based on the bits generated by the previous asynchronous counters. The clock gating circuit re-times the asynchronous logic value to generate a synchronous logic value that is used to toggle the next asynchronous counter. The hybrid counter functions more accurately than conventional asynchronous counters and with less power than conventional synchronous counters.
摘要翻译：混合计数器产生多位混合计数器值。混合计数器包括两个或多个异步计数器，每个异步计数器被配置为生成多比特混合计数器值的比特的子集。异步计数器由逻辑门和时钟门控电路互连。逻辑门根据以前的异步计数器产生的位产生异步逻辑值。时钟门控电路重新计时异步逻辑值以产生用于切换下一个异步计数器的同步逻辑值。混合计数器的功能比传统的异步计数器更精确，功耗比传统的同步计数器少。

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