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1. 发明授权

US08983023B2 Digital self-gated binary counter 有权
标题翻译：数字自门二进制计数器
公开(公告)号：US08983023B2
公开(公告)日：2015-03-17
申请号：US13935552
申请日：2013-07-04
申请人： Naman Gupta , Amol Agarwal , Gaurav Goyal
发明人： Naman Gupta , Amol Agarwal , Gaurav Goyal
IPC分类号： H03K23/00 , H03K23/40 , H03K21/12 , H03K21/38 , H03K23/58
CPC分类号： H03K23/40 , H03K21/00 , H03K21/12 , H03K21/38 , H03K23/00 , H03K23/58
摘要： An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower order counter sub-module. The control logic is arranged to clock gate at least one higher order counter sub-module dependent on a logical combination of outputs of the lower order counter sub-module and where the control logic uses pipelining to store at least one previous control logic output for use in determining a later control logic output.
摘要翻译： n位计数器由级联计数器子模块形成。计数器包括耦合到低阶计数器子模块的组合控制逻辑。控制逻辑被配置为根据低阶计数器子模块的输出的逻辑组合对至少一个更高阶计数器子模块进行时钟门控，并且其中控制逻辑使用流水线存储至少一个先前控制逻辑输出以供使用在确定稍后的控制逻辑输出时。

2. 发明授权

US08063685B1 Pulsed flip-flop circuit 有权
标题翻译：脉冲触发器电路
公开(公告)号：US08063685B1
公开(公告)日：2011-11-22
申请号：US12852514
申请日：2010-08-08
申请人： Kapil Narula , Amol Agarwal , Sumeet Aggarwal , Sunit K. Bansal , Sabaa Sandhu , Harkaran Singh
发明人： Kapil Narula , Amol Agarwal , Sumeet Aggarwal , Sunit K. Bansal , Sabaa Sandhu , Harkaran Singh
IPC分类号： H03K3/00
CPC分类号： H03K3/012 , H03K3/356121
摘要： A flip-flop circuit includes a data input, a clock input for receiving a clock signal having active edges and inactive edges, a data output, an input circuit, a pulse generator, and a latch. The input circuit sets first and second nodes to different initial logic states in response to an inactive edge of the clock signal, and selectively changes the logic state of either the first node or the second node in response to a pulse input signal to control the state of a third node, such that the selection depends on the logic state of the data input. The pulse generator circuit enables the pulse input signal in response to an active edge of the clock signal, and disables the pulse input signal in response to detecting the change in the initial logic state of either the first node or the second node. The latch stores a data output signal for output at the data output, the data output signal depending on the logic state of the third node.
摘要翻译：触发器电路包括数据输入端，用于接收具有有效边沿和无效边沿的时钟信号的时钟输入，数据输出，输入电路，脉冲发生器和锁存器。输入电路响应于时钟信号的不活动边缘将第一和第二节点设置到不同的初始逻辑状态，并且响应于脉冲输入信号选择性地改变第一节点或第二节点的逻辑状态以控制状态第三节点的选择取决于数据输入的逻辑状态。脉冲发生器电路响应于时钟信号的有效沿使能脉冲输入信号，并且响应于检测到第一节点或第二节点的初始逻辑状态的变化而禁用脉冲输入信号。锁存器存储用于在数据输出端输出的数据输出信号，数据输出信号取决于第三节点的逻辑状态。

3. 发明授权

US09438248B2 Low power digital self-gated binary counter 有权
标题翻译：低功率数字自门控二进制计数器
公开(公告)号：US09438248B2
公开(公告)日：2016-09-06
申请号：US14568115
申请日：2014-12-12
申请人： Naman Gupta , Amol Agarwal , Gaurav Goyal
发明人： Naman Gupta , Amol Agarwal , Gaurav Goyal
IPC分类号： H03K21/00 , H03K23/40 , H03K21/12 , H03K21/38 , H03K23/58 , H03K23/00
CPC分类号： H03K23/40 , H03K21/00 , H03K21/12 , H03K21/38 , H03K23/00 , H03K23/58
摘要： An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower-order counter sub-module. The control logic includes a clock-gating integrated cell arranged to clock gate at least one higher-order counter sub-module dependent on a logical combination of outputs of the lower-order counter sub-module and to provide a multi-cycle path for resolution of a logical combination of outputs of any subsequent cascaded counter sub-modules. The control logic does not include any intervening memory device between the lower-order counter sub-module and the clock-gating integrated cell for use in determining a later control logic output.
摘要翻译： n位计数器由级联计数器子模块形成。计数器包括耦合到低阶计数器子模块的组合控制逻辑。控制逻辑包括时钟门控集成单元，其布置成根据低阶计数器子模块的输出的逻辑组合对至少一个高阶计数器子模块进行时钟门控，并提供用于分辨率的多循环路径任何后续级联计数器子模块的输出的逻辑组合。控制逻辑不包括在低阶计数器子模块和时钟门控集成单元之间的任何中间存储器件，用于确定稍后的控制逻辑输出。

4. 发明申请

US20160173106A1 LOW POWER DIGITAL SELF-GATED BINARY COUNTER 有权
标题翻译：低功率数字自选二进制计数器
公开(公告)号：US20160173106A1
公开(公告)日：2016-06-16
申请号：US14568115
申请日：2014-12-12
申请人： Naman Gupta , Amol Agarwal , Gaurav Goyal
发明人： Naman Gupta , Amol Agarwal , Gaurav Goyal
IPC分类号： H03K23/40 , H03K21/00
CPC分类号： H03K23/40 , H03K21/00 , H03K21/12 , H03K21/38 , H03K23/00 , H03K23/58
摘要： An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower-order counter sub-module. The control logic includes a clock-gating integrated cell arranged to clock gate at least one higher-order counter sub-module dependent on a logical combination of outputs of the lower-order counter sub-module and to provide a multi-cycle path for resolution of a logical combination of outputs of any subsequent cascaded counter sub-modules. The control logic does not include any intervening memory device between the lower-order counter sub-module and the clock-gating integrated cell for use in determining a later control logic output.
摘要翻译： n位计数器由级联计数器子模块形成。计数器包括耦合到低阶计数器子模块的组合控制逻辑。控制逻辑包括时钟门控集成单元，其布置成根据低阶计数器子模块的输出的逻辑组合对至少一个高阶计数器子模块进行时钟门控，并提供用于分辨率的多循环路径任何后续级联计数器子模块的输出的逻辑组合。控制逻辑不包括在低阶计数器子模块和时钟门控集成单元之间的任何中间存储器件，用于确定稍后的控制逻辑输出。

5. 发明授权

US09081061B1 Scan flip-flop 有权
标题翻译：扫描触发器
公开(公告)号：US09081061B1
公开(公告)日：2015-07-14
申请号：US14262789
申请日：2014-04-27
申请人： Amol Agarwal , Gaurav Goyal , Reecha Jajodia
发明人： Amol Agarwal , Gaurav Goyal , Reecha Jajodia
IPC分类号： H03K19/173 , G01R31/3177
CPC分类号： G01R31/318541
摘要： A scan flip-flop includes a multiplexer, a flip-flop, and a logic circuit. The flip-flop includes a transmission gate that has two sets of clock-controlled transistors. The combined width of the clock-controlled transistors in a set equals the width of the single transistor commonly used in known scan flip-flop circuits. The logic circuit inhibits the clock signal from reaching one transistor of each set during scan mode, which reduces power consumption without sacrificing speed of operation.
摘要翻译：扫描触发器包括多路复用器，触发器和逻辑电路。触发器包括具有两组时钟控制晶体管的传输门。集合中的时钟控制晶体管的组合宽度等于已知扫描触发器电路中常用的单个晶体管的宽度。逻辑电路在扫描模式期间阻止时钟信号到达每组的一个晶体管，这降低了功耗，而不牺牲操作速度。

6. 发明申请

US20150010124A1 DIGITAL SELF-GATED BINARY COUNTER 有权
标题翻译：数字自选二进制计数器
公开(公告)号：US20150010124A1
公开(公告)日：2015-01-08
申请号：US13935552
申请日：2013-07-04
申请人： Naman Gupta , Amol Agarwal , Gaurav Goyal
发明人： Naman Gupta , Amol Agarwal , Gaurav Goyal
IPC分类号： H03K23/40
CPC分类号： H03K23/40 , H03K21/00 , H03K21/12 , H03K21/38 , H03K23/00 , H03K23/58
摘要： An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower order counter sub-module. The control logic is arranged to clock gate at least one higher order counter sub-module dependent on a logical combination of outputs of the lower order counter sub-module and where the control logic uses pipelining to store at least one previous control logic output for use in determining a later control logic output.
摘要翻译： n位计数器由级联计数器子模块形成。计数器包括耦合到低阶计数器子模块的组合控制逻辑。控制逻辑被配置为根据低阶计数器子模块的输出的逻辑组合对至少一个更高阶计数器子模块进行时钟门控，并且其中控制逻辑使用流水线存储至少一个先前控制逻辑输出以供使用在确定稍后的控制逻辑输出时。

7. 发明授权

US09311438B1 Signal delay flip-flop cell for fixing hold time violation 有权
标题翻译：用于固定保持时间违规的信号延迟触发器单元
公开(公告)号：US09311438B1
公开(公告)日：2016-04-12
申请号：US14509037
申请日：2014-10-07
申请人： Amol Agarwal , Gaurav Goyal , Abhishek Mahajan , Sidhartha Taneja
发明人： Amol Agarwal , Gaurav Goyal , Abhishek Mahajan , Sidhartha Taneja
IPC分类号： G06F17/50 , H03K3/037 , H03K3/012
CPC分类号： G06F17/5031 , G06F2217/02 , G06F2217/84 , H03K3/012 , H03K3/0372 , H03K3/0375
摘要： A signal delay cell for use in resolving hold time violations in an IC has a first multiplexer having a first functional data input node and a scan data input node TI and a second multiplexer having a second functional data input node, a second input node connected to the output of the first multiplexer and a flip-flop module. The propagation of a data input signal applied to the first multiplexer is delayed, and the hold margin of the flip-flop module is increased by transit through the first multiplexer. The signal delay cell is available to replace a flip-flop having a scan data hold problem, and also for use in solving a functional data violation in the same or another cell.
摘要翻译：用于解决IC中的保持时间冲突的信号延迟单元具有第一多路复用器，其具有第一功能数据输入节点和扫描数据输入节点TI，第二多路复用器具有第二功能数据输入节点，第二输入节点连接到第一多路复用器和触发器模块的输出。施加到第一多路复用器的数据输入信号的传播被延迟，并且通过第一多路复用器的传输来增加触发器模块的保持余量。信号延迟单元可用于替换具有扫描数据保持问题的触发器，并且还用于解决相同或另一个单元中的功能数据违例。

8. 发明申请

US20160098506A1 SIGNAL DELAY FLIP-FLOP CELL FOR FIXING HOLD TIME VIOLATION 有权
标题翻译：信号延迟翻转细胞固定持续时间
公开(公告)号：US20160098506A1
公开(公告)日：2016-04-07
申请号：US14509037
申请日：2014-10-07
申请人： Amol Agarwal , Gaurav Goyal , Abhishek Mahajan , Sidharrtha Taneja
发明人： Amol Agarwal , Gaurav Goyal , Abhishek Mahajan , Sidharrtha Taneja
IPC分类号： G06F17/50 , H03K3/012 , H03K3/037
CPC分类号： G06F17/5031 , G06F2217/02 , G06F2217/84 , H03K3/012 , H03K3/0372 , H03K3/0375
摘要： A signal delay cell for use in resolving hold time violations in an IC has a first multiplexer having a first functional data input node and a scan data input node TI and a second multiplexer having a second functional data input node, a second input node connected to the output of the first multiplexer and a flip-flop module. The propagation of a data input signal applied to the first multiplexer is delayed, and the hold margin of the flip-flop module is increased by transit through the first multiplexer. The signal delay cell is available to replace a flip-flop having a scan data hold problem, and also for use in solving a functional data violation in the same or another cell.
摘要翻译：用于解决IC中的保持时间冲突的信号延迟单元具有第一多路复用器，其具有第一功能数据输入节点和扫描数据输入节点TI，第二多路复用器具有第二功能数据输入节点，第二输入节点连接到第一多路复用器和触发器模块的输出。施加到第一多路复用器的数据输入信号的传播被延迟，并且通过第一多路复用器的传输来增加触发器模块的保持余量。信号延迟单元可用于替换具有扫描数据保持问题的触发器，并且还用于解决相同或另一个单元中的功能数据违例。

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