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    • 3. 发明授权
    • Distributed precharge wire-or bus
    • 分布式预充电线或母线
    • US4808855A
    • 1989-02-28
    • US133324
    • 1987-12-16
    • Stacey G. Lloyd
    • Stacey G. Lloyd
    • G06F3/00H03K17/0412H03K17/12H04L25/02H03K3/013H03K3/355H03K5/05H03K17/04
    • H03K17/122H03K17/04126H03K17/12
    • A plurality of bus-coupler circuits (14) are connected to a bus wire (10) at different points (12) along its length. Each bus-coupler circuit (14) includes a conventional bus driver (22) which may, for example, comprise a relatively large transistor, but also a bus precharge circuit (16). The bus precharge circuit (16) in each bus-coupler circuit responds to a control signal (20) to apply a small, precharge pulse to the bus wire (10). The control signal (20) is applied to each of the bus-coupler circuits (22) in synchronism with the data (38) in such a way that electrical precharge pulses are applied to the bus wire (10) substantially simultaneously by each bus coupler at approximately the instant of time of an expected data signal transition. In this way, the bus wire (10) receives a small electrical charge (24) at the various points along its length at which the bus coupler circuits are connected. The bus is thereby precharged in anticipation of a transition. The electrical charge is insufficient to substantially change the voltage level at any given local point on the bus; however, its total effect is to significantly reduce the rise time of a bus transition. The electrical charge is sufficient to precharge the capacitive load formed by the bus wire and the bus driver transistors in the immediate vicinity of the charging point. Since the electrical precharge is injected onto the bus by each bus precharge circuit at a number of points along its length, the entire bus wire receives a charge in anticipation of a data transition at any of the circuits (14) along the bus. Consequently, a single, large bus-driver transistor is not required to change the voltage level of the entire bus.
    • 多个总线耦合器电路(14)沿其长度在不同的点(12)处连接到总线(10)。 每个总线耦合器电路(14)包括常规的总线驱动器(22),其可以例如包括相对较大的晶体管,而且还包括总线预充电电路(16)。 每个总线耦合器电路中的总线预充电电路(16)响应控制信号(20),以向母线(10)施加小的预充电脉冲。 控制信号(20)以与数据(38)同步的方式施加到每个总线耦合器电路(22),使得预充电脉冲基本上同时由每个总线耦合器施加到总线(10) 大约在预期数据信号转换的时刻。 以这种方式,母线(10)沿着连接总线耦合器电路的长度的各个点处接收小的电荷(24)。 因此,公共汽车预计会过渡。 电荷不足以基本上改变总线上任何给定的局部点处的电压电平; 然而,其总体效果是显着减少公交车过渡的上升时间。 电荷足以预先对由充电点附近的总线和总线驱动晶体管形成的电容性负载进行预充电。 由于每个总线预充电电路沿着其长度的多个点将电预充电注入到总线上,所以整个总线线预期沿着总线在任何电路(14)处的数据转换期间接收电荷。 因此,不需要单个大型总线驱动晶体管来改变整个总线的电压电平。
    • 10. 发明授权
    • Integrated circuit one shot with extended length output pulse
    • 集成电路一次扩展长度输出脉冲
    • US5498989A
    • 1996-03-12
    • US230045
    • 1994-04-19
    • Sholeh Diba
    • Sholeh Diba
    • H03K3/033H03K5/1534H03K3/355
    • H03K5/1534H03K3/033
    • An integrated circuit one shot circuit provides relatively long duration (hundreds of nanoseconds up to a millisecond) output pulses without the need for excessively large transistors. The one shot circuit includes a pull up and a pull down device connected to the one shot circuit's input terminal, with a latch connected to a node between the pull up and pull down devices. The output terminal of the latch is connected to the input of a Schmitt trigger. One terminal of a grounded capacitor is connected between the latch output terminal and the Schmitt trigger input. The output terminal of the Schmitt trigger is connected through an inverter to one input terminal of a NAND gate, the other input terminal of which is connected to the one shot circuit's input terminal. A feedback line connects the output terminal of the NAND gate to the gate of a depletion mode transistor which is between the pull up and pull down devices. This provides a glitch free long duration output pulse using conventional CMOS transistor fabrication technology in a large scale integrated circuit.
    • 集成电路单触发电路提供相对较长的持续时间(几百纳秒直到毫秒)的输出脉冲,而不需要过大的晶体管。 单触发电路包括连接到单触发电路的输入端的上拉和下拉器件,其中锁存器连接到上拉和下拉器件之间的节点。 锁存器的输出端子连接到施密特触发器的输入端。 接地电容器的一个端子连接在锁存器输出端子和施密特触发器输入端之间。 施密特触发器的输出端子通过反相器连接到NAND门的一个输入端,其另一个输入端连接到单触发电路的输入端。 反馈线将NAND门的输出端连接到上拉和下拉器件之间的耗尽型晶体管的栅极。 这在大规模集成电路中使用传统的CMOS晶体管制造技术提供无故障长时间输出脉冲。