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1. 发明授权

US06759873B2 Reverse biasing logic circuit 有权
标题翻译：反向偏置逻辑电路
公开(公告)号：US06759873B2
公开(公告)日：2004-07-06
申请号：US10153158
申请日：2002-05-21
申请人： Sung-Mo Kang , Seung-Moon Yoo
发明人： Sung-Mo Kang , Seung-Moon Yoo
IPC分类号： H03K190185
CPC分类号： H03K19/0016
摘要： A reverse biasing logic circuit is disclosed for limiting standby leakage electric current losses during circuit operation. The circuit includes a logic function circuit having one or more logic transistors that receive an input and perform a logic function operation to generate an output. A power source transistor connects to the logic function circuit and receives a control signal that changes node voltages of the one or more logic transistors between an active mode and a standby mode. During the standby mode, the power source transistor causes reverse biasing of at least one of the one or more logic transistors which prevents a leakage electric current flow between the power source transistor and the one or more logic transistors.
摘要翻译：公开了一种反向偏置逻辑电路，用于在电路操作期间限制备用漏电流损耗。该电路包括具有一个或多个逻辑晶体管的逻辑功能电路，其接收输入并执行逻辑功能操作以产生输出。电源晶体管连接到逻辑功能电路并接收在主动模式和待机模式之间改变一个或多个逻辑晶体管的节点电压的控制信号。在待机模式期间，电源晶体管引起一个或多个逻辑晶体管中的至少一个逻辑晶体管的反向偏置，从而防止电源晶体管和一个或多个逻辑晶体管之间的漏电流流动。

2. 发明授权

US06756810B2 Apparatus and method to provide a single reference component for multiple circuit compensation using digital impedance code shifting 有权
标题翻译：提供使用数字阻抗代码转换的多个电路补偿的单个参考分量的装置和方法
公开(公告)号：US06756810B2
公开(公告)日：2004-06-29
申请号：US10360268
申请日：2003-02-06
申请人： Usman A. Mughal , Razi Uddin , Chee How Lim , Steven A. Peterson
发明人： Usman A. Mughal , Razi Uddin , Chee How Lim , Steven A. Peterson
IPC分类号： H03K190185
CPC分类号： H04L25/0298 , H03K19/00384 , H04L25/026 , H04L25/0272
摘要： A single external impedance element is used to perform multiple circuit compensation. A reference impedance code is first generated based on matching an internal impedance generated by transistors with an impedance of the external impedance element, and then the reference impedance code can be shifted to generate new impedance codes according to impedance requirements of various different circuits that require compensation. Use of the single external impedance element for compensation of multiple circuits reduces motherboard and packaging costs. Chip area is also conserved since simpler compensation circuits can be used.
摘要翻译：单个外部阻抗元件用于执行多路电路补偿。首先基于将由晶体管产生的内部阻抗与外部阻抗元件的阻抗进行匹配来产生参考阻抗代码，然后可以根据需要补偿的各种不同电路的阻抗要求，移动参考阻抗代码以产生新的阻抗代码。使用单个外部阻抗元件来补偿多个电路可以降低主板和封装成本。由于可以使用更简单的补偿电路，所以芯片面积也是保守的。

3. 发明授权

US06600357B1 High voltage level shifter 失效
标题翻译：高电压电平转换器
公开(公告)号：US06600357B1
公开(公告)日：2003-07-29
申请号：US10106944
申请日：2002-03-26
申请人： Masaharu Kirihara
发明人： Masaharu Kirihara
IPC分类号： H03K190185
CPC分类号： H03K3/356113 , H03K17/102
摘要： According to the present invention, a voltage level shifter with smaller size and less latch-up probability is described, in which extra two N-MOS transistors and two P-MOS transistors are added. The extra transistors help node voltages increase or decrease appropriately, and then the size of driving transistors can be small. As a result, the total size of the layout can be smaller. In addition, the voltage increasing or decreasing done by the extra transistors reduce a voltage bouncing which call cause latch-up.
摘要翻译：根据本发明，描述了具有较小尺寸和较小锁存概率的电压电平移位器，其中增加了额外的两个N-MOS晶体管和两个P-MOS晶体管。额外的晶体管有助于节点电压适当增加或减小，然后驱动晶体管的尺寸可以很小。结果，布局的总体尺寸可以更小。另外，由额外的晶体管进行的电压增加或减少会导致电压跳变，从而导致闭锁。

4. 发明授权

US06566932B2 On-chip system with voltage level converting device for preventing leakage current due to voltage level difference 有权
公开(公告)号：US06566932B2
公开(公告)日：2003-05-20
申请号：US10040341
申请日：2001-11-01
申请人： Seong-Ho Yoon
发明人： Seong-Ho Yoon
IPC分类号： H03K190185
CPC分类号： H03K3/356008 , H03K3/356113 , H03K19/00361
摘要： A first module is operated at a first power supply voltage and is blocked from the first power supply voltage in a power-off mode. A second module is operated at a second power supply voltage higher than the first power supply voltage and is supplied with the second voltage even in the power-off mode. An interface circuit is connected between the first and second modules. The interface circuit includes a voltage level converting circuit having an input control circuit. The input control circuit allows the voltage level converting circuit to carry out a normal voltage converting operation in a normal operating mode, while interrupting a leakage current path of the voltage level converting circuit due to an input signal in an unstable status in the power-off mode.

5. 发明授权

US06452419B1 Control circuit having stacked IC logic 失效
标题翻译：具有层叠IC逻辑的控制电路
公开(公告)号：US06452419B1
公开(公告)日：2002-09-17
申请号：US09834142
申请日：2001-04-12
申请人： Kevin Ovens
发明人： Kevin Ovens
IPC分类号： H03K190185
CPC分类号： G05F3/18
摘要： A stacked logic circuit (20) having a serially connected first logic circuit (12) operating off a first voltage differential and providing in series with a second logic circuit (14) operating off a second voltage differential. The second logic circuit being in series with the first logic circuit recycles the current of the first logic circuit. A low impedance shunt circuit (30) is provided in parallel with the first logic circuit (12) and shunts additional current required of and to the second logic circuit (14) from the single voltage source (VCC). A Zener diode (Z1) shunts current from the first logic circuit not required by the second logic circuit via a shunt node (N). The shunt circuit (30) includes a Darlington pair of transistors or a three terminal voltage regulator (42) and only shunts a very small amount of current to ground. The stacked logic circuit of the present invention efficiently uses current drawn by the single voltage source to reduce power consumption.
摘要翻译：堆叠逻辑电路（20）具有串联连接的第一逻辑电路（12），其操作第一电压差并与第二电压差动作的第二逻辑电路（14）串联。与第一逻辑电路串联的第二逻辑电路回收第一逻辑电路的电流。提供与第一逻辑电路（12）并联的低阻分流电路（30），并从第一逻辑电路（VCC）分流所需的额外电流并向第二逻辑电路（14）分流。齐纳二极管（Z1）通过分流节点（N）将来自第一逻辑电路的电流分流到第二逻辑电路不需要的电流。分流电路（30）包括达林顿晶体管对或三端电压调节器（42），并且仅将非常少量的电流分流到地。本发明的堆叠式逻辑电路有效地利用由单电源吸引的电流来降低功耗。

6. 发明授权

US06429684B1 Circuit having dynamic threshold voltage 有权
标题翻译：电路具有动态阈值电压
公开(公告)号：US06429684B1
公开(公告)日：2002-08-06
申请号：US09163267
申请日：1998-09-29
申请人： Theodore W. Houston
发明人： Theodore W. Houston
IPC分类号： H03K190185
CPC分类号： H03K19/01728 , H03K19/0027 , H03K19/01707 , H03K2217/0018
摘要： A body-tied-to-drain transistor having significantly reduced gate delay and being particularly appropriate for large drivers where a series of inverters is used. The basic configuration ties the drain of the transistor to the body of the transistor when the transistor is turned on, and is disconnected when the transistor is turned off.
摘要翻译：一种具有明显减小的栅极延迟并且特别适用于使用一系列逆变器的大型驱动器的体结到漏极晶体管。当晶体管导通时，基本配置将晶体管的漏极连接到晶体管的主体，并且当晶体管截止时，晶体管的漏极断开。

7. 发明授权

US06362652B1 High voltage buffer for submicron CMOS 失效
标题翻译：亚微米CMOS高压缓冲器
公开(公告)号：US06362652B1
公开(公告)日：2002-03-26
申请号：US09467367
申请日：1999-12-20
申请人： Mustafa Ertugrul Oner , Sumer Can
发明人： Mustafa Ertugrul Oner , Sumer Can
IPC分类号： H03K190185
CPC分类号： H03K19/00315
摘要： An input circuit allows input buffers fabricated using submicron CMOS technologies to receive input signals having a voltage swing of 5V. The input circuit uses a cascode transistor to bias the drain of the input transistor so that the VGD of the input transistor does not reach or exceed the gate-oxide breakdown voltage. Outputs of the input buffers have a maximum voltage that is limited by their respective supply voltages.
摘要翻译：输入电路允许使用亚微米CMOS技术制造的输入缓冲器接收具有5V摆幅的输入信号。输入电路使用共源共栅晶体管来偏置输入晶体管的漏极，使得输入晶体管的VGD不达到或超过栅氧化物击穿电压。输入缓冲器的输出具有受其各自电源电压限制的最大电压。

8. 发明授权

US06313664B1 Load capacitance compensated buffer, apparatus and method thereof 有权
标题翻译：负载电容补偿缓冲器，其装置及其方法
公开(公告)号：US06313664B1
公开(公告)日：2001-11-06
申请号：US09528857
申请日：2000-03-20
申请人： Geoffrey B. Hall , Pedro Ovalle , Dzung T. Tran
发明人： Geoffrey B. Hall , Pedro Ovalle , Dzung T. Tran
IPC分类号： H03K190185
CPC分类号： H03K19/00361 , H03K17/167 , H03K19/00384
摘要： A primary driver is activated to drive an output signal in response to an input signal. A reference signal is generated in response to the input signal. The output signal is compared to the reference signal. When the output signal lags the reference signal by a predefined amount an auxiliary driver is activated.
摘要翻译：主驱动器被激活以响应于输入信号来驱动输出信号。响应于输入信号产生参考信号。将输出信号与参考信号进行比较。当输出信号以预定量滞后参考信号时，辅助驱动器被激活。

9. 发明授权

US06307396B1 Low-consumption TTL-CMOS input buffer stage 失效
标题翻译：低功耗TTL-CMOS输入缓冲级
公开(公告)号：US06307396B1
公开(公告)日：2001-10-23
申请号：US09231130
申请日：1998-12-30
申请人： Jacopo Mulatti , Marco Maccarrone , Ignazio Martines , Rino Micheloni
发明人： Jacopo Mulatti , Marco Maccarrone , Ignazio Martines , Rino Micheloni
IPC分类号： H03K190185
CPC分类号： H03K19/0016
摘要： A low-consumption TTL-CMOS input buffer stage includes a chain of inverters cascade connected between an input receiving electric signals at a TTL logic level and an output reproducing electric signals at a CMOS logic level, and powered between a first or supply voltage reference and a second or ground reference. Advantageously, the first inverter in the chain includes a means of selecting the delivery path to the stage according to an activate signal for a low-consumption operation mode. In essence, the first inverter of the buffer has two signal paths: one for normal operation and the other for low consumption operation.
摘要翻译：低功耗TTL-CMOS输入缓冲级包括串联的反相器链，其串联在接收TTL逻辑电平的电信号的输入端和CMOS逻辑电平的输出再现电信号之间，并且在第一或电源电压基准和第二或地面参考。有利地，链中的第一反相器包括根据低功耗操作模式的激活信号选择到载物台的输送路径的装置。实质上，缓冲器的第一个反相器具有两个信号路径：一个用于正常操作，另一个用于低功耗操作。

10. 发明授权

US06268744B1 Three level pre-buffer voltage level shifting circuit and method 有权
标题翻译：三级预缓冲电压电平转换电路及方法
公开(公告)号：US06268744B1
公开(公告)日：2001-07-31
申请号：US09609022
申请日：2000-06-30
申请人： Oleg Drapkin , Grigori Temkine
发明人： Oleg Drapkin , Grigori Temkine
IPC分类号： H03K190185
CPC分类号： H03K19/00315 , H03K19/018585
摘要： A buffer circuit utilizes a single gate oxide pre-buffer voltage level shifting circuit on, for example, an output buffer of an I/O pad, to accommodate different I/O pad supply voltages while maintaining normal operating voltages (degradation levels) across boundaries of single gate oxide devices that form the buffer. The single gate oxide output buffer can operate at several different supply voltages. A pre-buffer voltage level shifting circuit includes a multi-supply voltage level shifting circuit having signal gate oxide devices coupled to produce a pre-buffer output signal to an output buffer. A single gate oxide cross coupled active load is coupled to the multi-supply voltage level shifting circuit and provides suitable drive voltages to at least one of cascaded buffer transistors.
摘要翻译：缓冲电路在例如I / O焊盘的输出缓冲器上使用单栅极氧化物预缓冲器电压电平移位电路，以适应不同的I / O焊盘电源电压，同时保持跨越边界的正常工作电压（劣化电平）的形成缓冲器的单栅极氧化物器件。单栅极氧化物输出缓冲器可以在几种不同的电源电压下工作。预缓冲器电压电平移位电路包括多电源电压移位电路，其具有被耦合以产生到缓冲器输出缓冲器的预缓冲器输出信号的信号栅极氧化器件。单栅极氧化物交叉耦合有源负载耦合到多电源电压电平移位电路，并向级联缓冲晶体管中的至少一个提供合适的驱动电压。

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