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1. 发明授权

US06677612B2 Method for fabricating a simplified CMOS polysilicon thin film transistor and resulting structure 失效
标题翻译：制造简化的CMOS多晶硅薄膜晶体管及其结构的方法
公开(公告)号：US06677612B2
公开(公告)日：2004-01-13
申请号：US09941202
申请日：2001-08-28
申请人： Salman Akram
发明人： Salman Akram
IPC分类号： H01L29786
CPC分类号： H01L27/127 , H01L27/1214 , Y10S257/928
摘要： A method of forming a MOS device using doped and activated n-type and p-type polysilicon layers includes forming a first doped and activated polysilicon area (either n-type and p-type) on a substrate. An isolation material layer is formed abutting the first activated area. A second doped and activated polysilicon area of opposite conductivity type from the first activated area is formed adjacent to the isolation material layer. The second activated opposite area has a height that does not exceed that of the first doped and activated polysilicon layer. Further processing may be effected to complete the MOS device. The method of the present invention eliminates ion implantation and annealing steps used in previously existing methods.
摘要翻译：使用掺杂和活化的n型和p型多晶硅层形成MOS器件的方法包括在衬底上形成第一掺杂和活化的多晶硅区域（n型和p型）。形成邻接第一激活区域的隔离材料层。与隔离材料层相邻地形成有与第一激活区域相反的导电类型的第二掺杂和活化多晶硅区域。第二激活的相对区域的高度不超过第一掺杂和活化多晶硅层的高度。可以进一步处理以完成MOS器件。本发明的方法消除了先前存在的方法中使用的离子注入和退火步骤。

2. 发明授权

US06639244B1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06639244B1
公开(公告)日：2003-10-28
申请号：US09479842
申请日：2000-01-10
申请人： Shunpei Yamazaki , Jun Koyama , Hiroshi Shibata , Takeshi Fukunaga
发明人： Shunpei Yamazaki , Jun Koyama , Hiroshi Shibata , Takeshi Fukunaga
IPC分类号： H01L29786
CPC分类号： H01L27/1255 , G02F1/13454 , G02F1/136213 , H01L27/1214 , H01L27/1277
摘要： A semiconductor device having high TFT characteristics is realized. In a pixel matrix circuit of an AM-LCD, a lower electrode of a storage capacitor is made to include an element in group 15 and a catalytic element used for crystallization, so that its resistance is reduced. Further, a dielectric of the storage capacitor is made thin, so that capacity can be secured without increasing an area for formation of the capacitance. Thus, it becomes possible to secure sufficient storage capacitor even in the AM-LCD having a size of 1 inch or less in diagonal without lowering an opening ratio.
摘要翻译：实现了具有高TFT特性的半导体器件。在AM-LCD的像素矩阵电路中，使存储电容器的下电极包括组15中的元件和用于结晶的催化元件，使得其电阻降低。此外，使存储电容器的电介质变薄，使得可以确保容量而不增加形成电容的面积。因此，即使在尺寸为1英寸以下的AM-LCD中，即使在对角线上也不降低开口率，也可以确保足够的存储电容器。

3. 发明授权

US06624477B1 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06624477B1
公开(公告)日：2003-09-23
申请号：US09122092
申请日：1998-07-24
申请人： Yasuhiko Takemura , Hongyong Zhang , Toshimitsu Konuma
发明人： Yasuhiko Takemura , Hongyong Zhang , Toshimitsu Konuma
IPC分类号： H01L29786
CPC分类号： H01L27/124 , H01L27/1214 , H01L27/127 , H01L29/458 , H01L29/4908 , H01L29/66757 , H01L29/78621
摘要： A monolithic circuit comprises a plurality of thin film transistors. Source and drain regions of the TFT are provided with a metal silicide layer having a relatively low resistivity. Thereby, the effective distance between a gate and a source/drain electrode can be reduced.
摘要翻译：单片电路包括多个薄膜晶体管。 TFT的源极和漏极区域设置有具有较低电阻率的金属硅化物层。由此，可以减小栅极与源极/漏极之间的有效距离。

4. 发明授权

US06590229B1 Semiconductor device and process for production thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06590229B1
公开(公告)日：2003-07-08
申请号：US09487432
申请日：2000-01-19
申请人： Shunpei Yamazaki , Jun Koyama , Hiroshi Shibata , Takeshi Fukunaga
发明人： Shunpei Yamazaki , Jun Koyama , Hiroshi Shibata , Takeshi Fukunaga
IPC分类号： H01L29786
CPC分类号： H01L27/124 , G02F1/13454 , G02F1/136209 , G02F1/136213 , G02F1/136227 , G02F1/136277 , G02F1/1368 , G02F2001/136245 , H01L27/1237 , H01L27/1255 , H01L27/3244 , H01L29/78633 , H01L29/78645
摘要： Disclosed herein is a semiconductor device with high reliability which has TFT of adequate structure arranged according to the circuit performance required. The semiconductor has the driving circuit and the pixel portion on the same substrate. It is characterized in that the storage capacitance is formed between the first electrode formed on the same layer as the light blocking film and the second electrode formed from a semiconductor film of the same composition as the drain region, and the first base insulating film is removed at the part of the storage capacitance so that the second base insulating film is used as the dielectric of the storage capacitance. This structure provides a large storage capacitance in a small area.
摘要翻译：本文公开了一种具有高可靠性的半导体器件，其具有根据所需电路性能布置的适当结构的TFT。半导体在同一衬底上具有驱动电路和像素部分。其特征在于，在与遮光膜形成在同一层上的第一电极和由与漏区相同组成的半导体膜形成的第二电极之间形成存储电容，并且去除第一基底绝缘膜在存储电容的一部分处，使得第二基极绝缘膜用作存储电容的电介质。该结构在小面积上提供了大的存储电容。

5. 发明授权

US06552362B2 Semiconductor device and process for producing the same 有权
公开(公告)号：US06552362B2
公开(公告)日：2003-04-22
申请号：US10087795
申请日：2002-03-05
申请人： Hisashi Ohtani , Etsuko Fujimoto
发明人： Hisashi Ohtani , Etsuko Fujimoto
IPC分类号： H01L29786
CPC分类号： G02F1/136213 , G02F1/136227 , H01L27/1255 , H01L29/78633
摘要： To provide a semiconductor device having a large aperture ratio, in which an auxiliary capacitance of a large capacity is provided in each pixel. Capacitance wiring 102 comprising a tantalum film is formed on a substrate 101 having an insulating surface, and a tantalum oxide film 103 is formed by heat oxidation thereof. An active layer 104 comprising a semiconductor thin film is formed, and an auxiliary capacitance comprising the structure obtained by sandwiching the tantalum oxide film 103 with a part of the active layer 104 and the capacitance wiring 102 is formed. The active layer 104 functions as an active layer of a top-gate TFT.

6. 发明授权

US06515301B2 Structure and fabrication method of flat panel display comprising address line with mending layer 有权
公开(公告)号：US06515301B2
公开(公告)日：2003-02-04
申请号：US09767340
申请日：2001-01-23
申请人： Biing-Seng Wu
发明人： Biing-Seng Wu
IPC分类号： H01L29786
CPC分类号： G02F1/136259 , G02F1/136286 , G02F2001/136272 , G02F2001/13629
摘要： A structure and a fabrication method of a flat panel display comprising address lines with mending layers. A first address line and a first mending layer are formed on a substrate. The first mending layer and the first address line are electrically insulated with each other, and the first mending layer is partitioned into different segments by the first address line. A first insulating layer is formed over the substrate to cover at least the first mending layer and the first address line. A second address line is formed on the first insulating layer over the first mending layer and crossing the first address line. A second insulating layer is formed over the substrate to cover at least the second address line. A second mending layer is formed on the second insulating layer over the second address line and crossing the first address line.

7. 发明授权

US06424016B1 SOI DRAM having P-doped polysilicon gate for a memory pass transistor 失效
标题翻译：具有用于存储器传输晶体管的P掺杂多晶硅栅极的SOI DRAM
公开(公告)号：US06424016B1
公开(公告)日：2002-07-23
申请号：US08862449
申请日：1997-05-23
申请人： Theodore W. Houston
发明人： Theodore W. Houston
IPC分类号： H01L29786
CPC分类号： H01L27/10894 , H01L21/84 , H01L27/0218 , H01L27/10873 , H01L27/10897 , H01L27/1203
摘要： An integrated circuit including a DRAM is disclosed, wherein the DRAM includes a memory array including a plurality of pass gate transistors and a plurality of memory elements. The pass gate transistors include a gate material selected to provide a substantially near mid-gap work function or greater. The DRAM also includes a peripheral area including a plurality of logic transistors. In a preferred embodiment the pass gate transistors are silicon-on-insulator transistors.
摘要翻译：公开了一种包括DRAM的集成电路，其中DRAM包括包括多个通栅晶体管和多个存储元件的存储器阵列。栅极晶体管包括选择用于提供基本上接近中间间隙功函数或更大的栅极材料。 DRAM还包括包括多个逻辑晶体管的外围区域。在优选实施例中，栅极晶体管是绝缘体上硅晶体管。

8. 发明授权

US06414356B1 Circuits and methods for dual-gated transistors 有权
标题翻译：双门控晶体管的电路和方法
公开(公告)号：US06414356B1
公开(公告)日：2002-07-02
申请号：US09605911
申请日：2000-06-28
申请人： Leonard Forbes , Wendell P. Noble
发明人： Leonard Forbes , Wendell P. Noble
IPC分类号： H01L29786
CPC分类号： H01L27/092
摘要： A circuit and method for an improved inverter is provided. The present invention capitalizes on a switched source impedance to prevent subthreshold leakage current at standby in low voltage CMOS circuits. The switched source impedance is provided by dual-gated transistors. The dual gates of the transistors are biased to modify the threshold voltage of the transistors (Vt). This design provides fast switching capability for low power battery operated CMOS circuits and systems. The devices can be used in a variety of applications, digital and analog, wherever a more compact structure with low power consumption and fast response time is needed.
摘要翻译：提供了一种改进的逆变器的电路和方法。本发明利用开关源阻抗来防止低电压CMOS电路中的亚阈值泄漏电流处于待机状态。开关源阻抗由双门控晶体管提供。晶体管的双栅极被偏置以修改晶体管（Vt）的阈值电压。该设计为低功率电池运行的CMOS电路和系统提供了快速的开关能力。这些器件可用于各种应用，数字和模拟，无论需要具有低功耗和快速响应时间的更紧凑的结构。

9. 发明授权

US06700135B2 Active matrix panel 失效
标题翻译：有源矩阵面板
公开(公告)号：US06700135B2
公开(公告)日：2004-03-02
申请号：US10229049
申请日：2002-08-28
申请人： Toshiyuki Misawa , Hiroyuki Oshima
发明人： Toshiyuki Misawa , Hiroyuki Oshima
IPC分类号： H01L29786
CPC分类号： G02F1/13454 , G02F1/133345 , G02F1/136213 , G02F2001/136254 , G09G3/001 , G09G3/002 , G09G3/003 , G09G3/006 , G09G3/2011 , G09G3/3648 , G09G3/3659 , G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2300/0809 , G09G2330/12 , H01L23/4825 , H01L27/124 , H01L29/78618 , H01L2224/48091 , H01L2224/8592 , H01L2924/12032 , H01L2924/13091 , Y10S257/923 , Y10S345/904 , H01L2924/00014 , H01L2924/00
摘要： An active matrix panel including a matrix of driving electrodes couples through thin film transistor switches to a corresponding source line and gate line and at least one of a driver circuit including complementary thin film transistors for driving the source and/or gate lines of the picture elements on the substrate. The thin film transistors of the active matrix have the same cross-sectional structure as the P-type or the N-type thin film transistors forming the driver circuit and are formed during the same patterning process.
摘要翻译：包括驱动电极的矩阵的有源矩阵面板通过薄膜晶体管开关耦合到对应的源极线和栅极线以及包括用于驱动像素的源极和/或栅极线的互补薄膜晶体管的驱动器电路中的至少一个在基板上。有源矩阵的薄膜晶体管具有与构成驱动电路的P型或N型薄膜晶体管相同的横截面结构，并且在相同的图案化工艺期间形成。

10. 发明授权

US06621101B2 Thin-film transistor 有权
公开(公告)号：US06621101B2
公开(公告)日：2003-09-16
申请号：US09936042
申请日：2001-12-12
申请人： Ichio Yudasaka , Mitsutoshi Miyasaka , Piero Migliorato
发明人： Ichio Yudasaka , Mitsutoshi Miyasaka , Piero Migliorato
IPC分类号： H01L29786
CPC分类号： H01L29/78696 , H01L29/78612
摘要： The present invention provides, in a TFT, a channel region facing a gate electrode through a gate insulating film, a source electrode connected to the channel region and a drain region connected to the channel region on the side opposite the source region that are formed in a polycrystal semiconductor film that was patterned in island forms. In the channel region, a recombination center is formed for capturing a small number of carriers (holes) by impurities, such as inert-gas, metals, Group III elements, Group IV elements and Group V elements, introduced to a predetermined region in this channel region, or by defects generated due to the introduction of these impurities. The present invention thus provides an arrangement restraining bipolar transistor type behavior to stabilize saturation current and to provide a TFT that can improve reliability.

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