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1. 发明授权

US08378454B2 Semiconductor device including metal-insulator-metal capacitor arrangement 失效
标题翻译：半导体器件包括金属 - 绝缘体 - 金属电容器布置
公开(公告)号：US08378454B2
公开(公告)日：2013-02-19
申请号：US13173709
申请日：2011-06-30
申请人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
发明人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
IPC分类号： H01L21/02
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.
摘要翻译：半导体器件具有形成在半导体器件上的半导体衬底，多层布线结构以及在多层布线结构中建立的金属 - 绝缘体 - 金属（MIM）电容器布置。 MIM电容器装置包括以规则的间隔彼此平行地排列的第一，第二，第三，第四，第五和第六电极结构。第一，第二，第五和第六电极结构彼此电连接以限定第一电容器，并且第三和第四电极结构彼此电连接以限定第二电容器。

2. 发明授权

US07477538B2 Magnetic random access memory 有权
标题翻译：磁性随机存取存储器
公开(公告)号：US07477538B2
公开(公告)日：2009-01-13
申请号：US10561213
申请日：2004-06-16
申请人： Kenichi Shimura , Kuniko Kikuta
发明人： Kenichi Shimura , Kuniko Kikuta
IPC分类号： G11C11/00
CPC分类号： H01L27/222 , G11C11/16
摘要： A technique for reducing influences of the bias magnetic field developed by yokes used for concentrating the magnetic field on magnetoresistance elements, on MRAM operations. An MRAM is composed of a plurality of magnetoresistance elements having magnetic anisotropy in a first direction; a wiring extended in a second direction different from the first direction, through which a write current flows for writing data into the magnetoresistance elements; and a yoke layer formed of ferromagnetic material, extended along the second direction, and covering at least a portion of a surface of the wiring. The plurality of magnetoresistance elements include a first magnetoresistance element, and a second magnetoresistance element of which the distance from an end of the yoke layer is further than that of the first magnetoresistance element. The first magnetoresistance element has a magnetic anisotropy stronger than that of the second magnetoresistance element.
摘要翻译：在MRAM操作中减小用于将磁场集中在磁阻元件上的磁轭产生的偏磁场的影响的技术。 MRAM由在第一方向上具有磁各向异性的多个磁阻元件构成; 沿与第一方向不同的第二方向延伸的布线，写入电流通过该布线将数据写入磁阻元件; 以及由铁磁材料形成的轭层，沿着第二方向延伸，并覆盖布线表面的至少一部分。多个磁阻元件包括第一磁阻元件和第二磁阻元件，其与轭层的端部的距离比第一磁阻元件的距离更远。第一磁阻元件具有比第二磁阻元件更强的磁各向异性。

3. 发明授权

US07432170B2 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07432170B2
公开(公告)日：2008-10-07
申请号：US11017695
申请日：2004-12-22
申请人： Hiroaki Ohkubo , Ryota Yamamoto , Masayuki Furumiya , Masaharu Sato , Kuniko Kikuta , Makoto Nakayama , Yasutaka Nakashiba
发明人： Hiroaki Ohkubo , Ryota Yamamoto , Masayuki Furumiya , Masaharu Sato , Kuniko Kikuta , Makoto Nakayama , Yasutaka Nakashiba
IPC分类号： H01L21/20
CPC分类号： H01L28/40 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： On a silicon substrate, a first insulation layer, a lower conductive layer, a capacitor-insulator layer, and an upper conductive layer are formed in that order. Then, a first resist pattern is formed, the upper conductive layer is etched to form an upper electrode, and the capacitor-insulator layer is successively etched partway under the same etching condition as that of the upper conductive layer. Next, second resist pattern is formed, the remaining part of the capacitor-insulator layer is etched to form a second insulation layer, and the lower conductive layer is successively etched under the same etching condition as that of the capacitor-insulator layer so as to form a lower electrode and a lower wiring. In this manner, an MiM capacitor element constituted by the upper electrode, a part of the second insulation layer, and the lower electrode can be fabricated.
摘要翻译：在硅衬底上依次形成第一绝缘层，下导电层，电容器 - 绝缘体层和上导电层。然后，形成第一抗蚀剂图案，蚀刻上导电层以形成上电极，并且在与上导电层的蚀刻条件相同的蚀刻条件下，电容器 - 绝缘体层被连续蚀刻。接下来，形成第二抗蚀剂图案，蚀刻电容器 - 绝缘体层的其余部分以形成第二绝缘层，并且在与电容器 - 绝缘体层的蚀刻条件相同的蚀刻条件下，依次蚀刻下导电层，以便形成下电极和下布线。以这种方式，可以制造由上电极，第二绝缘层的一部分和下电极构成的MiM电容器元件。

4. 发明申请

US20060132987A1 Magnetic random access memory 有权
标题翻译：磁性随机存取存储器
公开(公告)号：US20060132987A1
公开(公告)日：2006-06-22
申请号：US10561213
申请日：2004-06-16
申请人： Kenichi Shimura , Kuniko Kikuta
发明人： Kenichi Shimura , Kuniko Kikuta
IPC分类号： G11B5/33
CPC分类号： H01L27/222 , G11C11/16
摘要： The present invention provides a technique for reducing influences of the bias magnetic field developed by yokes used for concentrating the magnetic field on magnetoresistance elements, on MRAM operations. An MRAM according to the present invention is composed of a plurality of magnetoresistance elements having magnetic anisotropy in a first direction; a wiring extended in a second direction different from the first direction, through which a write current is flown for writing data into the magnetoresistance elements; and a yoke layer formed of ferromagnetic material, extended along the second direction, and covering at least a portion of a surface of the wiring. The plurality of magnetoresistance elements include a first magnetoresistance element, and a second magnetoresistance element of which the distance from an end of the yoke layer is further than that of the first magnetoresistance element. The first magnetoresistance element has a magnetic anisotropy stronger than that of the second magnetoresistance element.
摘要翻译：本发明提供了一种用于减小用于磁场集中的磁轭产生的偏磁场对磁阻元件的影响的技术。根据本发明的MRAM由在第一方向上具有磁各向异性的多个磁阻元件构成; 沿与第一方向不同的第二方向延伸的布线，通过该布线写入电流以将数据写入磁阻元件; 以及由铁磁材料形成的轭层，沿着第二方向延伸，并覆盖布线表面的至少一部分。多个磁阻元件包括第一磁阻元件和第二磁阻元件，其与轭层的端部的距离比第一磁阻元件的距离更远。第一磁阻元件具有比第二磁阻元件更强的磁各向异性。

5. 发明申请

US20050218520A1 Semiconductor device and manufacturing method for the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20050218520A1
公开(公告)日：2005-10-06
申请号：US11090112
申请日：2005-03-28
申请人： Kuniko Kikuta , Makoto Nakayama
发明人： Kuniko Kikuta , Makoto Nakayama
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L23/522 , H01L27/01 , H01L27/108
CPC分类号： H01L27/016 , H01L23/5223 , H01L28/55 , H01L2924/0002 , Y10S257/923 , Y10S257/924 , H01L2924/00
摘要： A lower interconnection is provided on a semiconductor substrate. A MIM capacitive element is provided on a first interlayer insulation film in which the lower interconnection is buried, and includes a lower electrode, an upper electrode, and a dielectric film sandwiched therebetween. An upper interconnection is provided on a second interlayer insulation film in which the MIM capacitive element is buried. A contact electrically connects the lower electrode and the upper interconnection. The lower electrode is mainly formed of Al, so that they are lower in electrical resistance than barrier metal, and also low in stress value. Therefore, it becomes possible to widen the area of the lower electrode for electrically connecting the contact while restraining their influences on charge accumulation and close contact between the lower electrode and the insulation film. In addition, since the electrical resistance is lowered, the thickness of the lower electrode can be increased. Accordingly, the MIM capacitive element with a large capacitance can be manufactured with a high yield.
摘要翻译：在半导体衬底上提供较低的互连。 MIM电容元件设置在第一层间绝缘膜上，其中下互连被埋入，并且包括下电极，上电极和夹在其间的电介质膜。在MIM电容元件被埋置的第二层间绝缘膜上设置上互连。触点电连接下电极和上互连。下电极主要由Al形成，使得它们的电阻低于阻挡金属，并且应力值也较低。因此，可以扩大用于电连接触点的下电极的面积，同时抑制它们对电荷累积的影响和下电极与绝缘膜之间的紧密接触。此外，由于电阻降低，所以能够提高下部电极的厚度。因此，可以以高产率制造具有大电容的MIM电容元件。

6. 发明申请

US20050082639A1 Semiconductor device having MIM structure resistor 有权
标题翻译：具有MIM结构电阻器的半导体器件
公开(公告)号：US20050082639A1
公开(公告)日：2005-04-21
申请号：US10964623
申请日：2004-10-15
申请人： Kuniko Kikuta , Makoto Nakayama
发明人： Kuniko Kikuta , Makoto Nakayama
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L27/088 , H01L21/20 , H01L29/00
CPC分类号： H01L27/0688 , H01L27/0629 , H01L28/20 , H01L28/40
摘要： As for the resistor on the semiconductor substrate, it is required to achieve obtaining a metal resistor, which can be formed in the latter half of a preliminary process for manufacturing a semiconductor, in addition to forming a polysilicon resistor, which is formed in the first half of the preliminary process. A capacitor having MIM structure includes a lower electrode, a capacitive insulating film and an upper electrode, all of which are sequentially formed in this sequence. A resistor structure having MIM structure also includes a lower electrode, a capacitive insulating film and a resistor, all of which are sequentially formed in this sequence. In this case, the biasing conditions thereof should be selected so that the resistor structure lower electrode of the MIM structure resistor is not coupled to any electric potential, and is in a floating condition.
摘要翻译：对于半导体衬底上的电阻器，除了形成多晶硅电阻器之外，还需要获得可以在用于制造半导体的预备工艺的后半部分中形成的金属电阻器，该多晶硅电阻器形成在第一一半的初步过程。具有MIM结构的电容器包括下电极，电容绝缘膜和上电极，所有这些按顺序依次形成。具有MIM结构的电阻器结构还包括下电极，电容绝缘膜和电阻器，所有这些按顺序依次形成。在这种情况下，应当选择其偏置条件，使得MIM结构电阻器的电阻器结构下电极不耦合到任何电位，并且处于浮置状态。

7. 发明授权

US06746875B2 Magnetic memory and method of its manufacture 有权
标题翻译：磁记忆及其制造方法
公开(公告)号：US06746875B2
公开(公告)日：2004-06-08
申请号：US10271007
申请日：2002-10-15
申请人： Takeshi Okazawa , Kiyotaka Tsuji , Kuniko Kikuta
发明人： Takeshi Okazawa , Kiyotaka Tsuji , Kuniko Kikuta
IPC分类号： H01L2100
CPC分类号： H01L27/228 , B82Y10/00 , H01L43/12
摘要： A magnetic memory of a present invention is formed as below. The magnetic memory has a TMR film formed on a first conductive film, and a second conductive film with a flat top surface, having the same plane shape as that of the TMR film, formed on the TMR laminated film. A first insulating film having a flat top surface and the same height as the surface of the second conductive film is formed so as to surround the TMR film and the second conductive film. A third conductive film connected electrically to the second conductive film is formed on the first insulating film.
摘要翻译：本发明的磁存储器如下形成。磁性存储器具有形成在第一导电膜上的TMR膜和形成在TMR层叠膜上的具有与TMR膜相同的平面形状的具有平坦顶表面的第二导电膜。形成具有与第二导电膜的表面平坦的顶表面和相同高度的第一绝缘膜，以便包围TMR膜和第二导电膜。与第二导电膜电连接的第三导电膜形成在第一绝缘膜上。

8. 发明授权

US06437394B1 Non-volatile semiconductor memory device with reduced line resistance and method of manufacturing 失效
标题翻译：具有线路电阻降低的非易失性半导体存储器件和制造方法
公开(公告)号：US06437394B1
公开(公告)日：2002-08-20
申请号：US09389168
申请日：1999-09-02
申请人： Masato Kawata , Kuniko Kikuta
发明人： Masato Kawata , Kuniko Kikuta
IPC分类号： H01L29788
CPC分类号： H01L27/105
摘要： To provide a non-volatile semiconductor memory device in which the word line resistance can be decreased in resistance without being accompanied by increase in chip area, and a manufacturing method for the non-volatile semi conductor memory device. In a non-volatile semiconductor memory device having a floating gate (203 of FIG. 2) and a control gate (205 of FIG. 2), a contact groove (407 of FIG. 4a) extending in the direction of a word line (102 of FIG. 1) is provided on an interlayer insulating film (404 of FIG. 4a) formed as an upper layer of the control gate, and an electrically conductive member of, for example, tungsten, is embedded in the contact groove to establish electrical connection between the wiring metal (409 of FIG. 4d) formed as an upper layer of the interlayer insulating film and the control gate with a large contact area.
摘要翻译：提供一种非易失性半导体存储器件，其中可以降低字线电阻而不伴随着芯片面积的增加，以及用于非易失性半导体存储器件的制造方法。在具有浮动栅极（图2的203）和控制栅极（图2的205）的非易失性半导体存储器件中，沿字线方向延伸的接触槽（图4a的407） 102设置在形成为控制栅极的上层的层间绝缘膜（图4a的404）上，并且例如钨的导电构件嵌入在接触槽中以建立形成为层间绝缘膜的上层的布线金属（图4d的409）与接触面积大的控制栅极之间的电连接。

9. 发明申请

US20100148307A1 SEMICONDUCTOR DEVICE INCLUDING METAL-INSULATOR-METAL CAPACITOR ARRANGEMENT 失效
标题翻译：包括金属绝缘体 - 金属电容器布置的半导体器件
公开(公告)号：US20100148307A1
公开(公告)日：2010-06-17
申请号：US12707121
申请日：2010-02-17
申请人： Masayuki FURUMIYA , Kuniko KIKUTA , Ryota YAMAMOTO , Makoto NAKAYAMA
发明人： Masayuki FURUMIYA , Kuniko KIKUTA , Ryota YAMAMOTO , Makoto NAKAYAMA
IPC分类号： H01L29/92
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.
摘要翻译：半导体器件具有形成在半导体器件上的半导体衬底，多层布线结构以及在多层布线结构中建立的金属 - 绝缘体 - 金属（MIM）电容器布置。 MIM电容器装置包括以规则的间隔彼此平行地排列的第一，第二，第三，第四，第五和第六电极结构。第一，第二，第五和第六电极结构彼此电连接以限定第一电容器，并且第三和第四电极结构彼此电连接以限定第二电容器。

10. 发明授权

US07705422B2 Semiconductor device including metal-insulator-metal capacitor arrangement 失效
标题翻译：半导体器件包括金属 - 绝缘体 - 金属电容器布置
公开(公告)号：US07705422B2
公开(公告)日：2010-04-27
申请号：US11247296
申请日：2005-10-12
申请人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
发明人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.
摘要翻译：半导体器件具有形成在半导体器件上的半导体衬底，多层布线结构以及在多层布线结构中建立的金属 - 绝缘体 - 金属（MIM）电容器布置。 MIM电容器装置包括以规则的间隔彼此平行地排列的第一，第二，第三，第四，第五和第六电极结构。第一，第二，第五和第六电极结构彼此电连接以限定第一电容器，并且第三和第四电极结构彼此电连接以限定第二电容器。

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