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1. 发明申请

US20100148307A1 SEMICONDUCTOR DEVICE INCLUDING METAL-INSULATOR-METAL CAPACITOR ARRANGEMENT 失效
标题翻译：包括金属绝缘体 - 金属电容器布置的半导体器件
公开(公告)号：US20100148307A1
公开(公告)日：2010-06-17
申请号：US12707121
申请日：2010-02-17
申请人： Masayuki FURUMIYA , Kuniko KIKUTA , Ryota YAMAMOTO , Makoto NAKAYAMA
发明人： Masayuki FURUMIYA , Kuniko KIKUTA , Ryota YAMAMOTO , Makoto NAKAYAMA
IPC分类号： H01L29/92
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.
摘要翻译：半导体器件具有形成在半导体器件上的半导体衬底，多层布线结构以及在多层布线结构中建立的金属 - 绝缘体 - 金属（MIM）电容器布置。 MIM电容器装置包括以规则的间隔彼此平行地排列的第一，第二，第三，第四，第五和第六电极结构。第一，第二，第五和第六电极结构彼此电连接以限定第一电容器，并且第三和第四电极结构彼此电连接以限定第二电容器。

2. 发明授权

US07705422B2 Semiconductor device including metal-insulator-metal capacitor arrangement 失效
标题翻译：半导体器件包括金属 - 绝缘体 - 金属电容器布置
公开(公告)号：US07705422B2
公开(公告)日：2010-04-27
申请号：US11247296
申请日：2005-10-12
申请人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
发明人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.
摘要翻译：半导体器件具有形成在半导体器件上的半导体衬底，多层布线结构以及在多层布线结构中建立的金属 - 绝缘体 - 金属（MIM）电容器布置。 MIM电容器装置包括以规则的间隔彼此平行地排列的第一，第二，第三，第四，第五和第六电极结构。第一，第二，第五和第六电极结构彼此电连接以限定第一电容器，并且第三和第四电极结构彼此电连接以限定第二电容器。

3. 发明授权

US07239002B2 Integrated circuit device 有权
标题翻译：集成电路器件
公开(公告)号：US07239002B2
公开(公告)日：2007-07-03
申请号：US11038094
申请日：2005-01-21
申请人： Hiroaki Ohkubo , Kuniko Kikuta , Yasutaka Nakashiba , Naoyoshi Kawahara , Hiroshi Murase , Naoki Oda , Tokuhito Sasaki , Nobukazu Ito
发明人： Hiroaki Ohkubo , Kuniko Kikuta , Yasutaka Nakashiba , Naoyoshi Kawahara , Hiroshi Murase , Naoki Oda , Tokuhito Sasaki , Nobukazu Ito
IPC分类号： H01L23/58 , H01L27/06 , H01L23/48 , G01K1/14
CPC分类号： H01L23/34 , G01K7/015 , H01L23/522 , H01L27/0248 , H01L2924/0002 , H01L2924/00
摘要： In a temperature sensor section of a semiconductor integrated circuit device, first vias of tungsten are formed at the topmost layer of a multi-layer wiring layer and pads of titanium are provided on regions of the multi-layer wiring layer which covers the vias. An insulating layer is provided in such a way as to cover the multi-layer wiring layer and the pads, second vias are so formed as to reach the pads. Vanadium oxide is buried in the second vias by reactive sputtering, and a temperature monitor part of vanadium oxide is provided in such a way as to connect the second vias each other. Accordingly, the temperature monitor part is connected between the two wires.
摘要翻译：在半导体集成电路器件的温度传感器部分中，在多层布线层的最上层形成钨的第一通孔，并且在覆盖通孔的多层布线层的区域上设置钛焊盘。以覆盖多层布线层和焊盘的方式设置绝缘层，第二通孔形成为到达焊盘。通过反应性溅射将氧化钒埋在第二通孔中，并且以使得第二通孔彼此连接的方式提供氧化钒的温度监视部分。因此，温度监视器部分连接在两条线之间。

4. 发明申请

US20070148825A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070148825A1
公开(公告)日：2007-06-28
申请号：US11681850
申请日：2007-03-05
申请人： Kuniko KIKUTA , Makoto NAKAYAMA
发明人： Kuniko KIKUTA , Makoto NAKAYAMA
IPC分类号： H01L21/00
CPC分类号： H01L27/016 , H01L23/5223 , H01L28/55 , H01L2924/0002 , Y10S257/923 , Y10S257/924 , H01L2924/00
摘要： A lower interconnection is provided on a semiconductor substrate. A MIM capacitive element is provided on a first interlayer insulation film in which the lower interconnection is buried, and includes a lower electrode, an upper electrode, and a dielectric film sandwiched therebetween. An upper interconnection is provided on a second interlayer insulation film in which the MIM capacitive element is buried. A contact electrically connects the lower electrode and the upper interconnection. The lower electrode is mainly formed of Al, so that they are lower in electrical resistance than barrier metal, and also low in stress value. Therefore, it becomes possible to widen the area of the lower electrode for electrically connecting the contact while restraining their influences on charge accumulation and close contact between the lower electrode and the insulation film. In addition, since the electrical resistance is lowered, the thickness of the lower electrode can be increased. Accordingly, the MIM capacitive element with a large capacitance can be manufactured with a high yield.
摘要翻译：在半导体衬底上提供较低的互连。 MIM电容元件设置在第一层间绝缘膜上，其中下互连被埋入，并且包括下电极，上电极和夹在其间的电介质膜。在MIM电容元件被埋置的第二层间绝缘膜上设置上互连。触点电连接下电极和上互连。下电极主要由Al形成，使得它们的电阻低于阻挡金属，并且应力值也较低。因此，可以扩大用于电连接触点的下电极的面积，同时抑制它们对电荷累积的影响和下电极与绝缘膜之间的紧密接触。此外，由于电阻降低，所以能够提高下部电极的厚度。因此，可以以高产率制造具有大电容的MIM电容元件。

5. 发明申请

US20060237819A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20060237819A1
公开(公告)日：2006-10-26
申请号：US11407323
申请日：2006-04-20
申请人： Kuniko Kikuta , Masayuki Furumiya , Ryota Yamamoto , Makoto Nakayama
发明人： Kuniko Kikuta , Masayuki Furumiya , Ryota Yamamoto , Makoto Nakayama
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a capacitor with an MIM structure, by which the dimensional accuracy of the device is improved, and a stable capacitance value is given. The semiconductor device 100 includes: a semiconductor substrate 102; a capacitor forming region 130 in which an MIM capacitor is formed, which has an insulating interlayer 104 formed on the semiconductor substrate 102, a first electrode 110, and a second electrode 112, and the first electrode 110 and the second electrode 112 are arranged facing each other through the insulating interlayer 104; and a shielding region 132 which includes a plurality of shielding electrodes 114 formed in the outer edge of the capacitor forming region 130 and, at the same time, set at a predetermined potential in the same layer as that of the MIM capacitor on the semiconductor substrate 102, and shields the capacitor forming region 130 from other regions.
摘要翻译：半导体器件包括具有MIM结构的电容器，通过该电容器提高器件的尺寸精度，并给出稳定的电容值。半导体器件100包括：半导体衬底102; 形成有MIM电容器的电容器形成区域130，其具有形成在半导体衬底102上的绝缘中间层104，第一电极110和第二电极112，并且第一电极110和第二电极112面向彼此通过绝缘夹层104; 以及屏蔽区域132，其包括形成在电容器形成区域130的外边缘中的多个屏蔽电极114，并且同时在与半导体衬底上的MIM电容器相同的层中设定预定电位 102，并且将电容器形成区域130与其他区域屏蔽。

6. 发明申请

US20060180871A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060180871A1
公开(公告)日：2006-08-17
申请号：US11338641
申请日：2006-01-25
申请人： Ryota Yamamoto , Kuniko Kikuta
发明人： Ryota Yamamoto , Kuniko Kikuta
IPC分类号： H01L29/76
CPC分类号： H01L21/823878 , H01L21/761 , H01L21/823892 , H01L27/0928
摘要： An N-type deep well is used to protect a circuit from a noise. However, a noise with a high frequency propagates through the N-type deep well, and as a result, the circuit that should be protected malfunctions. To reduce the area of the N-type deep well. For instance, in the present invention, a semiconductor device comprises a semiconductor substrate of a first conductivity type, a digital circuit part and an analog circuit part provided on the semiconductor substrate, a plurality of wells of the first conductivity type formed in either the analog circuit part or the digital circuit part, and a first deep well of a second conductivity type, which is the opposite conductivity type to the first conductivity type, isolating some of the plurality of wells from the semiconductor substrate.
摘要翻译： N型深井用于保护电路免受噪音。然而，高频噪声通过N型深井传播，因此应保护的电路发生故障。减少N型深井的面积。例如，在本发明中，半导体器件包括第一导电类型的半导体衬底，设置在半导体衬底上的数字电路部分和模拟电路部分，第一导电类型的多个阱形成于模拟电路部分或数字电路部分，以及与第一导电类型相反的导电类型的第二导电类型的第一深阱，从半导体衬底隔离多个阱中的一些。

7. 发明申请

US20050173775A1 Integrated circuit device and fabrication method therefor 有权
标题翻译：集成电路器件及其制造方法
公开(公告)号：US20050173775A1
公开(公告)日：2005-08-11
申请号：US11052215
申请日：2005-02-08
申请人： Naoyoshi Kawahara , Hiroshi Murase , Hiroaki Ohkubo , Kuniko Kikuta , Yasutaka Nakashiba , Naoki Oda , Tokuhito Sasaki , Nobukazu Ito
发明人： Naoyoshi Kawahara , Hiroshi Murase , Hiroaki Ohkubo , Kuniko Kikuta , Yasutaka Nakashiba , Naoki Oda , Tokuhito Sasaki , Nobukazu Ito
IPC分类号： H01L21/768 , H01C7/10 , H01L21/822 , H01L23/58 , H01L27/04 , H01L27/06 , H01L27/16 , H01L31/058
CPC分类号： H01C7/1013 , H01L27/16 , H01L2924/0002 , H01L2924/00
摘要： In a temperature sensor section of a semiconductor integrated circuit device, wires of the topmost wiring layer of a multi-layer wiring structure are formed. A sheet-like temperature monitor element of vanadium oxide is provided between two of the wires in such a way as to cover the two wires. Accordingly, the temperature monitor element is connected between the two wires of an underlying wiring layer of the multi-layer wiring structure through two vias and the two wires of the topmost wiring layer.
摘要翻译：在半导体集成电路器件的温度传感器部分中，形成多层布线结构的最上层布线层的布线。在两条电线之间设置氧化钒的片状温度监视元件，以覆盖两条电线。因此，温度监视元件通过两个通孔和最上面布线层的两条导线连接在多层布线结构的底层布线层的两条导线之间。

8. 发明授权

US6114244A Method for manufacturing a semiconductor device having fine contact hole with high aspect ratio 失效
标题翻译：制造具有高纵横比的细小接触孔的半导体器件的方法
公开(公告)号：US6114244A
公开(公告)日：2000-09-05
申请号：US910020
申请日：1997-08-12
申请人： Kazuyuki Hirose , Kuniko Kikuta
发明人： Kazuyuki Hirose , Kuniko Kikuta
IPC分类号： H01L23/485 , H01L23/532 , H01L29/45 , H01L21/44
CPC分类号： H01L23/485 , H01L23/53223 , H01L29/456 , H01L2924/0002
摘要： A semiconductor device includes at least one hole formed on a semiconductor substrate. A barrier method is formed on at least one portion in contact with the semiconductor substrate in the hole. A metal interconnection is constituted by two layers including a first Al-containing metal film formed on the barrier metal, and a second Al-containing metal film formed on the first Al-containing metal film and having a melting point lower than the melting point of the first Al-containing metal film.
摘要翻译：半导体器件包括形成在半导体衬底上的至少一个孔。在与孔中的半导体衬底接触的至少一个部分上形成屏障方法。金属互连由两层构成，包括形成在阻挡金属上的第一含Al金属膜和形成在第一含Al金属膜上的第二含Al金属膜，其熔点低于第一含Al金属膜。

9. 发明授权

US5691571A Semiconductor device having fine contact hole with high aspect ratio 失效
标题翻译：具有高纵横比的细小接触孔的半导体装置
公开(公告)号：US5691571A
公开(公告)日：1997-11-25
申请号：US578318
申请日：1995-12-26
申请人： Kazuyuki Hirose , Kuniko Kikuta
发明人： Kazuyuki Hirose , Kuniko Kikuta
IPC分类号： H01L23/485 , H01L23/532 , H01L29/45 , H01L23/48 , H01L29/46 , H01L29/52 , H01L29/64
CPC分类号： H01L23/485 , H01L23/53223 , H01L29/456 , H01L2924/0002
摘要： A semiconductor device includes at least one hole formed on a semiconductor substrate. A barrier metal is formed on at least one portion in contact with the semiconductor substrate in the hole. A metal interconnection is constituted by two layers including a first Al-containing metal film formed on the barrier metal, and a second Al-containing metal film formed on the first Al-containing metal film and having a melting point lower than the melting point of the first Al-containing metal film.
摘要翻译：半导体器件包括形成在半导体衬底上的至少一个孔。在与孔中的半导体衬底接触的至少一个部分上形成阻挡金属。金属互连由两层构成，包括形成在阻挡金属上的第一含Al金属膜和形成在第一含Al金属膜上的第二含Al金属膜，其熔点低于第一含Al金属膜。

10. 发明授权

US4983534A Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US4983534A
公开(公告)日：1991-01-08
申请号：US555678
申请日：1990-07-20
申请人： Kuniko Kikuta
发明人： Kuniko Kikuta
IPC分类号： H01L21/331 , H01L29/267 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/267 , H01L29/7371 , Y10S148/01 , Y10S148/011 , Y10S148/072 , Y10S148/084 , Y10S438/933
摘要： A method of manufacturing a semiconductor device includes forming a base region and a collector region on an Si substrate, forming, on the base region, an emitter region of a semiconductor material having an energy gap larger than that of Si, forming an Si film on the emitter region, ion-implanting an element into a surface portion of the emitter region or at the interface of the emitter region and the Si film and a periphery portion of the interface, and simultaneously forming electrodes on the base and collector regions and on the Si film. A heterojunction bipolar transistor manufactured by the above method is also disclosed.
摘要翻译：一种制造半导体器件的方法包括在Si衬底上形成基极区域和集电极区域，在基极区域上形成具有比Si间隙大的能隙的半导体材料的发射极区域，形成Si膜发射极区域，将元素离子注入到发射极区域的表面部分中或者在发射极区域和Si膜的界面处以及界面的周边部分之间，并且同时在基极和集电极区域上形成电极硅胶片。还公开了通过上述方法制造的异质结双极晶体管。

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