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1. 发明授权

US5995349A Protection device for solid state switched power electronics 失效
标题翻译：固态开关电源的保护装置
公开(公告)号：US5995349A
公开(公告)日：1999-11-30
申请号：US944513
申请日：1997-10-06
申请人： Victor A. K. Temple
发明人： Victor A. K. Temple
IPC分类号： H03K17/0814 , H02H3/00
CPC分类号： H03K17/0814
摘要： A circuit and method of protecting the antiparallel diodes of a power bridge circuit from stress induced failures caused by the fast operation of the power switches. An auxiliary power switch is provided in parallel to the main power switch which is operable during the reverse recovery of the antiparallel diode, after which the main power switch carries the bulk of the switch current.
摘要翻译：一种保护电力电路电路的反并联二极管的电路和方法，不受电源开关快速运行引起的应力引起的故障。辅助电源开关与主电源开关并联设置，该主电源开关在反并联二极管的反向恢复期间可操作，之后主电源开关承载大部分开关电流。

2. 发明授权

US5594261A Device for isolating parallel sub-elements with reverse conducting diode regions 失效
标题翻译：用反向导通二极管区域隔离并联子元件的装置
公开(公告)号：US5594261A
公开(公告)日：1997-01-14
申请号：US223425
申请日：1994-04-05
申请人： Victor A. K. Temple
发明人： Victor A. K. Temple
IPC分类号： H01L29/74 , H01L29/749 , H01L29/10
CPC分类号： H01L29/749 , H01L29/7416
摘要： A monolithic semiconductor power switching device and a method of separating plural thyristor based active areas therein includes reverse conducting diode regions between the active areas. The reverse conducting diode regions influence current flow at the edges of the operable ones of the active areas so that current from an operable one of the active areas does not flow into and turn on an inoperable one of the active areas. The reverse conducting diode regions have a width so that substantially all of the carriers of the current from an operable one of the active areas recombine before reaching an adjacent active area.
摘要翻译：单片半导体功率开关器件和分离其中的多个基于晶闸管的有源区的方法包括在有源区之间的反向导通二极管区。反向导电二极管区域影响有源区域中的可操作的区域的边缘处的电流，使得来自可操作的有源区域中的电流不流入并导通不可操作的有源区域中的一个。反向导通二极管区域具有宽度，使得来自可操作的一个有源区域的电流的基本上所有载流子在到达相邻的有源区域之前复合。

3. 发明授权

US5497013A Semi-conductor chip having interdigitated gate runners with gate bonding pads 失效
标题翻译：半导体芯片具有带栅极焊盘的交错栅极流道
公开(公告)号：US5497013A
公开(公告)日：1996-03-05
申请号：US276464
申请日：1994-07-18
申请人： Victor A. K. Temple
发明人： Victor A. K. Temple
IPC分类号： H01L23/051 , H01L23/482 , H01L29/423 , H01L29/78 , H01L23/48 , H01L29/44 , H01L29/52 , H01L29/60
CPC分类号： H01L29/7802 , H01L23/051 , H01L23/4824 , H01L24/06 , H01L29/4238 , H01L2924/01079 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/3011
摘要： A semiconductor chip having a cellular topography and a method of packaging a cellular semiconductor chip, includes plural interdigitated metal gate runners that overlie and contact selected gate electrodes on the chip surface, each of the gate runners having an integral widened area to enable a package-carried gate electrode contact foil to be bonded thereto. The gate runner widened areas are relatively small and have little impact on chip active area. The plural gate runners have portions that underlie a package-carried power electrode contact foil and that are separated therefrom by a nonbondable, insulating layer. The gate runners may be deposited on the chip in the same step and from the name material am the power electrode. The portion of the power electrode on the chip surface that underlies the package-carried gate electrode contact foil is separated therefrom and available for use as active area of the chip, Package lid-to-chip alignment tolerances may be relaxed as they are not dictated by alignment of the lid-carried gate contact foil with the gate electrode on the chip.
摘要翻译：具有细胞形貌的半导体芯片和封装蜂窝半导体芯片的方法包括多个叉指的金属栅极流道，其覆盖并接触芯片表面上的选定的栅电极，每个栅极流道具有整体加宽的区域，携带的栅电极接触箔与其键合。闸口加宽区域相对较小，对芯片活动区域影响不大。多个栅极流道具有位于封装携带的电极接触箔的下方的部分，并且通过非粘结的绝缘层与其分离。栅极流道可以以相同的步骤和来自电源电极的名称材料沉积在芯片上。芯片表面上位于封装载体栅极电极接触箔下方的功率电极部分与芯片分离，可用作芯片的有源区域，封装盖到芯片对准公差可能会因为未被规定而放宽通过将盖带电的栅极接触箔与芯片上的栅电极对准。

4. 发明授权

US5260590A Field effect transistor controlled thyristor having improved turn-on characteristics 失效
标题翻译：场效应晶体管控制晶闸管具有提高的导通特性
公开(公告)号：US5260590A
公开(公告)日：1993-11-09
申请号：US811999
申请日：1991-12-23
申请人： Victor A. K. Temple
发明人： Victor A. K. Temple
IPC分类号： H01L29/74 , H01L29/745 , H01L29/749 , H01L29/78
CPC分类号： H01L29/7455 , H01L29/749
摘要： A composite thyristor comprising a plurality of parallel connected identical thyristor cells, each of the cells including a turn-on field effect transistor (FET) and a turn-off FET. The gate electrodes of all the FETs form a grid-like pattern on a surface of the semiconductor substrate of the device. The pattern includes strips which intersect at corners. Turn-off FETs are formed along the boundary of the grid and beneath it, and turn-on FETs are disposed beneath the corners.
摘要翻译：一种复合晶闸管，包括多个并联的相同晶闸管单元，每个单元包括导通场效应晶体管（FET）和截止FET。所有FET的栅电极在器件的半导体衬底的表面上形成格栅状图案。该图案包括在角落处相交的条纹。截止FET沿着栅格的边界及其下方形成，并且导通FET设置在角落的下方。

5. 发明授权

US5105536A Method of packaging a semiconductor chip in a low inductance package 失效
标题翻译：在低电感封装中封装半导体芯片的方法
公开(公告)号：US5105536A
公开(公告)日：1992-04-21
申请号：US690409
申请日：1991-04-23
申请人： Constantine A. Neugebauer , Robert J. Satriano , James F. Burgess , Homer H. Glascock, II , Victor A. K. Temple , Donald L. Watrous
发明人： Constantine A. Neugebauer , Robert J. Satriano , James F. Burgess , Homer H. Glascock, II , Victor A. K. Temple , Donald L. Watrous
IPC分类号： H01L23/495
CPC分类号： H01L24/40 , H01L23/49562 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01079 , H01L2924/01082 , H01L2924/12042 , H01L2924/1301 , H01L2924/14 , H01L2924/15787 , Y10T29/4913 , Y10T29/49169
摘要： A hermetic, high current package for a semiconductor device includes wide flat leads which are bonded to the contact pads of the device and formed to extend through apertures in an insulating lid. The lid is sealed to a base and the apertures around the leads are sealed with solder to provide the hermetic package. This package limits lateral current flow in the contact pads of the semiconductor device to relatively low levels which ensure the integrity of the contact pads.
摘要翻译：用于半导体器件的密封的高电流封装包括宽扁平引线，其结合到器件的接触焊盘并且形成为延伸穿过绝缘盖中的孔。盖被密封到基座上，并且用焊料密封引线周围的孔以提供气密封装。该封装将半导体器件的接触焊盘中的横向电流流动限制到相对较低的水平，这确保了接触焊盘的完整性。

6. 发明授权

US5103290A Hermetic package having a lead extending through an aperture in the package lid and packaged semiconductor chip 失效
标题翻译：密封包装具有延伸穿过封装盖中的孔和封装的半导体芯片的引线
公开(公告)号：US5103290A
公开(公告)日：1992-04-07
申请号：US367525
申请日：1989-06-16
申请人： Victor A. K. Temple , Donald L. Watrous , Constantine A. Neugebauer , James F. Burgess , Homer H. Glascock, II
发明人： Victor A. K. Temple , Donald L. Watrous , Constantine A. Neugebauer , James F. Burgess , Homer H. Glascock, II
IPC分类号： H01L23/04 , H01L23/049 , H01L23/485
CPC分类号： H01L24/10 , H01L23/04 , H01L23/049 , H01L24/13 , H01L2224/13 , H01L2224/13099 , H01L2224/45144 , H01L2924/01004 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/1301 , H01L2924/1306 , H01L2924/14 , H01L2924/15787 , H01L2924/30107
摘要： A hermetically sealed package for a semiconductor device includes a lid through which the leads of the device extend vertically away from the chip through an aperture in the lid which is hermetically sealed by the external terminal or electrode. The package is compact, lightweight and free of magnetic materials.
摘要翻译：用于半导体器件的密封封装包括一个盖子，该器件的引线通过该盖子通过盖子的孔垂直地远离芯片延伸，盖子上的孔被外部端子或电极气密地密封。该包装体积小巧，重量轻，无磁性材料。

7. 发明授权

US5082795A Method of fabricating a field effect semiconductor device having a self-aligned structure 失效
标题翻译：具有自对准结构的场效应半导体器件的制造方法
公开(公告)号：US5082795A
公开(公告)日：1992-01-21
申请号：US267757
申请日：1988-11-01
申请人： Victor A. K. Temple
发明人： Victor A. K. Temple
IPC分类号： H01L21/336 , H01L29/06 , H01L29/423 , H01L29/739 , H01L29/745 , H01L29/772 , H01L29/78 , H01L29/872
CPC分类号： H01L29/66666 , H01L29/0696 , H01L29/7391 , H01L29/7397 , H01L29/7455 , H01L29/7722 , H01L29/7813 , H01L29/872 , H01L29/4232 , H01L29/42368 , H01L29/4238
摘要： A self aligned method of fabricating a vertical channel insulated gate semiconductor device comprises providing a first layer of one type conductivity atop a partially processed wafer. A first protective layer is disposed over the first layer and a window is opened therethrough. A first region can be established through the first window and in the first layer. A trench is established through the first window, and extending entirely through the first region and first layer, into the partially processed wafer. An insulated gate is established in the trench to control the drift region electric field under reverse bias operation.
摘要翻译：制造垂直沟道绝缘栅半导体器件的自对准方法包括在部分处理的晶片的顶部提供一种导电类型的第一层。第一保护层设置在第一层上并且通过其中打开窗口。可以通过第一窗口和第一层建立第一区域。通过第一窗口建立沟槽，并且完全延伸穿过第一区域和第一层，进入部分处理的晶片。在沟槽中建立绝缘栅极，以在反向偏压操作下控制漂移区电场。

8. 发明授权

US4904609A Method of making symmetrical blocking high voltage breakdown semiconductor device 失效
标题翻译：制造对称阻挡高压击穿半导体器件的方法
公开(公告)号：US4904609A
公开(公告)日：1990-02-27
申请号：US190903
申请日：1988-05-06
申请人： Victor A. K. Temple
发明人： Victor A. K. Temple
IPC分类号： H01L21/76 , H01L21/78 , H01L23/31 , H01L29/06 , H01L29/78
CPC分类号： H01L23/3178 , H01L21/78 , H01L29/0619 , H01L2924/0002 , Y10S148/126
摘要： A symmetrical blocking high breakdown voltage semiconductor device in which the lower junction termination is brought to the upper surface is fabricated by diffusing first and second regions of a first conductivity type into an upper surface of an epitaxial layer of a second conductivity type disposed on a substrate, and forming a groove having sloped sidewalls in the upper surface such that the groove extends through the second diffused region, the epitaxial layer and into the substrate. A thin layer of impurities of the first conductivity type is implanted into the sidewalls, and the impurities are electrically activated to form a low resistivity path that connects the substrate to the second diffused region. Subsequently, the semiconductor device may be separated from the wafer by cutting the wafer at the groove. The manufacturing process enables substantially complete fabrication of a plurality of devices while still in wafer form, thereby avoiding the inconvenience of processing individual dice.

9. 发明授权

US4821095A Insulated gate semiconductor device with extra short grid and method of fabrication 失效
标题翻译：具有超短栅格和制造方法的绝缘栅半导体器件
公开(公告)号：US4821095A
公开(公告)日：1989-04-11
申请号：US25036
申请日：1987-03-12
申请人： Victor A. K. Temple
发明人： Victor A. K. Temple
IPC分类号： H01L29/08 , H01L29/10 , H01L29/739 , H01L29/745 , H01L29/78
CPC分类号： H01L29/0834 , H01L29/1095 , H01L29/7395 , H01L29/745 , H01L29/7455
摘要： An improved insulated gate semiconductor device is provided with an extra short grid region of one type conductivity disposed proximate the PN junction between the first and second regions of the device. The extra short grid region provides an alternate path for one type conductivity carriers to inhibit forward biasing of the PN junction between the first and second electrodes. In addition, the grid allows opposite type conductivity carriers to flow therethrough. A portion of the grid is spaced and separated from the first region. Accordingly, a device fabricated in accordance with the present invention is less susceptible to latching and exhibits a higher voltage latching threshold.
摘要翻译：改进的绝缘栅半导体器件具有设置在器件的第一和第二区域附近的PN结附近的一种类型导电体的额外的短格栅区域。额外的短栅格区域为一种类型的导电载流子提供了一个替代路径，以阻止PN结在第一和第二电极之间的正向偏置。此外，电网允许相反的导电载流子流过其中。网格的一部分与第一区域间隔开并分离。因此，根据本发明制造的器件不易于锁存，并且具有较高的电压锁存阈值。

10. 发明授权

US4739387A Amplifying gate thyristor having high gate sensitivity and high dv/dt rating 失效
标题翻译：具有高栅极灵敏度和高dv / dt额定值的放大栅极晶闸管
公开(公告)号：US4739387A
公开(公告)日：1988-04-19
申请号：US497339
申请日：1983-05-23
申请人： Victor A. K. Temple , Armand P. Ferro
发明人： Victor A. K. Temple , Armand P. Ferro
IPC分类号： H01L29/06 , H01L29/74
CPC分类号： H01L29/0646 , H01L29/0649 , H01L29/7428
摘要： A thyristor is provided having high gate sensitivity in combination with high dv/dt ratings. An amplifying gate structure is utilized having a pilot thyristor region including a first portion characterized by a first extent and at least one projection of said first portion extending therefrom and having a lateral extent greater than the extent of said first portion; and means substantially isolating said pilot thyristor region from the remainder of the device which means surround said first portion and the sides of said projection.
摘要翻译：提供了具有高栅极灵敏度和高dv / dt额定值的晶闸管。使用具有先导晶闸管区域的放大栅极结构，该导频晶闸管区域包括第一部分，第一部分的特征在于第一范围和所述第一部分的至少一个突出部，其从其延伸并具有大于所述第一部分的范围的横向范围; 并且意味着基本上将所述引导可控硅区域与装置的其余部分隔离，所述剩余部分意味着围绕所述突起的所述第一部分和侧面。

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