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1. 发明授权

US06376345B1 Process for manufacturing semiconductor integrated circuit device 有权
公开(公告)号：US06376345B1
公开(公告)日：2002-04-23
申请号：US09356707
申请日：1999-07-20
申请人： Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
发明人： Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
IPC分类号： H01L2138
CPC分类号： H01L21/0209 , G09G5/399 , H01L21/02074 , H01L21/3212 , H01L21/76838 , H01L21/7684 , Y10S438/906
摘要： In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

2. 发明授权

US06207540B1 Method for manufacturing high performance MOSFET device with raised source and drain 失效
标题翻译：用于制造具有升高的源极和漏极的高性能MOSFET器件的方法
公开(公告)号：US06207540B1
公开(公告)日：2001-03-27
申请号：US09379940
申请日：1999-08-24
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma , Jack A. Mandelman
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma , Jack A. Mandelman
IPC分类号： H01L2138
CPC分类号： H01L29/66613 , H01L21/2255 , H01L29/66621 , H01L29/7834
摘要： A MOSFET device and a method of manufacturing the device. The device has a trench formed in a silicon substrate. The channel of the device is at the bottom of the trench. Diffusion layers are formed adjacent to opposite sides of the trench. Each diffusion layer is connected to the edge of the device channel by extending the diffusion layer along the side wall of the trench and under a portion of the trench.
摘要翻译：一种MOSFET器件及其制造方法。该器件具有形成在硅衬底中的沟槽。设备的通道位于沟槽的底部。扩散层邻近沟槽的相对侧形成。通过沿着沟槽的侧壁和沟槽的一部分延伸扩散层，将每个扩散层连接到器件沟道的边缘。

3. 发明授权

US06436800B1 Method for fabricating a non-volatile memory with a shallow junction 有权
标题翻译：用于制造具有浅结的非易失性存储器的方法
公开(公告)号：US06436800B1
公开(公告)日：2002-08-20
申请号：US09990393
申请日：2001-11-20
申请人： Tung-Cheng Kuo , Shou-Wei Hung , Chien-Hung Liu , Shyi-Shuh Pan
发明人： Tung-Cheng Kuo , Shou-Wei Hung , Chien-Hung Liu , Shyi-Shuh Pan
IPC分类号： H01L2138
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： A fabrication method for a nonvolatile memory with a shallow junction is described. A gate structure, comprising an electron-trapping layer and a conductive layer, is formed on a substrate. A doped spacer is formed on the sidewall of the gate structure. Buried bit lines are further formed in the substrate beside the gate structure. Thereafter, thermal process is conducted to diffuse the dopants from the doped spacer into the substrate adjacent to the buried bit lines.
摘要翻译：描述了一种具有浅结的非易失性存储器的制造方法。在基板上形成包括电子捕获层和导电层的栅极结构。掺杂间隔物形成在栅极结构的侧壁上。在栅极结构旁边的衬底中进一步形成掩埋位线。此后，进行热处理以将掺杂的掺杂剂从埋入的位线扩散到衬底中。

4. 发明授权

US06303477B1 Removal of organic anti-reflection coatings in integrated circuits 有权
标题翻译：去除集成电路中的有机防反射涂层
公开(公告)号：US06303477B1
公开(公告)日：2001-10-16
申请号：US09826489
申请日：2001-04-04
申请人： Serguei Ianovitch
发明人： Serguei Ianovitch
IPC分类号： H01L2138
CPC分类号： H01L21/31144 , G03F7/091 , G03F7/40 , H01L21/0276 , H01L21/31138
摘要： A method for manufacturing an integrated circuit structure is provided having a semiconductor substrate and depositing a layer to be patterned on the semiconductor substrate. An organic anti-reflection coating is deposited on the layer to be patterned and then an organic photoresist on the anti-reflection coating. The photoresist is patterned and developed to form an opening having side walls and to expose a portion of the anti-reflection coating. The photoresist and the exposed portion of the anti-reflection coating adsorb non-active molecules. A unidirectional electron-ion bombardment causes desorption of non-active molecules that gives access of active molecules to the exposed surface of the anti-reflection coating. Bombardment also causes decomposition of non-active molecules on the exposed surfaces, which produces active atoms. Both processes provide unidirectional removal of the anti-reflection coating without attacking the photoresist side walls and underlying layers.
摘要翻译：提供一种用于制造集成电路结构的方法，其具有半导体衬底并在半导体衬底上沉积待图案化的层。在待图案化的层上沉积有机抗反射涂层，然后在抗反射涂层上沉积有机光致抗蚀剂。对光致抗蚀剂进行图案化和显影以形成具有侧壁的开口并暴露一部分抗反射涂层。抗蚀剂和抗反射涂层的曝光部分吸附非活性分子。单向电子轰击引起非活性分子的解吸，使活性分子进入抗反射涂层的暴露表面。轰击也导致暴露表面上的非活性分子的分解，产生活性原子。两种方法提供单向去除防反射涂层，而不会侵蚀光刻胶侧壁和下层。

5. 发明授权

US06809016B1 Diffusion stop implants to suppress as punch-through in SiGe 有权
标题翻译：扩散停止植入物以抑制SiGe的穿透
公开(公告)号：US06809016B1
公开(公告)日：2004-10-26
申请号：US10379794
申请日：2003-03-06
申请人： Qi Xiang
发明人： Qi Xiang
IPC分类号： H01L2138
CPC分类号： H01L29/7833 , H01L21/26513 , H01L21/26586 , H01L29/1054 , Y10S438/922 , Y10S438/923 , Y10S438/933
摘要： Diffusion of As in SiGe of MOS transistors based on Si/SiGe is prevented by ion implanting boron. Embodiments include forming As source/drain extension implants in a strained Si/SiGe substrate, ion implanting boron at between the As source/drain extension implant junctions and subsequently annealing to activate the As source/drain extensions, thereby preventing distortion of the originally formed junction.
摘要翻译：通过离子注入硼可以防止基于Si / SiGe的MOS晶体管的SiGe中的As扩散。实施例包括在应变Si / SiGe衬底中形成As源极/漏极延伸植入物，在As源极/漏极延伸注入接合点之间离子注入硼，随后退火以激活As源极/漏极延伸部分，从而防止原始形成的结的失真。

6. 发明授权

US06339015B1 Method of fabricating a non-volatile semiconductor device 失效
标题翻译：制造非易失性半导体器件的方法
公开(公告)号：US06339015B1
公开(公告)日：2002-01-15
申请号：US09574410
申请日：2000-05-18
申请人： John A. Bracchitta , James S. Nakos
发明人： John A. Bracchitta , James S. Nakos
IPC分类号： H01L2138
CPC分类号： H01L29/7883 , H01L21/28273 , H01L29/42336
摘要： A non-volatile random access memory (NVRAM) cell and methods of forming thereof are disclosed. The NVRAM cell includes a substrate having source and drain regions. A spike having a sharp tip extends in the source region. Instead of a single spike, two adjacent spikes are included in the source. Alternatively, in addition to the single spike in the source, two adjacent spikes are included in the drain. The two adjacent spikes have one tip pointing toward the floating gate and two tips pointing away from the floating gate. The spikes provide high electric field to facilitate charge movement between the floating gate and the source region. A tunnel oxide layer separates the floating gate from the substrate. A gate oxide and a control gate are also formed over the floating gate. The single spike is formed by preferentially etching the substrate along a selected crystal plane through an opening formed in a mask that covers the substrate. The two adjacent spikes are formed by first forming spacers on sidewalls of the opening to reduce a width thereof; filling the reduced opening with a mask plug; removing the sidewalls; and etching the substrate.
摘要翻译：公开了非易失性随机存取存储器（NVRAM）单元及其形成方法。 NVRAM单元包括具有源区和漏区的衬底。具有尖锐尖端的尖端在源区域中延伸。代替单个尖峰，源中包含两个相邻的尖峰。或者，除了源中的单个尖峰之外，两个相邻的尖峰包括在排水管中。两个相邻的尖峰具有指向浮动门的一个尖端和指向远离浮动门的两个尖端。尖峰提供高电场以促进浮动栅极和源极区域之间的电荷移动。隧道氧化层将浮栅与衬底分开。栅极氧化物和控制栅极也形成在浮动栅极上。通过优选地通过形成在覆盖衬底的掩模中形成的开口沿着选定的晶面蚀刻衬底而形成单个尖峰。两个相邻的钉是通过在开口的侧壁上首先形成间隔物而形成的，以减小其宽度; 用面罩塞填充减小的开口; 去除侧壁; 并蚀刻衬底。

7. 发明授权

US06365493B1 Method for antimony and boron doping of spherical semiconductors 失效
标题翻译：锑和硼掺杂球形半导体的方法
公开(公告)号：US06365493B1
公开(公告)日：2002-04-02
申请号：US09490650
申请日：2000-01-24
申请人： Evangellos Vekris , Nainesh J. Patel , Murali Hanabe
发明人： Evangellos Vekris , Nainesh J. Patel , Murali Hanabe
IPC分类号： H01L2138
CPC分类号： H01L29/0657 , H01L21/2255 , H01L21/228
摘要： A method for doping crystals is disclosed. The method includes a receiver for receiving semiconductor spheres and doping powder. The semiconductor spheres and dopant powder are then directed to a chamber defined within an enclosure. The chamber maintains a heated, inert atmosphere with which to diffuse the dopant to the semiconductor spheres.
摘要翻译：公开了掺杂晶体的方法。该方法包括用于接收半导体球和掺杂粉末的接收器。然后将半导体球和掺杂剂粉末引导到限定在外壳内的室。该室保持加热的惰性气氛，以使掺杂剂扩散到半导体球体。

8. 发明授权

US06214708B1 Method and apparatus for diffusing zinc into groups III-V compound semiconductor crystals 有权
标题翻译：将锌扩散到III-V族化合物半导体晶体中的方法和装置
公开(公告)号：US06214708B1
公开(公告)日：2001-04-10
申请号：US09363397
申请日：1999-07-29
申请人： Yasuhiro Iguchi , Sosuke Sowa
发明人： Yasuhiro Iguchi , Sosuke Sowa
IPC分类号： H01L2138
CPC分类号： H01L21/67109 , H01L21/2233
摘要： An LPE (Liquid Phase Epitaxy) apparatus is diverted to a Zn-diffusion apparatus for diffusing Zn into III-V group compound semiconductor. The Zn-diffusion apparatus comprises a base plank extending in a direction, having a wafer-storing cavity for storing an object wafer and an exhaustion hole for exhaling gases, a slider having a frame and a cap plate for attaching to or detaching from the frame, the frame having serially aligning M rooms with an open bottom and a rack being separated from each other by (M−1) partition walls, a manipulating bar for sliding the slider upon the base plank forward or backward in the direction, a tube for enclosing the base plank and the slider and for being capable of being made vacuous, a heater surrounding the tube for heating the slider, each rack of the rooms being allocated with a Zn-diffusion material and a V element material (or a non-doped capping wafer) in turn for aligning the rooms into repetitions of a V element room and a diffusion room. The V element room or the capping wafer covers and protects the object wafer during the heating step. During the diffusion step, the diffusion room covers the object wafer for diffusing Zn into the wafer.
摘要翻译：将LPE（液相外延）装置转移到用于将Zn扩散到III-V族化合物半导体中的Zn扩散装置。 Zn扩散装置包括沿着方向延伸的底板，具有用于存储物体晶片的晶片储存腔和用于呼出气体的排气孔;具有框架的滑块和用于附接到框架或从框架拆卸的盖板（M-1）分隔壁彼此分离的具有开放底部和齿条的M个房间的框架，用于将滑块在基板上沿着该方向向前或向后滑动的操纵杆，用于封闭基板和滑块并且能够被制成真空的围绕管的加热器的加热器，每个机架的房间被分配有Zn扩散材料和V元件材料（或非掺杂的盖子晶片）反过来将房间对准V元件室和扩散室的重复。 V元件室或封盖晶片在加热步骤期间覆盖并保护对象晶片。在扩散步骤期间，扩散室覆盖用于将Zn扩散到晶片中的目标晶片。

9. 发明授权

US06645839B2 Method for improving a doping profile for gas phase doping 有权
标题翻译：改善气相掺杂掺杂特性的方法
公开(公告)号：US06645839B2
公开(公告)日：2003-11-11
申请号：US10139165
申请日：2002-05-06
申请人： Moritz Haupt , Anja Morgenschweis , Dietmar Ottenwälder , Uwe Schröder
发明人： Moritz Haupt , Anja Morgenschweis , Dietmar Ottenwälder , Uwe Schröder
IPC分类号： H01L2138
CPC分类号： H01L21/223 , H01L27/1087 , Y10S438/914 , Y10S438/923
摘要： A method for improving a doping profile using gas phase doping is described. In the method, silicon nitride and/or products of decomposition from a silicon nitride deposition are introduced in a process chamber before or during the actual gas phase doping. This allows the doping profile to be significantly improved.
摘要翻译：描述了使用气相掺杂改善掺杂分布的方法。在该方法中，氮化硅和/或氮化硅沉积的分解产物在实际气相掺杂之前或期间被引入处理室中。这允许显着改善掺杂分布。

10. 发明授权

US06516743B2 Method and apparatus diffusing zinc into groups III-V compound semiconductor crystals 失效
标题翻译：将锌扩散到III-V族化合物半导体晶体中的方法和装置
公开(公告)号：US06516743B2
公开(公告)日：2003-02-11
申请号：US09773545
申请日：2001-02-02
申请人： Yasuhiro Iguchi , Sosuke Sowa
发明人： Yasuhiro Iguchi , Sosuke Sowa
IPC分类号： H01L2138
CPC分类号： H01L21/67109 , H01L21/2233
摘要： An LPE (Liquid Phase Epitaxy) apparatus is diverted to a Zn-diffusion apparatus for diffusing Zn into III-V group compound semiconductor. The Zn-diffusion apparatus comprises a base plank extending in a direction, having a wafer-storing cavity for storing an object wafer and an exhaustion hole for exhaling gases, a slider having a frame and a cap plate for attaching to or detaching from the frame, the frame having serially aligning M rooms with an open bottom and a rack being separated from each other by (M−1) partition walls, a manipulating bar for sliding the slider upon the base plank forward or backward in the direction, a tube for enclosing the base plank and the slider and for being capable of being made vacuous, a heater surrounding the tube for heating the slider, each rack of the rooms being allocated with a Zn-diffusion material and a V element material (or a non-doped capping wafer) in turn for aligning the rooms into repetitions of a V element room and a diffusion room. The V element room or the capping wafer covers and protects the object wafer during the heating step. During the diffusion step, the diffusion room covers the object wafer for diffusing Zn into the wafer.
摘要翻译：将LPE（液相外延）装置转移到用于将Zn扩散到III-V族化合物半导体中的Zn扩散装置。 Zn扩散装置包括沿着方向延伸的底板，具有用于存储物体晶片的晶片储存腔和用于呼出气体的排气孔;具有框架的滑块和用于附接到框架或从框架拆卸的盖板（M-1）分隔壁彼此分离的具有开放底部和齿条的M个房间的框架，用于将滑块在基板上沿着该方向向前或向后滑动的操纵杆，用于封闭基板和滑块并且能够被制成真空的围绕管的加热器的加热器，每个机架的房间被分配有Zn扩散材料和V元件材料（或非掺杂的盖子晶片）反过来将房间对准V元件室和扩散室的重复。 V元件室或封盖晶片在加热步骤期间覆盖并保护对象晶片。在扩散步骤期间，扩散室覆盖用于将Zn扩散到晶片中的目标晶片。

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