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1. 发明申请

US20090271585A1 DATA ACCESSING SYSTEM AND RELATED STORAGE DEVICE 审中-公开
标题翻译：数据访问系统及相关存储设备
公开(公告)号：US20090271585A1
公开(公告)日：2009-10-29
申请号：US12342083
申请日：2008-12-23
申请人： Tung-Cheng Kuo , Ching-Sung Yang , Ruei-Ling Lin , Cheng-Jye Liu
发明人： Tung-Cheng Kuo , Ching-Sung Yang , Ruei-Ling Lin , Cheng-Jye Liu
IPC分类号： G06F12/14 , G06F12/00
CPC分类号： G06F21/445
摘要： A data accessing system includes a host computer and a storage device. The host computer has a first media access control (MAC) address, and the storage device includes a first storage region, a second storage region, and a controller. The first storage region is utilized for storing data. The second storage region stores a second media access control address. The controller couples to the first storage region and the second storage region for executing a security checking function to determine if the host computer is qualified to access the first storage region according to the first media access control address.
摘要翻译：数据访问系统包括主计算机和存储设备。主机具有第一媒体访问控制（MAC）地址，存储装置包括第一存储区域，第二存储区域和控制器。第一存储区域用于存储数据。第二存储区域存储第二媒体访问控制地址。控制器耦合到第一存储区域和第二存储区域，用于执行安全检查功能，以根据第一媒体访问控制地址确定主计算机是否有资格访问第一存储区域。

2. 发明申请

US20080186084A1 VOLTAGE STABILIZING CIRCUIT FOR CHIPS AND METHOD THEREOF 审中-公开
标题翻译：电压稳定电路及其方法
公开(公告)号：US20080186084A1
公开(公告)日：2008-08-07
申请号：US12022434
申请日：2008-01-30
申请人： Yi-Lin Chen , Tung-Cheng Kuo
发明人： Yi-Lin Chen , Tung-Cheng Kuo
IPC分类号： G05F3/16 , G05F3/02
CPC分类号： H03K19/00315 , G11C5/147 , H03K19/00384
摘要： A voltage stabilizing circuit for chips and the method thereof are disclosed. The circuit and the method thereof are applied to chips with at least one non-wire bonded I/O circuit. The driver circuit of the I/O circuit includes a plurality of transistors. The method of voltage stabilizing involves causing at least one of these transistors to start conducting in order to generate a stabilizing capacitor. Therefore, chip damages caused by voltage or current fluctuations can be avoided, simultaneously reducing the cost and the amount of chip surface area being consumed.
摘要翻译：公开了一种用于芯片的稳压电路及其方法。电路及其方法应用于具有至少一个非线接合I / O电路的芯片。 I / O电路的驱动电路包括多个晶体管。电压稳定的方法包括使这些晶体管中的至少一个开始导通以产生稳定电容器。因此，可以避免由电压或电流波动引起的芯片损坏，同时降低成本和芯片表面积的消耗量。

3. 发明授权

US06898127B2 Method for fabricating embedded flash ROM structure having code cells and data cells and operations for the same 有权
标题翻译：用于制造具有代码单元和数据单元的嵌入式闪存ROM结构的方法及其操作
公开(公告)号：US06898127B2
公开(公告)日：2005-05-24
申请号：US10112311
申请日：2002-03-27
申请人： Tung-Cheng Kuo
发明人： Tung-Cheng Kuo
IPC分类号： G11C16/04 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11568 , G11C16/0466 , H01L27/115
摘要： A method for fabricating an embedded flash ROM structure having code cells and data cells. A substrate is provided and then a plurality of bit lines are formed over the substrate. A plurality of isolation structures are formed over the bit lines and a charge trapping layer is formed between the isolation structures. A plurality of word lines are formed over the isolation structures and the charge trapping layer to form the embedded flash ROM structure. According to requirement, embedded flash ROM structure is divided into a code cell region and a data cell region.
摘要翻译：一种用于制造具有代码单元和数据单元的嵌入式快闪ROM结构的方法。提供衬底，然后在衬底上形成多个位线。在位线之间形成多个隔离结构，并且在隔离结构之间形成电荷捕获层。多个字线形成在隔离结构和电荷俘获层上，以形成嵌入式闪存ROM结构。根据要求，嵌入式闪存ROM结构分为码单元区和数据单元区。

4. 发明授权

US06797635B2 Fabrication method for lines of semiconductor device 有权
标题翻译：半导体器件线路的制造方法
公开(公告)号：US06797635B2
公开(公告)日：2004-09-28
申请号：US10142696
申请日：2002-05-08
申请人： Tung-Cheng Kuo
发明人： Tung-Cheng Kuo
IPC分类号： H01L21302
CPC分类号： G03F1/36 , H01L21/32139
摘要： A fabrication method for lines of a semiconductor device provides a substrate with a deposition layer already formed thereon, followed by forming a photoresist layer on the deposition layer. Photolithography is conducted with a mask to pattern the photoresist layer, wherein the photoresist layer is designed with the consideration of both the proximity effect and the microloading effect due to etching. Thereafter, using the patterned photoresist layer as an etching mask, an etching is conducted to form a plurality of lines. Since during the patterning of the photoresist layer, the proximity effect and the microlaoding effect are being considered, the difference in the linewidths between the dense feature region and the scattered feature region is minimized after the etching process.
摘要翻译：用于半导体器件的线的制造方法为衬底提供已经在其上形成的沉积层，随后在沉积层上形成光致抗蚀剂层。用掩模进行光刻以对光致抗蚀剂层进行图案化，其中考虑到由于蚀刻引起的邻近效应和微加载效应，设计光致抗蚀剂层。此后，使用图案化的光致抗蚀剂层作为蚀刻掩模，进行蚀刻以形成多条线。由于在光致抗蚀剂层的图案化期间，考虑了接近效应和微致密效应，所以在蚀刻处理之后，致密特征区域和散射特征区域之间的线宽的差异被最小化。

5. 发明授权

US06555866B1 Non-volatile memory and fabrication thereof 有权
标题翻译：非易失性存储器及其制造
公开(公告)号：US06555866B1
公开(公告)日：2003-04-29
申请号：US10112312
申请日：2002-03-27
申请人： Tung-Cheng Kuo
发明人： Tung-Cheng Kuo
IPC分类号： H01L2976
CPC分类号： H01L27/11568 , H01L27/115
摘要： A non-volatile memory and the fabrication thereof are described. The non-volatile memory comprises a substrate having a trench therein, a buried bit-line in the substrate crossing the trench, a word-line covering at least the trench and crossing over the buried bit-line, and a charge trapping layer between the substrate and the word-line.
摘要翻译：描述非易失性存储器及其制造。非易失性存储器包括其中具有沟槽的衬底，衬底中与衬底交叉的掩埋位线，至少覆盖沟槽并跨过掩埋位线的字线，以及位于掩模位线之间的电荷俘获层底物和字线。

6. 发明授权

US06545309B1 Nitride read-only memory with protective diode and operating method thereof 有权
标题翻译：具有保护二极管的氮化物只读存储器及其操作方法
公开(公告)号：US06545309B1
公开(公告)日：2003-04-08
申请号：US10104397
申请日：2002-03-22
申请人： Tung-Cheng Kuo
发明人： Tung-Cheng Kuo
IPC分类号： H01L27108
CPC分类号： H01L27/11568 , G11C16/0466 , H01L27/105 , H01L27/11573
摘要： A NROM with a protective diode is described. The NROM comprises a substrate, a NROM cell, an n+-doped region, an n+-doped guard ring and a polysilicon guard ring, wherein the substrate, the n+-doped region, the n+-doped guard ring and the polysilicon guard ring constitute a protective diode. The NROM cell is disposed on the substrate. The n+-doped region is located in the substrate and is electrically connected with a word-line of the NROM cell. The n+ guard ring is located in the substrate surrounding the n+-doped region. The polysilicon guard ring is disposed on the substrate between the n+-doped region and the n+-doped guard ring.
摘要翻译：描述了具有保护二极管的NROM。 NROM包括衬底，NROM单元，n +掺杂区，n +掺杂的保护环和多晶硅保护环，其中衬底，n +掺杂区，n +掺杂的保护环和多晶硅保护环构成一个保护二极管。 NROM单元设置在基板上。 n +掺杂区位于衬底中并与NROM单元的字线电连接。 n +保护环位于围绕n +掺杂区域的衬底中。多晶硅保护环设置在n +掺杂区域和n +掺杂保护环之间的衬底上。

7. 发明授权

US06477085B1 Method for operating non-volatile memory with symmetrical dual-channels 有权
公开(公告)号：US06477085B1
公开(公告)日：2002-11-05
申请号：US09994767
申请日：2001-11-28
申请人： Tung-Cheng Kuo
发明人： Tung-Cheng Kuo
IPC分类号： G11C1604
CPC分类号： G11C16/0466
摘要： A method for operating a non-volatile memory with symmetrical dual-channels. A programmed step is performed on the non-volatile memory to retain charges in both sides of an ONO layer so that the symmetrical dual-channels are generated and the one-bit writing step is completed. Afterwards, a selected voltage is simultaneously exerted on a first bit line and a third bit line to select a second bit line of the symmetrical dual-channels. Finally, a reading voltage is applied to the second bit line to acquire a reading current which is the sum of total current through the symmetrical dual-channels for increasing the reading speed of the non-volatile memory.

8. 发明授权

US06417053B1 Fabrication method for a silicon nitride read-only memory 有权
标题翻译：氮化硅只读存储器的制造方法
公开(公告)号：US06417053B1
公开(公告)日：2002-07-09
申请号：US09990455
申请日：2001-11-20
申请人： Tung-Cheng Kuo
发明人： Tung-Cheng Kuo
IPC分类号： H01L21336
CPC分类号： H01L21/28282
摘要： A fabrication method for a silicon nitride read-only memory is described. A silicon nitride read-only memory and a grounding doped region are formed in the substrate. A contact is formed on the substrate. A metal protection line is also formed, wherein the metal protection line is electrically connected to the word line of the silicon nitride read-only memory. Moreover, the metal protection line is electrically connected the grounding doped region through the contact to conduct charges generated during the manufacturing process to the substrate. The resistance of the metal protection line is higher than that of the word line. A high current is then used to bum out the metal protection line after the formation of the metal interconnect on the substrate to ensure a normal function of the memory device.
摘要翻译：描述了氮化硅只读存储器的制造方法。在衬底中形成氮化硅只读存储器和接地掺杂区域。在基板上形成接触。还形成金属保护线，其中金属保护线与氮化硅只读存储器的字线电连接。此外，金属保护线通过接触电连接到接地掺杂区域，以将制造过程中产生的电荷导入衬底。金属保护线的电阻高于字线。然后在衬底上形成金属互连件之后，使用高电流来使金属保护线烧结，以确保存储器件的正常功能。

9. 发明授权

US06388913B1 Method for detecting polarization of a ferroelectric capacitor in a ferroelectric memory and thereof structure 有权
标题翻译：铁电存储器中的铁电电容器的极化检测方法及其结构
公开(公告)号：US06388913B1
公开(公告)日：2002-05-14
申请号：US09772326
申请日：2001-01-30
申请人： Tung-Cheng Kuo , Hsiang-Lan Lung , Shue-Shuen Chen
发明人： Tung-Cheng Kuo , Hsiang-Lan Lung , Shue-Shuen Chen
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A method for detecting polarization of a ferroelectric capacitor in a ferroelectric memory and thereof structure is provided by detecting polarization of a ferroelectric capacitor through a characteristic which present different voltage values by providing different voltages on the ferroelectric capacitor stay at different polarization directions, so that the disadvantages caused by a conventional method for detecting charge quantity can be improved and a limited size of a capacitance of the cell ferroelectric capacitor can be solved. The method for detecting comprises the step of detecting an output voltage on a connection node between a cell ferroelectric capacitor and a sense linear capacitor, and then if the detected output voltage is high read voltage, a logic state of the cell ferroelectric capacitor is decided to a first logic state, if the detected output voltage is low read voltage, a logic state of the cell ferroelectric capacitor is decided to a second logic state.
摘要翻译：通过在强电介质电容器停留在不同的极化方向上提供不同的电压，通过检测出不同的电压值的特性来检测铁电电容器的偏振，从而提供强电介质存储器中铁电电容器的极化检测方法，可以提高由传统的检测电荷量的方法引起的缺点，并且可以解决单元铁电电容器的电容的有限尺寸。检测方法包括检测单元铁电电容器和感测线性电容器之间的连接节点上的输出电压的步骤，然后如果检测到的输出电压为高读取电压，则判定单元铁电电容器的逻辑状态第一逻辑状态，如果检测到的输出电压为低读取电压，则将单元铁电电容器的逻辑状态判定为第二逻辑状态。

10. 发明授权

US06385077B1 Non-volatile memory cell and sensing method 有权
标题翻译：非易失性存储单元和感测方法
公开(公告)号：US06385077B1
公开(公告)日：2002-05-07
申请号：US09732019
申请日：2000-12-08
申请人： Tung-Cheng Kuo , Hsiang-Lan Lung , Shue-Shuen Chen
发明人： Tung-Cheng Kuo , Hsiang-Lan Lung , Shue-Shuen Chen
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A non-volatile ferroelectric capacitor memory of the present invention comprises a plurality of word lines located in parallel to each other, a plurality of bit lines across the word lines, a plurality of sensing ferroelectric capacitor connected to ground, a plurality of output transistors, and a plurality of memory cells located at intersections between each word line and bit line. In each of the memory cells including a depletion field effect transistor and a ferroelectric capacitor, the first electrode plate of the ferroelectric capacitor is connected to the depletion field effect transistor and the second electrode plate is connected to the bit line, and the gate electrode of the depletion field effect transistor is connected to the bit line.
摘要翻译：本发明的非挥发性铁电电容器存储器包括彼此平行的多个字线，跨越字线的多个位线，连接到地的多个感测铁电电容器，多个输出晶体管，以及位于每个字线和位线之间的交叉点处的多个存储单元。在包括耗尽场效应晶体管和铁电电容器的每个存储单元中，强电介质电容器的第一电极板连接到耗尽场效应晶体管，第二电极板连接到位线，栅电极耗尽场效应晶体管连接到位线。

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