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1. 发明授权

US06339015B1 Method of fabricating a non-volatile semiconductor device 失效
标题翻译：制造非易失性半导体器件的方法
公开(公告)号：US06339015B1
公开(公告)日：2002-01-15
申请号：US09574410
申请日：2000-05-18
申请人： John A. Bracchitta , James S. Nakos
发明人： John A. Bracchitta , James S. Nakos
IPC分类号： H01L2138
CPC分类号： H01L29/7883 , H01L21/28273 , H01L29/42336
摘要： A non-volatile random access memory (NVRAM) cell and methods of forming thereof are disclosed. The NVRAM cell includes a substrate having source and drain regions. A spike having a sharp tip extends in the source region. Instead of a single spike, two adjacent spikes are included in the source. Alternatively, in addition to the single spike in the source, two adjacent spikes are included in the drain. The two adjacent spikes have one tip pointing toward the floating gate and two tips pointing away from the floating gate. The spikes provide high electric field to facilitate charge movement between the floating gate and the source region. A tunnel oxide layer separates the floating gate from the substrate. A gate oxide and a control gate are also formed over the floating gate. The single spike is formed by preferentially etching the substrate along a selected crystal plane through an opening formed in a mask that covers the substrate. The two adjacent spikes are formed by first forming spacers on sidewalls of the opening to reduce a width thereof; filling the reduced opening with a mask plug; removing the sidewalls; and etching the substrate.
摘要翻译：公开了非易失性随机存取存储器（NVRAM）单元及其形成方法。 NVRAM单元包括具有源区和漏区的衬底。具有尖锐尖端的尖端在源区域中延伸。代替单个尖峰，源中包含两个相邻的尖峰。或者，除了源中的单个尖峰之外，两个相邻的尖峰包括在排水管中。两个相邻的尖峰具有指向浮动门的一个尖端和指向远离浮动门的两个尖端。尖峰提供高电场以促进浮动栅极和源极区域之间的电荷移动。隧道氧化层将浮栅与衬底分开。栅极氧化物和控制栅极也形成在浮动栅极上。通过优选地通过形成在覆盖衬底的掩模中形成的开口沿着选定的晶面蚀刻衬底而形成单个尖峰。两个相邻的钉是通过在开口的侧壁上首先形成间隔物而形成的，以减小其宽度; 用面罩塞填充减小的开口; 去除侧壁; 并蚀刻衬底。

2. 发明授权

US06373095B1 NVRAM cell having increased coupling ratio between a control gate and floating gate without an increase in cell area 失效
标题翻译： NVRAM单元在控制栅极和浮动栅极之间具有增加的耦合比，而不增加单元面积
公开(公告)号：US06373095B1
公开(公告)日：2002-04-16
申请号：US09030094
申请日：1998-02-25
申请人： John A. Bracchitta , James S. Nakos
发明人： John A. Bracchitta , James S. Nakos
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： A field effect floating gate transistor forming an NVRAM cell is disclosed. A substrate having field isolation structures includes therebetween a doped region forming a channel connecting a source and drain. An oxide layer is disposed over said channel forming a tunneling oxide layer for the device. A layer of polysilicon extends over the oxide layer, to each of the isolation structures and then extends upwards forming a U-shaped pillar floating gate. A second oxide layer disposed within the interior of the U-shaped floating gate supports a control gate. A second layer of polysilicon formed over the second oxide layer forms a control gate, and is connected to a conductor which is common to a row of such cells within a memory. The control gate is coupled to the floating gate through the second oxide layer to the upwardly extending layer of the floating gate as well as over the portion of the floating gate extending over the channel.
摘要翻译：公开了形成NVRAM单元的场效应浮栅晶体管。具有场隔离结构的衬底之间包括形成连接源极和漏极的沟道的掺杂区域。在所述通道上设置氧化物层，形成用于该器件的隧穿氧化物层。一层多晶硅在氧化物层上延伸到每个隔离结构，然后向上延伸形成U形柱状浮动栅极。设置在U形浮动门的内部的第二氧化物层支撑控制门。形成在第二氧化物层上的第二层多晶硅形成控制栅极，并且连接到存储器内的一排这样的单元的公共导体。控制栅极通过第二氧化物层与浮动栅极耦合到浮动栅极的向上延伸层以及在通道上延伸的浮置栅极的部分之上。

3. 发明授权

US06232633B1 NVRAM cell using sharp tip for tunnel erase 失效
标题翻译： NVRAM单元使用锋利的尖端进行隧道擦除
公开(公告)号：US06232633B1
公开(公告)日：2001-05-15
申请号：US09093165
申请日：1998-06-08
申请人： John A. Bracchitta , James S. Nakos
发明人： John A. Bracchitta , James S. Nakos
IPC分类号： H01L29788
CPC分类号： H01L29/7883 , H01L21/28273 , H01L29/42336
摘要： A non-volatile random access memory (NVRAM) cell and methods of forming thereof are disclosed. The NVRAM cell includes a substrate having source and drain regions. A spike having a sharp tip extends in the source region. Instead of a single spike, two adjacent spikes are included in the source. Alternatively, in addition to the single spike in the source, two adjacent spikes are included in the drain. The two adjacent spikes have one tip pointing toward the floating gate and two tips pointing away from the floating gate. The spikes provide high electric field to facilitate charge movement between the floating gate and the source region. A tunnel oxide layer separates the floating gate from the substrate. A gate oxide and a control gate are also formed over the floating gate. The single spike is formed by preferentially etching the substrate along a selected crystal plane through an opening formed in a mask that covers the substrate. The two adjacent spikes are formed by first forming spacers on sidewalls of the opening to reduce a width thereof; filling the reduced opening with a mask plug; removing the sidewalls; and etching the substrate.
摘要翻译：公开了非易失性随机存取存储器（NVRAM）单元及其形成方法。 NVRAM单元包括具有源区和漏区的衬底。具有尖锐尖端的尖端在源区域中延伸。代替单个尖峰，源中包含两个相邻的尖峰。或者，除了源中的单个尖峰之外，两个相邻的尖峰包括在排水管中。两个相邻的尖峰具有指向浮动门的一个尖端和指向远离浮动门的两个尖端。尖峰提供高电场以促进浮动栅极和源极区域之间的电荷移动。隧道氧化层将浮栅与衬底分开。栅极氧化物和控制栅极也形成在浮动栅极上。通过优选地通过形成在覆盖衬底的掩模中形成的开口沿着选定的晶面蚀刻衬底而形成单个尖峰。两个相邻的钉是通过在开口的侧壁上首先形成间隔物而形成的，以减小其宽度; 用面罩塞填充减少的开口; 去除侧壁; 并蚀刻衬底。

4. 发明授权

US06882015B2 Intralevel decoupling capacitor, method of manufacture and testing circuit of the same 失效
公开(公告)号：US06882015B2
公开(公告)日：2005-04-19
申请号：US10660755
申请日：2003-09-12
申请人： Kerry Bernstein , John A. Bracchitta , William J. Cote , Tak H. Ning , Wilbur D. Pricer
发明人： Kerry Bernstein , John A. Bracchitta , William J. Cote , Tak H. Ning , Wilbur D. Pricer
IPC分类号： H01L21/02 , H01L27/08 , H01L29/76
CPC分类号： H01G4/1272 , H01G4/35 , H01L22/14 , H01L22/22 , H01L23/5223 , H01L23/642 , H01L27/0805 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/3011 , Y10T29/435 , H01L2924/00
摘要： A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.

5. 发明授权

US6130469A Electrically alterable antifuse using FET 失效
标题翻译：使用FET的电可变反熔丝
公开(公告)号：US6130469A
公开(公告)日：2000-10-10
申请号：US66122
申请日：1998-04-24
申请人： John A. Bracchitta , Wilbur D. Pricer
发明人： John A. Bracchitta , Wilbur D. Pricer
IPC分类号： H01L23/525 , H01L29/00 , H01L23/58 , H01L29/04 , H01L29/74
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： An integrated circuit and fabrication method for an antifuse structure that includes a shallow trench oxide isolation region disposed in a silicon substrate, the oxide in the trench having a top surface recessed below the surface of the substrate to form sharp corners at each side of the trench. The substrate includes diffusion regions adjacent to the sharp corners, electrical insulation layers over the diffusion regions, and an electrical conductor is disposed over the recessed oxide in the trench. When voltage is applied on the electrical conductor, a high field point is produced at the sharp corners causing the electrical insulation layer at the corners to break down and create a short circuit between the electrical conductor and the diffusions, thus providing a fuse function.
摘要翻译：一种用于反熔丝结构的集成电路和制造方法，其包括设置在硅衬底中的浅沟槽氧化物隔离区域，沟槽中的氧化物具有在衬底的表面下方凹陷的顶表面，以在沟槽的每一侧形成锐角。衬底包括与锐角相邻的扩散区域，在扩散区域上的电绝缘层，并且电导体设置在沟槽中的凹陷氧化物上。当电压施加在电导体上时，在尖角产生高场点，导致拐角处的电绝缘层分解，并在电导体和扩散之间产生短路，从而提供保险丝功能。

6. 发明授权

US06858889B2 Polysilicon capacitor having large capacitance and low resistance 失效
标题翻译：具有大电容和低电阻的多晶硅电容器
公开(公告)号：US06858889B2
公开(公告)日：2005-02-22
申请号：US09878117
申请日：2001-06-08
申请人： James W. Adkisson , John A. Bracchitta , Jed H. Rankin , Anthony K. Stamper
发明人： James W. Adkisson , John A. Bracchitta , Jed H. Rankin , Anthony K. Stamper
IPC分类号： H01L21/02 , H01L21/314 , H01L21/334 , H01L21/8242 , H01L29/78 , H01L33/00
CPC分类号： H01L28/75 , H01L21/3144 , H01L28/91
摘要： A process for forming capacitors in a semiconductor device. In one embodiment, a first insulating layer is deposited on the semiconductor device; a trench is formed in the insulating layer; a first low resistance metal layer is formed covering the interior surface of the trench; a first polysilicon layer is formed over the first low resistance metal layer; a first dielectric layer is formed over the first polysilicon layer; a second polysilicon layer is formed over the first dielectric layer; a second low resistance metal layer is formed over the second polysilicon layer; a third polysilicon layer is formed over the second low resistance metal layer; a second dielectric layer is formed over the third polysilicon layer; a fourth polysilicon layer is formed over the second dielectric layer; a third low resistance metal layer is formed over the fourth polysilicon layer until the trench is filled; the semiconductor device is planarized until the first, second and third low resistance metal layers are exposed above the trench; finally, capacitor leads are formed to the first, second, and third low resistance metal layers.
摘要翻译：一种用于在半导体器件中形成电容器的工艺。在一个实施例中，第一绝缘层沉积在半导体器件上; 在绝缘层中形成沟槽; 形成覆盖沟槽内表面的第一低电阻金属层; 在第一低电阻金属层上形成第一多晶硅层; 第一介电层形成在第一多晶硅层上; 在第一介电层上形成第二多晶硅层; 在第二多晶硅层上形成第二低电阻金属层; 在第二低电阻金属层上形成第三多晶硅层; 在所述第三多晶硅层上形成第二电介质层; 在第二介电层上形成第四多晶硅层; 第四低电阻金属层形成在第四多晶硅层上，直到沟槽被填充; 半导体器件被平坦化，直到第一，第二和第三低电阻金属层暴露在沟槽上方; 最后，对第一，第二和第三低电阻金属层形成电容器引线。

7. 发明授权

US6020777A Electrically programmable anti-fuse circuit 失效
标题翻译：电子可编程反熔丝电路
公开(公告)号：US6020777A
公开(公告)日：2000-02-01
申请号：US938754
申请日：1997-09-26
申请人： John A. Bracchitta , Wilbur D. Pricer
发明人： John A. Bracchitta , Wilbur D. Pricer
IPC分类号： G11C17/16 , H01H37/76
CPC分类号： G11C17/16
摘要： An array of anti-fuse cells forming rows and columns of a matrix is described. The anti-fuse cell includes an MOS capacitor connected to a source of high voltage which is capable of rendering the capacitor permanently conductive. A first voltage limiting transistor connects the free end of the MOS capacitor to a second transistor. An address decoder provides address signals to a source and gate of the second transistor within the cell. The MOS capacitor is rendered permanently conductive when the first and second transistors are rendered conductive. The high voltage is confined to the MOS capacitor, which is fused through the high current being drawn through the capacitor by the first and second transistors. Other components on the integrated circuit carrying the array of fusible cells are maintained free of any high voltage.
摘要翻译：描述形成矩阵行和列的反熔丝单元的阵列。反熔丝单元包括连接到能够使电容器永久导电的高电压源的MOS电容器。第一电压限制晶体管将MOS电容器的自由端连接到第二晶体管。地址解码器向单元内的第二晶体管的源极和栅极提供地址信号。当第一和第二晶体管导通时，MOS电容器被永久导通。高电压被限制在MOS电容器中，MOS电容器通过第一和第二晶体管通过电容器吸收的高电流熔断。携带易熔电池阵列的集成电路上的其他部件保持不受任何高电压的影响。

8. 发明授权

US5734192A Trench isolation for active areas and first level conductors 失效
公开(公告)号：US5734192A
公开(公告)日：1998-03-31
申请号：US581680
申请日：1995-12-22
申请人： Edward W. Sengle , Mark D. Jaffe , Daniel Nelson Maynard , Mark Alan Lavin , Eric Jeffrey White , John A. Bracchitta
发明人： Edward W. Sengle , Mark D. Jaffe , Daniel Nelson Maynard , Mark Alan Lavin , Eric Jeffrey White , John A. Bracchitta
IPC分类号： H01L21/762 , H01L23/522 , H01L29/00
CPC分类号： H01L21/76224 , H01L23/5222 , H01L2924/0002
摘要： A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the outside by inactive semiconductor area. The isolation path extends from the isolation ring through the inactive semiconductor area. A first level conductor on the isolation path electrically connects or capacitively couples a device in the active semiconductor area to a location on the substrate outside the isolation ring. The isolation path has a configuration derived from the layout of the conductor.

9. 发明授权

US07323382B2 Intralevel decoupling capacitor, method of manufacture and testing circuit of the same 有权
标题翻译：内部去耦电容器，制造和测试电路的方法
公开(公告)号：US07323382B2
公开(公告)日：2008-01-29
申请号：US11707060
申请日：2007-02-16
申请人： Kerry Bernstein , John A. Bracchitta , William J. Cote , Tak H. Ning , Wilbur D. Pricer
发明人： Kerry Bernstein , John A. Bracchitta , William J. Cote , Tak H. Ning , Wilbur D. Pricer
IPC分类号： H01L21/8242
CPC分类号： H01G4/1272 , H01G4/35 , H01L22/14 , H01L22/22 , H01L23/5223 , H01L23/642 , H01L27/0805 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/3011 , Y10T29/435 , H01L2924/00
摘要： A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.
摘要翻译：为半导体器件提供去耦电容器，并且可以包括在单个互连平面中在第一低介电绝缘体的表面上形成至少两个交叉指示图案的第一低介电绝缘体层和低电阻导体。可以在两个图案之间提供高介电常数材料。还提供了用于测试多个这些电容器的电路，其包括充电监视电路，耦合电路和控制电路。

10. 发明授权

US07195971B2 Method of manufacturing an intralevel decoupling capacitor 有权
标题翻译：制造级联去耦电容器的方法
公开(公告)号：US07195971B2
公开(公告)日：2007-03-27
申请号：US11066738
申请日：2005-02-28
申请人： Kerry Bernstein , John A. Bracchitta , William J. Cote , Tak H. Ning , Wilbur D. Pricer
发明人： Kerry Bernstein , John A. Bracchitta , William J. Cote , Tak H. Ning , Wilbur D. Pricer
IPC分类号： H01L21/8242
CPC分类号： H01G4/1272 , H01G4/35 , H01L22/14 , H01L22/22 , H01L23/5223 , H01L23/642 , H01L27/0805 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/3011 , Y10T29/435 , H01L2924/00
摘要： A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.
摘要翻译：为半导体器件提供去耦电容器，并且可以包括在单个互连平面中在第一低介电绝缘体的表面上形成至少两个交叉指示图案的第一低介电绝缘体层和低电阻导体。可以在两个图案之间提供高介电常数材料。还提供了用于测试多个这些电容器的电路，其包括充电监视电路，耦合电路和控制电路。

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