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1. 发明授权

US08410820B2 High speed latch comparators 有权
公开(公告)号：US08410820B2
公开(公告)日：2013-04-02
申请号：US13026904
申请日：2011-02-14
申请人： Klaas Bult , Rudy Van de Plassche , Jan Mulder
发明人： Klaas Bult , Rudy Van de Plassche , Jan Mulder
IPC分类号： G01R19/00 , G11C7/00 , H03K3/45
CPC分类号： H03K3/356043 , H03K3/012 , H03K3/35613 , H03K3/356182 , H03K3/356191 , H03M1/002 , H03M1/362
摘要： In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

2. 发明授权

US07352215B2 High speed latch comparators 有权
标题翻译：高速锁存比较器
公开(公告)号：US07352215B2
公开(公告)日：2008-04-01
申请号：US10649808
申请日：2003-08-28
申请人： Klaas Bult , Rudy Van de Plassche , Jan Mulder
发明人： Klaas Bult , Rudy Van de Plassche , Jan Mulder
IPC分类号： G01R19/00 , G11C7/00 , H03K3/45
CPC分类号： H03K3/356043 , H03K3/012 , H03K3/35613 , H03K3/356182 , H03K3/356191 , H03M1/002 , H03M1/362
摘要： In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.
摘要翻译：在具有第一极性的双稳态交叉晶体管对和第二极性的第三晶体管的锁存电路中，在锁存电路端口处接收大于偏置电流的电流信号，用第三晶体管放大并施加到锁存电路端口。这减小了接收大于偏置电流的电流信号的锁存电路端口达到稳态电压的时间。

3. 发明授权

US06639430B2 High speed latch comparators 失效
公开(公告)号：US06639430B2
公开(公告)日：2003-10-28
申请号：US10083463
申请日：2002-02-27
申请人： Klaas Bult , Rudy Van de Plassche , Jan Mulder
发明人： Klaas Bult , Rudy Van de Plassche , Jan Mulder
IPC分类号： G11C706
CPC分类号： H03K3/356043 , H03K3/012 , H03K3/35613 , H03K3/356182 , H03K3/356191 , H03M1/002 , H03M1/362
摘要： In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

4. 发明授权

US07906992B2 High speed latch comparators 有权
标题翻译：高速锁存比较器
公开(公告)号：US07906992B2
公开(公告)日：2011-03-15
申请号：US12040805
申请日：2008-02-29
申请人： Klaas Bult , Rudy Van de Plassche , Jan Mulder
发明人： Klaas Bult , Rudy Van de Plassche , Jan Mulder
IPC分类号： G01R19/00 , G11C7/00
CPC分类号： H03K3/356043 , H03K3/012 , H03K3/35613 , H03K3/356182 , H03K3/356191 , H03M1/002 , H03M1/362
摘要： In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.
摘要翻译：在具有第一极性的双稳态交叉晶体管对和第二极性的第三晶体管的锁存电路中，在锁存电路端口处接收大于偏置电流的电流信号，用第三晶体管放大并施加到锁存电路端口。这减小了接收大于偏置电流的电流信号的锁存电路端口达到稳态电压的时间。

5. 发明授权

US06583747B1 Subranging analog to digital converter with multi-phase clock timing 失效
公开(公告)号：US06583747B1
公开(公告)日：2003-06-24
申请号：US10158773
申请日：2002-05-31
申请人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Rudy van de Plassche , Marcel Lugthart
发明人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Rudy van de Plassche , Marcel Lugthart
IPC分类号： H03M112
CPC分类号： H03M1/146 , H03K17/04106 , H03M1/204 , H03M1/365
摘要： An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

6. 发明授权

US06653966B1 Subranging analog to digital converter with multi-phase clock timing 有权
标题翻译：使用多相时钟定时将模数转换器分段
公开(公告)号：US06653966B1
公开(公告)日：2003-11-25
申请号：US10359201
申请日：2003-02-06
申请人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Rudy van de Plassche , Marcel Lugthart
发明人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Rudy van de Plassche , Marcel Lugthart
IPC分类号： H03M100
CPC分类号： H03M1/146 , H03K17/04106 , H03M1/204 , H03M1/365
摘要： An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.
摘要翻译： N位模数转换器包括参考梯形图，连接到输入电压的跟踪和保持放大器，在其输入处连接到粗略电容器的粗略ADC放大器，并具有由第一时钟控制的粗略ADC复位开关两相时钟的相位，精细ADC放大器在其输入端连接到精细电容器，并具有由两相时钟的第二时钟相位控制的精细ADC复位开关，开关矩阵从第二时钟相位选择电压子范围参考梯形图，用于基于粗ADC放大器的输出的精细ADC放大器使用，并且其中粗电容器在第一时钟相位期间被充电到粗略的参考梯形电压，并且在第二时钟相位期间连接到T / H输出其中精细电容器在第一时钟相位期间连接到电压子范围，并且在第二时钟相位期间连接到T / H输出;以及编码器，其将粗略和精细ADC放大器的输出转换为Nb 它输出。

7. 发明授权

US07800449B2 Single-ended-to-differential converter with common-mode voltage control 有权
标题翻译：具有共模电压控制的单端到差分转换器
公开(公告)号：US07800449B2
公开(公告)日：2010-09-21
申请号：US11060395
申请日：2005-02-17
申请人： Jan Mulder , Marcel Lugthart , Chi-Hung Lin
发明人： Jan Mulder , Marcel Lugthart , Chi-Hung Lin
IPC分类号： H03F3/04
CPC分类号： H03H11/32
摘要： Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.
摘要翻译：提供了在提供共模电压控制的同时执行单端到差分转换的电路。电路包括将单端信号转换为差分信号的转换器和适于接收差分信号的稳定电路。稳定电路包括被配置为感测差分信号的共模电压电平的传感器和具有耦合到转换器的输出端口的比较器。比较器被配置为将差分信号共模电压电平与参考信号共模电压电平进行比较，并且基于该比较产生调整信号。调整信号经由输出端口被施加到转换器，并且可操作地调整差分信号的后续共模电压电平。

8. 发明申请

US20100186666A1 DEVICE FOR COATING SUBSTRATES DISPOSED ON A SUSCEPTOR 有权
标题翻译：用于涂覆在SUSCEPTOR上的基材的设备
公开(公告)号：US20100186666A1
公开(公告)日：2010-07-29
申请号：US12664648
申请日：2008-06-13
申请人： Johannes Kappeler , Adam Boyd , Victor Saywell , Jan Mulder , Olivier Feron
发明人： Johannes Kappeler , Adam Boyd , Victor Saywell , Jan Mulder , Olivier Feron
IPC分类号： B05C11/00
CPC分类号： C23C16/4586 , C23C16/4583 , C23C16/46 , C30B25/12 , H01L21/68735
摘要： The invention relates to a device for coating substrates having a process chamber (1) disposed in a reactor housing and a two-part, substantially cup-shaped susceptor (2, 3) disposed therein, forming an upper susceptor part (3) with the cup floor thereof having a flat plate (2) and a lower susceptor part (3) with the cup side walls thereof, the outer side (4) of the plate (2) of the upper susceptor part (2) facing upwards toward the process chamber (1) and forming a contact surface for at least one substrate, the upper susceptor part (2) contacting a front edge (3′) of the lower susceptor part (3) at the edge of said upper susceptor part (2), the lower susceptor part (3) being supported by a susceptor carrier (6), and heating zones (A, B, C) for heating the upper susceptor part (2) being disposed below the plate (2′). An advantageous refinement of the invention proposes that the upper susceptor part (2) be removable from the process chamber (1) separately from the lower susceptor part (3), and the joint between the edge of the upper susceptor part (2) and the front edge (3′) of the lower susceptor part (3) be formed as a heat conduction barrier.
摘要翻译：本发明涉及一种用于涂覆基材的装置，其具有设置在反应器壳体中的处理室（1）和设置在反应器壳体中的两部分基本杯形基座（2,3），形成上基座部分（3），其中其底板具有平板（2）和具有杯侧壁的下基座部分（3），上托架部分（2）的板（2）的外侧（4）朝向处理并且形成用于至少一个基板的接触表面，所述上基座部分（2）在所述上基座部分（2）的边缘处接触下基座部分（3）的前边缘（3'），下基座部分（3）由基座托架（6）支撑，加热区（A，B，C）用于加热设置在板（2'）下方的上基座部分（2）。本发明的有益改进提出，上基座部分（2）可以与下基座部分（3）分离地从处理室（1）移除，并且上基座部分（2）的边缘与下感受器部分（3）的前边缘（3'）形成为导热屏障。

9. 发明申请

US20060246860A1 Method and system for a control scheme on power and common-mode voltage reduction for a transmitter 有权
公开(公告)号：US20060246860A1
公开(公告)日：2006-11-02
申请号：US11409277
申请日：2006-04-24
申请人： Yee Cheung , Kevin Chan , Jan Mulder
发明人： Yee Cheung , Kevin Chan , Jan Mulder
IPC分类号： H01Q11/12
CPC分类号： H03F3/45183 , H03F2203/45466
摘要： Provided is a method and system for controlling current characteristics in a transceiver having a transmitter. The method includes identifying a phase control signal from an adjacent current cell preceding the particular current cell in time and logically ORing the phase control signal from the preceding cell with a phase control signal from the particular current cell.

10. 发明申请

US20050162299A1 Reistor ladder interpolation for subranging ADC 有权
标题翻译：电阻梯形图内插，用于辅助ADC
公开(公告)号：US20050162299A1
公开(公告)日：2005-07-28
申请号：US11084236
申请日：2005-03-21
申请人： Jan Mulder
发明人： Jan Mulder
IPC分类号： H03K17/041 , H03M1/06 , H03M1/14 , H03M1/20 , H03M1/36 , H03M1/12
CPC分类号： H03K17/04106 , H03F3/45183 , H03F3/45632 , H03F2203/45352 , H03F2203/45354 , H03F2203/45511 , H03M1/204 , H03M1/365
摘要： An analog to digital converter includes a resistive ladder outputting a plurality of reference voltages and a coarse ADC receiving the reference voltages and a voltage input. A plurality of coarse comparators receive an output of the coarse ADC. A switch matrix receives an output of the coarse ADC and the reference voltages. The switch matrix inputs a plurality of control signals for selecting at least two voltage subranges. A fine ADC receives the two voltage subranges and the voltage input. A plurality of fine comparators receive an output of the fine ADC. An encoder converts outputs of the coarse and fine comparators to a digital representation of the voltage input. The voltage subranges are adjacent. Each control signal includes a plurality of control lines for controlling corresponding switches. The switches are field effect transistors.
摘要翻译：模数转换器包括输出多个参考电压的电阻梯形图和接收参考电压的粗略ADC和电压输入。多个粗略比较器接收粗略ADC的输出。开关矩阵接收粗略ADC的输出和参考电压。开关矩阵输入用于选择至少两个电压子范围的多个控制信号。精密ADC接收两个电压子范围和电压输入。多个精细比较器接收精细ADC的输出。编码器将粗略和精细比较器的输出转换为电压输入的数字表示。电压子范围相邻。每个控制信号包括用于控制相应的开关的多个控制线。开关是场效应晶体管。

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