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1. 发明申请

US20170288567A1 POWER CONVERSION DEVICE 有权
公开(公告)号：US20170288567A1
公开(公告)日：2017-10-05
申请号：US15511289
申请日：2015-08-05
申请人： DAIKIN INDUSTRIES, LTD.
发明人： Yasutaka TAGUCHI , Junya MITSUI , Akira MORIGUCHI
IPC分类号： H02M7/155 , H02M1/12 , H02M1/44 , H02M5/458 , H02M1/32 , G01R19/22 , G06G7/25
CPC分类号： H02M7/1557 , F04B35/04 , F04B39/02 , F04B49/06 , F04B49/103 , F04B49/20 , F04B2203/0201 , F04B2203/0209 , F24F11/89 , F25B1/00 , F25B13/00 , F25B49/022 , F25B2600/021 , F25B2600/0253 , F25B2700/151 , H02M1/12 , H02M1/32 , H02M1/44 , H02M5/458 , H02M7/48 , H02M2001/123 , H02P6/06
摘要： A power converter including a compressor as a load includes a compensation current output (80) allowing compensation current (Ic), which compensates for leakage current (Ia), to flow. A controller (50) receives a detection signal from a rotational speed sensor (55) which senses the rotational speed of the compressor (CM). When the rotational speed has increased to a set rotational speed at which the leakage current (Ia) is lower than or equal to its limiting value (Lmax) (e.g., the limiting value specified under the Electrical Appliances and Materials Safety Act or by the IEC) in a state where the compensation current output (80) is off, the compensation current output (80) is switched from an on state to an off state. This may reduce the leakage current from the compressor with low power loss.

2. 发明申请

US20070222495A2 METHOD AND DEVICE FOR CLOCK SYNCHRONISATION WITH A VESTIGIAL-SIDEBAND-MODULATED TRANSMITTED SIGNAL 有权
标题翻译：用于时域同步传输信号的方法和装置
公开(公告)号：US20070222495A2
公开(公告)日：2007-09-27
申请号：US11302320
申请日：2005-12-13
申请人： Jochen Pliquett , Thomas Reichert
发明人： Jochen Pliquett , Thomas Reichert
IPC分类号： H03D1/24 , G06G7/25
CPC分类号： H04L7/027 , H04L7/007
摘要： A method for clock synchronisation between an amplitude-modulated or phase-modulated received signal (r(t)) and a transmitted signal (s(t)) estimates the timing offset (ε) between the received signal (r(t)) and the transmitted signal (s(t)) by means of a maximum-likelihood method. The maximum-likelihood method in this context is realised by an estimation filtering (S40; S140) dependent upon the transmission characteristic, a subsequent nonlinear signal-processing function (S50; S150) and an averaging filtering (S60, S100; S180, S200) The received signal (r(t)) is especially a modified vestigial-sideband-modulated received signal (rVSB′(t)). The nonlinear signal-processing function (S50; S150) maintains the alternating component in the spectrum of the pre-filtered vestigial-sideband-modulated received signal (vVSB′(t)).
摘要翻译：在幅度调制或相位调制接收信号（r（t））和发送信号（s（t））之间的时钟同步的方法估计接收信号（r（t））和通过最大似然法发射信号（s（t））。在上下文中的最大似然法通过依赖于传输特性的估计滤波（S40; S140），随后的非线性信号处理功能（S50; S150）和平均滤波（S60，S100; S180，S200）来实现，所接收的信号（r（t））特别是经修改的残留边带调制接收信号（r“VSB”（t））。非线性信号处理功能（S50; S150）维持预滤波的残留边带调制接收信号（v> VSB“（t））的频谱中的交替分量。

3. 发明授权

US5631941A Register circuit 失效
标题翻译：寄存器电路
公开(公告)号：US5631941A
公开(公告)日：1997-05-20
申请号：US558418
申请日：1995-11-16
申请人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
IPC分类号： G06F7/49 , G06G7/25 , G11C11/56 , G11C27/00 , G11C27/04 , H03M1/42 , G11C19/00
CPC分类号： H03M1/42 , G06F7/49 , G06G7/25 , G11C11/56 , G11C27/00 , G11C27/04 , G11C19/00 , G11C7/16 , G11C8/04
摘要： A quantized voltage is held by a holding circuit or a feedback circuit connected to a quantizing circuit so that a multi-valued voltage is registered. In another embodiment, outputs of bi-stable circuits with stopwise thresholds are added with weights introduced by a capacitive coupling.
摘要翻译：量化电压由连接到量化电路的保持电路或反馈电路保持，从而登记多值电压。在另一个实施例中，具有逐步阈值的双稳态电路的输出加上由电容耦合引入的权重。

4. 发明授权

US5477171A Full wave rectifier using current mirror bridge 失效
标题翻译：全波整流器采用电流镜桥
公开(公告)号：US5477171A
公开(公告)日：1995-12-19
申请号：US271043
申请日：1994-07-06
申请人： Paolo Menegoli , Mark E. Rohrbaugh
发明人： Paolo Menegoli , Mark E. Rohrbaugh
IPC分类号： G05F3/26 , G01R19/22 , H02M7/21 , H02M7/217 , H03K5/22 , G06G7/25
CPC分类号： G01R19/22 , H02M7/217
摘要： A full wave rectifier includes an amplifier having a minus input, a plus input and an amplifier output; an input resistor connected between a circuit input and the minus input; and a current bridge having an output terminal connected to the circuit output, a first terminal connected to the minus input and a second terminal connected to the amplifier output. The current bridge includes a first current mirror circuit and a second current mirror circuit. The first current mirror circuit includes a first current source and a second current source, a source end of each current source of the first and second current sources being connected to the first terminal, a drain end of the first current source being connected to the second terminal and a drain end of the second current source being connected to the output terminal. The second current mirror circuit includes a third current source and fourth current source, a source end of each current source of the third and fourth current sources being connected to the second terminal, a drain end of the third current source being connected to the first terminal and a drain end of the fourth current source being connected to the output terminal.
摘要翻译：全波整流器包括具有负输入，正输入和放大器输出的放大器; 连接在电路输入和负输入之间的输入电阻; 以及具有连接到电路输出的输出端的电流桥，连接到负输入的第一端和连接到放大器输出的第二端。电流桥包括第一电流镜电路和第二电流镜电路。第一电流镜电路包括第一电流源和第二电流源，第一和第二电流源的每个电流源的源极端连接到第一端子，第一电流源的漏极端连接到第二电流源端子和第二电流源的漏极端连接到输出端子。第二电流镜电路包括第三电流源和第四电流源，第三和第四电流源的每个电流源的源极端连接到第二端子，第三电流源的漏极端连接到第一端子并且第四电流源的漏极端连接到输出端子。

5. 发明授权

US4866300A Detection arrangement for detection of signal variations in a signal 失效
标题翻译：用于检测信号中的信号变化的检测装置
公开(公告)号：US4866300A
公开(公告)日：1989-09-12
申请号：US183203
申请日：1988-04-19
申请人： Hendrik J. J. Bolk , Georges C. P. Zieltjens
发明人： Hendrik J. J. Bolk , Georges C. P. Zieltjens
IPC分类号： H03K5/01 , G06G7/25 , H03K5/08
CPC分类号： H03K5/082 , G06G7/25
摘要： A detection arrangement (1) for detecting variations in a signal has an input (5) to which is supplied a signal that is processed into a reference signal by a signal processing device (2) comprising a threshold circuit (3) followed by a signal hold circuit (6). The reference signal is formed at an output (12) of the signal hold circuit (6). The signal supplied to the input (5) of the detection arrangement and the reference signal formed at the output (12) of the signal hold circuit are supplied to a comparison circuit (9). The signal processing device ensures that the reference signal formed at the output of the signal hold circuit follows peaks and valleys of the signal except for a difference value, the reference signal assuming a threshold value when a peak or a valley is reached. If the signal varies within a range determined by the difference value around the threshold value, the signal hold circuit holds the threshold value. As a result noise influences are eliminated upon detection of peaks and valleys in the signals. The signal processing device comprises means for adjusting the difference value so that it is possible to adapt the apparatus to various signal-to-noise conditions.

6. 发明授权

US4461961A Accurate high speed absolute value circuit and method 失效
标题翻译：精确的高速绝对值电路及方法
公开(公告)号：US4461961A
公开(公告)日：1984-07-24
申请号：US322900
申请日：1981-11-19
申请人： Larry J. Kendall
发明人： Larry J. Kendall
IPC分类号： G01R19/22 , G06G7/25 , H03K5/00
CPC分类号： G06G7/25 , G01R19/22
摘要： The absolute value circuit of the invention comprises differential voltage to current converter means for converting an input voltage of alternating polarity into a pair of currents whose difference represents the input voltage, first and second inverter means for separately inverting each of the two currents, means for connecting the output of each inverter to the input of the other, the inverters being of the type which will only invert current of a predetermined polarity, and current summer and clamp means which are supplied with the outputs of the inverters for generating a unipolar output current signal whose magnitude represents the difference of absolute values of the pair of currents.
摘要翻译：本发明的绝对值电路包括差分电压 - 电流转换器装置，用于将交替极性的输入电压转换为差异代表输入电压的一对电流;第一和第二反相器装置，用于分别反转两个电流中的每一个，将每个逆变器的输出连接到另一个的输入，反相器的类型将仅反转预定极性的电流，以及电流加法器和钳位装置，其被提供有用于产生单极性输出电流的反相器的输出信号，其幅度表示该对电流的绝对值的差。

7. 发明授权

US3832536A Integrator circuit 失效
标题翻译：集成电路
公开(公告)号：US3832536A
公开(公告)日：1974-08-27
申请号：US29278172
申请日：1972-09-27
申请人： CIT ALCATEL
发明人： LE DILY C , LAJOTTE D
IPC分类号： G06G7/18 , G06G7/186 , G06G7/25
CPC分类号： G06G7/18 , G06G7/186 , G06G7/25
摘要： Integrator comprising an operational amplifier having an input (E1)(-) and an input (E2)(+), and an output (S), with a resistance having a value of (R1) connected up between the input (E2) and the earth, a capacitor shunted by a resistor having an ohmic value of (R2) between the output (S) and the ihput (E1), the input voltage being applied to the input (E1) through a resistor having a value of R1), characterized in that the output (S) is connected up to the input (E2) by a network comprising two diodes connected up head to tail in parallel, in series with a resistor having an ohmic value equal to (R2).
摘要翻译：积分器包括具有输入（E1）（ - ）和输入（E2）（+）的运算放大器和输出（S），其中电阻具有连接在输入（E2）和地线，由输出（S）和输出（E1）之间的欧姆值（R2）的电阻器分流的电容器，输入电压通过具有值R1的电阻施加到输入端（E1）其特征在于，输出（S）通过网络连接到输入端（E2），该网络包括并联连接的头二尾二极管，与欧姆值等于（R2）的电阻串联。

8. 发明授权

US3816761A Comparator circuitry 失效
标题翻译：比较器电路
公开(公告)号：US3816761A
公开(公告)日：1974-06-11
申请号：US32063473
申请日：1973-01-02
申请人： RCA CORP
发明人： AHMED A
IPC分类号： G01R19/165 , G06G7/25 , H03K3/2885 , H03K3/2897 , H03K5/08 , H03K5/20 , H03K3/12
CPC分类号： H03K3/2897 , H03K3/2885
摘要： A dead-zone comparator includes first and second component voltage comparators used respectively to compare an input signal to a high reference level and to a low reference level, which reference levels may be programmable. A bistable is set by the output signal of one comparator and reset by the output signal of the other. These SET and RESET signals are opposite polarity currents, one of which is more severely constrained in value than the other, and are applied via a common SET-RESET buss to the bistable.
摘要翻译：死区比较器包括分别用于将输入信号与高参考电平和低参考电平进行比较的第一和第二分量电压比较器，该参考电平可以是可编程的。双稳态由一个比较器的输出信号设置，并由另一个比较器的输出信号复位。这些SET和RESET信号是相反的极性电流，其中一个电流的值比另一个更严格的约束，并通过一个公共的SET-RESET总线施加到双稳态电路。

9. 发明授权

US3768033A Electronic dead band device 失效
标题翻译：电子死皮带设备
公开(公告)号：US3768033A
公开(公告)日：1973-10-23
申请号：US3768033D
申请日：1972-03-17
申请人： GEN ELECTRIC
发明人： LOWE E
IPC分类号： H02P23/00 , G06G7/25 , H02P1/00 , H03G11/00 , H03F3/68
CPC分类号： H03G11/002 , G06G7/25
摘要： An electronic dead band device, which provides for zero output in a dead band region including a negative voltage polarity sensitive circuit, and a positive voltage polarity sensitive circuit, each biased to a dead band level of opposite polarities by biasing circuitry.
摘要翻译：一种电子死区装置，其在包括负电压极性敏感电路的死区区域和正电压极性敏感电路中提供零输出，每个偏置电路通过偏置电路偏置到具有相反极性的死区电平。

10. 发明授权

US3760255A Ac to dc converter circuit 失效
标题翻译：交直流转换器电路
公开(公告)号：US3760255A
公开(公告)日：1973-09-18
申请号：US3760255D
申请日：1972-02-25
申请人： GRODINSKY R
发明人： GRODINSKY R
IPC分类号： G06G7/25 , H03G3/20 , H02M , H03F , H03K
CPC分类号： H03G3/3005 , G06G7/25
摘要： An AC to DC converter for producing a varying DC signal proportional to the amplitude of the varying AC input signal, the converter including a pair of clamping circuits for providing output signals having DC components proportional to the AC amplitude of the AC input signal and AC components following the AC input signal, and where either the DC or the AC signal components of the outputs of the clamping circuits are of opposite sense while the other of same are of the same sense. Means are provided for combining the clamped signals so that the AC signal components are substantially cancelled and the DC signal components are added together.
摘要翻译：一种用于产生与变化的AC输入信号的幅度成比例的变化的DC信号的AC到DC转换器，所述转换器包括一对钳位电路，用于提供具有与AC输入信号的AC振幅成比例的DC分量的输出信号和AC分量遵循AC输入信号，并且其中钳位电路的输出的DC或AC信号分量中的任一个具有相反的意义，而另一个具有相同的意义。提供了用于组合被钳位的信号的装置，使得AC信号分量基本上被消除，并且将DC信号分量相加在一起。

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