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1. 发明授权

US06754755B1 Service request system using an activity indicator to reduce processing overhead 失效
标题翻译：服务请求系统使用活动指示器来减少处理开销
公开(公告)号：US06754755B1
公开(公告)日：2004-06-22
申请号：US09717667
申请日：2000-11-21
申请人： Scott C. Johnson , Rodney S. Canion
发明人： Scott C. Johnson , Rodney S. Canion
IPC分类号： G06F948
CPC分类号： G06F13/24 , G06F13/102
摘要： A service request system for a subsystem of a computer including a processor, a driver, and inhibit logic. The inhibit logic detects requests for service by the subsystem and asserts an interrupt unless the driver is executing and servicing the subsystem. The driver is executed by the processor in response to the interrupt to service the subsystem, where the driver controls the inhibit logic to prevent interrupts associated with the subsystem from being asserted while the driver is being executed by the processor. In this manner, redundant interrupts or service requests initiated by the subsystem are eliminated. The service request system may include an activity indicator that indicates whether the driver is being executed. Th inhibit logic asserts an interrupt in response to a service request from the subsystem unless the activity indicator indicates that the driver is in control of the processor. The subsystem may further detect the activity indicator and inhibit requesting service while the activity indicator indicates that the driver is active. In this manner, the subsystem avoids wasting time associated with requesting service. Also, the subsystem may be operated in a more streamlined mode while the driver is in control of the processor. In one embodiment, the activity indicator is a logic bit, where the driver changes the state of the logic bit upon execution to a first state and changes the state of the logic bit to a second state upon exiting.
摘要翻译：一种用于包括处理器，驱动器和禁止逻辑的计算机的子系统的服务请求系统。禁止逻辑检测子系统的服务请求并断言中断，除非驱动程序正在执行和维护子系统。驱动器由处理器响应于中断来执行以对子系统进行服务，其中驱动器控制禁止逻辑，以防止在处理器执行驱动程序时与子系统相关联的中断被断言。以这种方式，消除了由子系统发起的冗余中断或服务请求。服务请求系统可以包括指示是否正在执行驱动程序的活动指示符。响应于来自子系统的服务请求，禁止逻辑断言中断，除非活动指示符指示驱动程序处于处理器的控制状态。当活动指示符指示驾驶员是活动的时，子系统可以进一步检测活动指示符并禁止请求服务。以这种方式，子系统避免与请求服务相关联的浪费时间。而且，当驱动程序控制处理器时，子系统可以以更加流线型的模式操作。在一个实施例中，活动指示符是逻辑位，其中驱动器在执行时将逻辑位的状态改变到第一状态，并且在退出时将逻辑位的状态改变为第二状态。

2. 发明授权

US06615304B1 Processing unit in which access to system memory is controlled 失效
标题翻译：其中控制对系统存储器的访问的处理单元
公开(公告)号：US06615304B1
公开(公告)日：2003-09-02
申请号：US09603880
申请日：2000-06-26
申请人： Takaharu Ishizuka
发明人： Takaharu Ishizuka
IPC分类号： G06F948
CPC分类号： G06F9/30029 , G06F9/3834 , G06F9/3836 , G06F9/3857
摘要： Has an instruction issuing unit that monitors a change in a memory access sequencing model as well as monitoring a change in an interruption level. When the memory access sequencing model has been changed following a change in the interruption level, the instruction issuing unit restricts the issuing of memory access instructions corresponding to the interruption level after the change until when the execution of all the instructions issued before the change in the interruption level has been finished.
摘要翻译：具有指令发布单元，用于监视存储器访问排序模型的变化以及监视中断级别的变化。当存储器访问顺序模型在中断级别改变之后被改变时，指令发布单元限制在更改之后发出与中断级别相对应的存储器访问指令，直到执行在更改之前发生的所有指令中断级别已经完成。

3. 发明授权

US06449675B1 Multifield register having a selection field for selecting a source of an information field 有权
标题翻译：多域寄存器具有用于选择信息字段源的选择字段
公开(公告)号：US06449675B1
公开(公告)日：2002-09-10
申请号：US09342519
申请日：1999-06-29
申请人： William C. Moyer , Brian D. Branson
发明人： William C. Moyer , Brian D. Branson
IPC分类号： G06F948
CPC分类号： G06F9/4812
摘要： A data processing system (10) has a multifield register (62) which has two fields, a selection field (90) and an information field (91). The selection field (90) identifies the source of the information loaded in the information field (91). In one embodiment, the multifield register (62) is an interrupt flag register (62) and the selection field (90) identifies which of the two registers portions (59,60) of the interrupt pending register (58) is loaded into the multifield register (62). The low register portion (59) can identify up to thirty-one sources of interrupt requests and the high register portion (60) can identify up to thirty-two sources of interrupt requests even though the information field (91) is only thirty-one bits. This is achievable because the selection field (90) may serves a dual function, namely as a flag bit and as bit-32 of the interrupt pending register (58).
摘要翻译：数据处理系统（10）具有具有两个场，选择区（90）和信息区（91）的多域寄存器（62）。选择字段（90）标识加载在信息字段（91）中的信息的来源。在一个实施例中，多路寄存器（62）是中断标志寄存器（62），选择字段（90）识别中断挂起寄存器（58）的两个寄存器部分（59,60）中的哪一个加载到多路寄存器（62）。低寄存器部分（59）可以识别多达三十一个中断请求源，并且高寄存器部分（60）可以识别多达三十二个中断请求源，即使信息字段（91）只有三十一个位。这是可以实现的，因为选择字段（90）可以用作双重功能，即作为标志位和中断挂起寄存器（58）的位32。

4. 发明授权

US06336184B1 Method and apparatus for performing a trap operation in an information handling system 有权
标题翻译：在信息处理系统中执行陷阱操作的方法和装置
公开(公告)号：US06336184B1
公开(公告)日：2002-01-01
申请号：US09134010
申请日：1998-08-14
申请人： Gregory A. Burke , Greg A. Dyck , David E. Lee , Brian B. Moore , Steven J. Repka
发明人： Gregory A. Burke , Greg A. Dyck , David E. Lee , Brian B. Moore , Steven J. Repka
IPC分类号： G06F948
CPC分类号： G06F9/3005 , G06F8/78
摘要： A central processing unit of an information handling system is provided with a Trap instruction to facilitate transfer of control from a user program to a trap program. A dispatchable unit control block (DUCT) of the CPU is loaded with the address of a trap control block, which in turn contains the addresses of a trap save area and a trap program. The user program is provided with Trap instructions at the desired transfer points. Upon decoding a Trap instruction in the user program, the CPU saves state information from the program status word (PSW), general registers and access registers in the designated trap save area, loads the address of the trap control block into a general register, and copies the address of the trap program into the instruction address field of the PSW to transfer control to the trap program. Upon completion of execution, the trap program may issue a Resume Program (RP) instruction to restore the previously saved state information to return control to the user program.
摘要翻译：信息处理系统的中央处理单元设置有Trap指令，以便于将控制从用户程序传送到陷阱程序。 CPU的可调度单元控制块（DUCT）装载有陷阱控制块的地址，该地址又包含陷阱保存区域的地址和陷阱程序。用户程序在所需的传输点提供陷阱指令。在解码用户程序中的Trap指令时，CPU从指定的陷阱保存区中的程序状态字（PSW），通用寄存器和访问寄存器中保存状态信息，将陷阱控制块的地址加载到通用寄存器中，将陷阱程序的地址复制到PSW的指令地址字段中，以将控制传输到陷阱程序。完成执行后，陷阱程序可以发出恢复程序（RP）指令以恢复先前保存的状态信息，以将控制权返回给用户程序。

5. 发明授权

US06189061B1 Multi-master bus system performing atomic transactions and method of operating same 有权
标题翻译：执行原子事务的多主总线系统及其操作方法
公开(公告)号：US06189061B1
公开(公告)日：2001-02-13
申请号：US09241161
申请日：1999-02-01
申请人： Itai Katz , Moti Kurnick , Noam Halevi , Vladislav Kopzon
发明人： Itai Katz , Moti Kurnick , Noam Halevi , Vladislav Kopzon
IPC分类号： G06F948
CPC分类号： G06F13/362 , G06F13/18
摘要： A multi-master bus system (10) comprises bus (12), a plurality of bus devices (14, 16, 18, 20, 22, 24), coupled to the bus, including masters (14, 16, 18), and slaves (20, 22, 24), a memory controller (26) for controlling the data exchange on bus (12), having a memory (36) for storing a transaction type value with respect to each slave (20, 22, 24). The multi-master bus system (10) comprises further an arbiter (30) for performing bus arbitration, arbiter (30) having logic for conditionally subsequently granting the bus (12) to a master of an initiating transaction for a closing transaction depending on the transaction type value of the slave of the initiating transaction. The multi-master bus system makes atomic or indivisible transactions possible on a bus without changing the bus width or the bus protocol.
摘要翻译：多主总线系统（10）包括总线（12），耦合到总线的多个总线装置（14,16,18,20,22,24），包括主机（14,16,18）和从机（20,22,24），用于控制总线（12）上的数据交换的存储器控制器（26），具有用于存储关于每个从机（20,22,24）的交易类型值的存储器（36）。多主总线系统（10）还包括用于执行总线仲裁的仲裁器（30），仲裁器（30）具有逻辑，用于有条件地随后将总线（12）授予终止事务的主机，取决于关闭事务启动事务的从属事务类型值。多主总线系统可以在总线上实现原子或不可分割的交易，而无需更改总线宽度或总线协议。

6. 发明授权

US06820155B1 Interruption managing device and interruption managing method 失效
标题翻译：中断管理设备和中断管理方法
公开(公告)号：US06820155B1
公开(公告)日：2004-11-16
申请号：US09890940
申请日：2001-08-07
申请人： Hiroyuki Ito
发明人： Hiroyuki Ito
IPC分类号： G06F948
CPC分类号： G06F9/4812 , G06F9/4843 , G06F13/24
摘要： An interrupt management section 103 for holding interrupt acceptance possibility states prepared for each of interrupt sources 121 to 122, and an interrupt mask cancellation section 104 for controlling interrupt enabling in interrupt processing tasks 127, are provided, and a multiple interruption control section 109 is provided for performing interrupt mask update control using sections 103 and 104 within an interrupt handler 101.
摘要翻译：提供了用于保持为每个中断源121至122准备的中断接受可能性状态的中断管理部分103和用于控制中断处理任务127中的中断使能的中断屏蔽消除部分104，并且提供多个中断控制部分109 用于使用中断处理程序101内的部分103和104执行中断屏蔽更新控制。

7. 发明授权

US06779065B2 Mechanism for interrupt handling in computer systems that support concurrent execution of multiple threads 有权
标题翻译：支持并发执行多个线程的计算机系统中的中断处理机制
公开(公告)号：US06779065B2
公开(公告)日：2004-08-17
申请号：US09945419
申请日：2001-08-31
申请人： Keshav Murty , Scott Bobholz
发明人： Keshav Murty , Scott Bobholz
IPC分类号： G06F948
CPC分类号： G06F9/4812 , G06F9/4843
摘要： The present invention provides a mechanism for handling interrupts on a processor that supports multiple-threads concurrently. The processor's resources are allocated to provide multiple logical processors. In response to a common interrupt, the logical processors vie for access to a shared register. The first logical processor to access the shared register handles the common interrupt. The remaining logical processors return from the interrupt.
摘要翻译：本发明提供了一种用于处理同时支持多线程的处理器上的中断的机制。处理器的资源被分配以提供多个逻辑处理器。响应于一个共同的中断，逻辑处理器可以访问共享寄存器。访问共享寄存器的第一个逻辑处理器处理公共中断。剩余的逻辑处理器从中断返回。

8. 发明授权

US06701015B2 Character string extraction apparatus and method based on basic component in document image 失效
标题翻译：基于文档图像中基本组件的字符串提取装置和方法
公开(公告)号：US06701015B2
公开(公告)日：2004-03-02
申请号：US09960978
申请日：2001-09-25
申请人： Katsuhito Fujimoto , Hiroshi Kamada
发明人： Katsuhito Fujimoto , Hiroshi Kamada
IPC分类号： G06F948
CPC分类号： G06K9/00463
摘要： A character string extraction apparatus extracts an aggregate of basic components from a document image, such as a binary image, gray scale image, color image, etc., and judges whether each basic component is a character component using an inclusion relationship between the basic components. Then, the character string extraction apparatus extracts an aggregate of character components based on the judgment result and extracts a character string from the aggregate of character components.
摘要翻译：字符串提取装置从诸如二进制图像，灰度图像，彩色图像等的文档图像中提取基本组分的聚合，并且使用基本组件之间的包含关系来判断每个基本组件是否是字符组件。然后，字符串提取装置基于判断结果提取字符分量的聚合，并从字符分量的集合中提取字符串。

9. 发明授权

US06453412B1 Method and apparatus for reissuing paired MMX instructions singly during exception handling 有权
标题翻译：在异常处理期间单独重新发布成对的MMX指令的方法和装置
公开(公告)号：US06453412B1
公开(公告)日：2002-09-17
申请号：US09357703
申请日：1999-07-20
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F948
CPC分类号： G06F9/3853 , G06F9/3861
摘要： In a computer having a single execution pipeline, the invention provides a method for executing paired MMX-type instructions. The method includes executing two MMX-type instructions as paired MMX instructions. If execution of the paired MMX instructions causes an exception, pairing of instructions is disabled, and the two MMX-type instructions are re-executed in sequential fashion. Paired execution is re-enabled following re-execution of the two MMX-type instructions.
摘要翻译：在具有单个执行流水线的计算机中，本发明提供了一种用于执行成对的MMX型指令的方法。该方法包括执行两个MMX类型的指令作为成对的MMX指令。如果配对的MMX指令的执行导致异常，则禁止配对指令，并且以连续的方式重新执行两个MMX型指令。在重新执行两个MMX类型的指令后，重新启用配对执行。

10. 发明授权

US06401155B1 Interrupt/software-controlled thread processing 失效
标题翻译：中断/软件控制的线程处理
公开(公告)号：US06401155B1
公开(公告)日：2002-06-04
申请号：US09273938
申请日：1999-03-22
申请人： Winthrop L. Saville , Kevin Ross
发明人： Winthrop L. Saville , Kevin Ross
IPC分类号： G06F948
CPC分类号： G06F9/462 , G06F9/30123
摘要： Rapid thread processing is achieved by transferring complete thread contexts between a memory and a context register set. Each thread context is read from a respective memory location in response to either a designated interrupt or an instruction.
摘要翻译：通过在存储器和上下文寄存器集之间传送完整的线程上下文来实现快速线程处理。响应于指定的中断或指令，从相应的存储器位置读取每个线程上下文。

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