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1. 发明授权

US09274795B2 Conditional non-branch instruction prediction 有权
标题翻译：条件非分支指令预测
公开(公告)号：US09274795B2
公开(公告)日：2016-03-01
申请号：US13413258
申请日：2012-03-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
IPC分类号： G06F9/30
CPC分类号： G06F9/30174 , G06F9/30076 , G06F9/30112 , G06F9/3017 , G06F9/30189 , G06F9/30196
摘要： A microprocessor processes conditional non-branch instructions that specify a condition and instruct the microprocessor to perform an operation if the condition is satisfied and otherwise to not perform the operation. A predictor provides a prediction about a conditional non-branch instruction. An instruction translator translates the conditional non-branch instruction into a no-operation microinstruction when the prediction predicts the condition will not be satisfied, and into a set of one or more microinstructions to unconditionally perform the operation when the prediction predicts the condition will be satisfied. An execution pipeline executes the no-operation microinstruction or the set of microinstructions. The predictor translates into a second set of one or more microinstructions to conditionally perform the operation when the prediction does not make a prediction. In the case of a misprediction, the translator re-translates the conditional non-branch instruction into the second set of microinstructions.
摘要翻译：微处理器处理指定条件的条件非分支指令，并指示微处理器在条件满足的情况下执行操作，否则不执行操作。预测器提供关于条件非分支指令的预测。当预测预测条件不满足时，指令翻译器将条件非分支指令转换为无操作微指令，并且当预测预测条件将被满足时，指令转换为一组或多个微指令以无条件地执行操作。执行流水线执行无操作微指令或微指令集。当预测不进行预测时，预测器转换成第二组一个或多个微指令以有条件地执行操作。在错误预测的情况下，翻译者将条件非分支指令重新翻译成第二组微指令。

2. 发明授权

US09146742B2 Heterogeneous ISA microprocessor that preserves non-ISA-specific configuration state when reset to different ISA 有权
标题翻译：异构ISA微处理器在复位到不同的ISA时保留非ISA特定的配置状态
公开(公告)号：US09146742B2
公开(公告)日：2015-09-29
申请号：US13412914
申请日：2012-03-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
IPC分类号： G06F9/48 , G06F9/50 , G06F9/54 , G06F9/30 , G06F9/38 , G06F9/46
CPC分类号： G06F9/30174 , G06F9/3017 , G06F9/30181 , G06F9/30189 , G06F9/3844 , G06F9/461
摘要： A microprocessor capable of operating as both an x86 ISA and an ARM ISA microprocessor includes first, second, and third storage that stores x86 ISA-specific, ARM ISA-specific, and non-ISA-specific state, respectively. When reset, the microprocessor initializes the first storage to default values specified by the x86 ISA, initializes the second storage to default values specified by the ARM ISA, initializes the third storage to predetermined values, and begins fetching instructions of a first ISA. The first ISA is the x86 ISA or the ARM ISA and a second ISA is the other ISA. The microprocessor updates the third storage in response to the first ISA instructions. In response to a subsequent one of the first ISA instructions that instructs the microprocessor to reset to the second ISA, the microprocessor refrains from modifying the non-ISA-specific state stored in the third storage and begins fetching instructions of the second ISA.
摘要翻译：能够同时运行x86 ISA和ARM ISA微处理器的微处理器分别包含第一，第二和第三存储，它们分别存储特定于x86 ISA特定的ISA特定状态和非ISA特定状态。当复位时，微处理器将第一个存储器初始化为由x86 ISA指定的默认值，将第二个存储初始化为由ARM ISA指定的默认值，将第三个存储初始化为预定值，并开始获取第一个ISA的指令。第一个ISA是x86 ISA或ARM ISA，另一个ISA是另一个ISA。微处理器响应于第一ISA指令更新第三存储器。响应于指示微处理器重置到第二ISA的第一ISA指令中的随后的一个，微处理器不修改存储在第三存储器中的非ISA特定状态，并开始获取第二ISA的指令。

3. 发明授权

US09128701B2 Generating constant for microinstructions from modified immediate field during instruction translation 有权
标题翻译：在指导翻译过程中，从修改的立即场产生微指令的常数
公开(公告)号：US09128701B2
公开(公告)日：2015-09-08
申请号：US13416879
申请日：2012-03-09
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30167 , G06F9/30072 , G06F9/30094 , G06F9/30112 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/30196 , G06F9/3806
摘要： An ISA-defined instruction includes an immediate field having a first and second portions specifying first and second values, which instructs the microprocessor to perform an operation using a constant value as one of its source operands. The constant value is the first value rotated/shifted by a number of bits based on the second value. An instruction translator translates the instruction into one or more microinstructions. An execution pipeline executes the microinstructions generated by the instruction translator. The instruction translator, rather than the execution pipeline, generates the constant value for the execution pipeline as a source operand of at least one of the microinstructions for execution by the execution pipeline. Alternatively, if the immediate field value is not within a predetermined subset of values known by the instruction translator, the instruction translator generates, rather than the constant, a second microinstruction for execution by the execution pipeline to generate the constant.
摘要翻译： ISA定义的指令包括具有指定第一和第二值的第一和第二部分的立即字段，其指示微处理器使用常数值作为其源操作数之一执行操作。常数值是基于第二值旋转/移位多个位的第一值。指令翻译器将指令转换为一个或多个微指令。执行流水线执行指令转换器生成的微指令。指令转换器而不是执行流水线，将执行流水线的常量值作为执行流水线执行的至少一个微指令的源操作数。或者，如果立即字段值不在指令转换器已知的值的预定子集内，则指令转换器生成第二微指令而不是常数，用于由执行流水线执行以产生常数。

4. 发明授权

US09032189B2 Efficient conditional ALU instruction in read-port limited register file microprocessor 有权
标题翻译：读端口限制寄存器文件微处理器中有效的条件ALU指令
公开(公告)号：US09032189B2
公开(公告)日：2015-05-12
申请号：US13333520
申请日：2011-12-21
申请人： G. Glenn Henry , Gerard M. Col , Rodney E. Hooker , Terry Parks
发明人： G. Glenn Henry , Gerard M. Col , Rodney E. Hooker , Terry Parks
IPC分类号： G06F9/30
CPC分类号： G06F9/30189 , G06F9/30072 , G06F9/30094 , G06F9/30141 , G06F9/30174
摘要： A microprocessor having performs an architectural instruction that instructs it to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if its architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result. To execute the second microinstruction, it writes the destination register with the result generated by the first microinstruction if the architectural condition flags satisfy the condition, and writes the destination register with the current value of the destination register if the architectural condition flags do not satisfy the condition.
摘要翻译：一种微处理器，其执行结构指令，指示其在第一和第二源操作数上执行操作以产生结果，并且仅当其结构条件标志满足建筑指令中指定的条件时才将结果写入目的寄存器。硬件指令转换器将指令转换为第一和第二微指令。要执行第一个微指令，执行流水线对源操作数执行操作以生成结果。要执行第二个微指令，如果架构条件标志满足条件，则将目标寄存器写入由第一微指令生成的结果，如果结构条件标志不满足条件标志，则将目标寄存器写入目标寄存器的当前值条件。

5. 发明授权

US08924695B2 Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor 有权
标题翻译：条件ALU指令条件满足在读端口限制寄存器文件微处理器中的微指令之间的传播
公开(公告)号：US08924695B2
公开(公告)日：2014-12-30
申请号：US13333631
申请日：2011-12-21
申请人： G. Glenn Henry , Gerard M. Col , Rodney E. Hooker , Terry Parks
发明人： G. Glenn Henry , Gerard M. Col , Rodney E. Hooker , Terry Parks
IPC分类号： G06F9/30
CPC分类号： G06F9/30189 , G06F9/30072 , G06F9/30123 , G06F9/30174
摘要： An architectural instruction instructs a microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the architectural instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result, determines whether the architectural condition flags satisfy the condition, and updates a non-architectural indicator to indicate whether the architectural condition flags satisfy the condition. To execute the first microinstruction, if the non-architectural indicator updated by the first microinstruction indicates the architectural condition flags satisfy the condition, it updates the destination register with the result; otherwise, it updates the destination register with the current value of the destination register.
摘要翻译：架构指令指示微处理器对第一和第二源操作数执行操作以产生结果，并且只有在体系结构条件标志满足建筑指令中指定的条件时才将结果写入目的寄存器。硬件指令翻译器将架构指令转换为第一和第二微指令。为了执行第一微指令，执行流水线对源操作数执行操作以生成结果，确定架构条件标志是否满足条件，并更新非架构指示符以指示架构条件标志是否满足条件。为了执行第一微指令，如果由第一微指令更新的非架构指示符指示架构条件标志满足条件，则用结果更新目的寄存器; 否则，它将使用目标寄存器的当前值更新目标寄存器。

6. 发明授权

US08880857B2 Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor 有权
标题翻译：条件ALU指令在读端口限制寄存器文件微处理器中的微指令之前进行移位生成的进位标志传播
公开(公告)号：US08880857B2
公开(公告)日：2014-11-04
申请号：US13333572
申请日：2011-12-21
申请人： G. Glenn Henry , Gerard M. Col , Rodney E. Hooker , Terry Parks
发明人： G. Glenn Henry , Gerard M. Col , Rodney E. Hooker , Terry Parks
IPC分类号： G06F9/30
CPC分类号： G06F9/30189 , G06F9/30094 , G06F9/30174
摘要： A microprocessor includes a hardware instruction translator that translates an architectural instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the shift operation on the first source operand to generate the first result and a carry flag value and updates a non-architectural carry flag with the generated carry flag value. To execute the second microinstruction, it performs the second operation on the first result and the second operand to generate the second result and new condition flag values based on the second result. If a architectural condition flags satisfy the condition, it updates the architectural carry flag with the non-architectural carry flag value and updates at least one of the other architectural condition flags with the corresponding generated new condition flag values; otherwise, it updates the architectural condition flags with the current value of the architectural condition flags.
摘要翻译：微处理器包括将架构指令转换成第一和第二微指令的硬件指令转换器。为了执行第一微指令，执行流水线对第一源操作数执行移位操作以产生第一结果和进位标志值，并且利用所生成的进位标志值更新非架构进位标志。为了执行第二微指令，它对第一结果和第二操作数执行第二操作，以基于第二结果产生第二结果和新条件标志值。如果架构条件标志满足条件，则使用非架构进位标志值来更新架构进位标志，并用对应的生成的新条件标志值来更新其他架构状态标志中的至少一个; 否则，它使用架构条件标志的当前值更新架构条件标志。

7. 发明授权

US08880851B2 Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline 有权
标题翻译：通过硬件转换执行X86 ISA和arm ISA机器语言程序指令的微处理器由通用执行管道执行的微指令
公开(公告)号：US08880851B2
公开(公告)日：2014-11-04
申请号：US13224310
申请日：2011-09-01
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
IPC分类号： G06F9/30 , G06F9/26
CPC分类号： G06F9/441 , G06F9/265 , G06F9/30043 , G06F9/30072 , G06F9/30076 , G06F9/30105 , G06F9/30123 , G06F9/30145 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/30196 , G06F9/3802 , G06F9/4401 , G06F9/4403 , G06F15/82
摘要： A microprocessor includes a hardware instruction translator that translates x86 ISA and ARM ISA machine language program instructions into microinstructions, which are encoded in a distinct manner from the x86 and ARM instructions. An execution pipeline executes the microinstructions to generate x86/ARM-defined results. The microinstructions are distinct from the results generated by the execution of the microinstructions by the execution pipeline. The translator directly provides the microinstructions to the execution pipeline for execution. Each time the microprocessor performs one of the x86 ISA and ARM ISA instructions, the translator translates it into the microinstructions. An indicator indicates either x86 or ARM as a boot ISA. After reset, the microprocessor initializes its architectural state, fetches its first instructions from a reset address, and translates them all as defined by the boot ISA. An instruction cache caches the x86 and ARM instructions and provides them to the translator.
摘要翻译：微处理器包括硬件指令转换器，将x86 ISA和ARM ISA机器语言程序指令转换为微指令，它们以不同于x86和ARM指令的方式进行编码。执行流水线执行微指令以生成x86 / ARM定义的结果。微指令与由执行管道执行微指令生成的结果不同。翻译器直接向执行管道提供微指令以供执行。每当微处理器执行x86 ISA和ARM ISA指令之一时，翻译器将其转换为微指令。指示符指示x86或ARM作为引导ISA。复位后，微处理器初始化其架构状态，从复位地址获取其第一条指令，并按照引导ISA定义将其全部转换。指令缓存缓存x86和ARM指令，并将其提供给翻译器。

8. 发明授权

US08838924B2 Microprocessor having internal secure memory 有权
标题翻译：微处理器具有内部安全存储器
公开(公告)号：US08838924B2
公开(公告)日：2014-09-16
申请号：US12263143
申请日：2008-10-31
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F12/00 , G06F21/72 , G06F21/70
CPC分类号： G06F21/72 , G06F12/1408 , G06F21/12 , G06F21/14 , G06F21/554 , G06F21/70 , G06F21/71 , G06F21/73 , G06F21/74 , G06F21/75 , G06F21/82
摘要： An apparatus providing for a secure execution environment. The apparatus includes a microprocessor that is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus. The microprocessor has a non-secure memory and a secure volatile memory. The non-secure memory is configured to store portions of the non-secure application programs for execution by the microprocessor, where the non-secure memory is observable and accessible by the non-secure application programs and by system bus resources within the microprocessor. The secure volatile memory is configured to store the secure application program for execution by the microprocessor, where the secure volatile memory is isolated from the non-secure application programs and the system bus resources within the microprocessor. The secure application program is decrypted using a processor unique key and is written to the secure volatile memory.
摘要翻译：一种提供安全执行环境的设备。该装置包括被配置为执行非安全应用程序和安全应用程序的微处理器，其中通过系统总线从系统存储器访问非安全应用程序。微处理器具有非安全存储器和安全易失性存储器。非安全存储器被配置为存储用于由微处理器执行的非安全应用程序的部分，其中非安全存储器是可观察的并且可由非安全应用程序和微处理器内的系统总线资源访问。安全易失性存储器被配置为存储用于由微处理器执行的安全应用程序，其中安全易失性存储器与非安全应用程序和微处理器内的系统总线资源隔离。安全应用程序使用处理器唯一密钥解密，并被写入安全易失性存储器。

9. 发明授权

US08671285B2 Microprocessor that fetches and decrypts encrypted instructions in same time as plain text instructions 有权
标题翻译：微处理器在纯文本指令的同时提取和解密加密的指令
公开(公告)号：US08671285B2
公开(公告)日：2014-03-11
申请号：US13091487
申请日：2011-04-21
申请人： G. Glenn Henry , Terry Parks , Brent Bean , Thomas A. Crispin
发明人： G. Glenn Henry , Terry Parks , Brent Bean , Thomas A. Crispin
IPC分类号： G06F21/00
CPC分类号： H04L9/0827 , G06F9/30003 , G06F9/30079 , G06F9/30178 , G06F9/30189 , G06F12/0875 , G06F21/52 , G06F21/54 , G06F21/602 , G06F21/71 , G06F21/72 , G06F2212/402 , G06F2212/452 , G06F2221/2107 , H04L9/0618 , H04L9/0861 , H04L9/0891 , H04L9/0894 , H04L2209/12 , H04L2209/20
摘要： A fetch unit (a) fetches a block of instruction data from an instruction cache of the microprocessor; (b) performs an XOR on the block with a data entity to generate plain text instruction data; and (c) provides the plain text instruction data to an instruction decode unit. In a first instance the block comprises encrypted instruction data and the data entity is a decryption key. In a second instance the block comprises unencrypted instruction data and the data entity is Boolean zeroes. The time required to perform (a), (b), and (c) is the same in the first and second instances regardless of whether the block is encrypted or unencrypted. A decryption key generator selects first and second keys from a plurality of keys, rotates the first key, and adds/subtracts the rotated first key to/from the second key, all based on portions of the fetch address, to generate the decryption key.
摘要翻译：提取单元（a）从微处理器的指令高速缓冲存储器获取指令数据块; （b）使用数据实体在块上执行异或以产生明文指令数据; 和（c）将明文指令数据提供给指令译码单元。在第一种情况下，块包括加密指令数据，数据实体是解密密钥。在第二种情况下，该块包括未加密的指令数据，并且数据实体为布尔零。执行（a），（b）和（c）所需的时间在第一和第二实例中是相同的，而不管该块是加密还是未加密。解密密钥生成器从多个密钥中选择第一和第二密钥，旋转第一密钥，并且基于获取地址的部分，将旋转后的第一密钥加到/从第二密钥中加减乘以产生解密密钥。

10. 发明授权

US08635476B2 Decentralized power management distributed among multiple processor cores 有权
标题翻译：分散式电源管理分布在多个处理器内核之间
公开(公告)号：US08635476B2
公开(公告)日：2014-01-21
申请号：US13299122
申请日：2011-11-17
申请人： G. Glenn Henry , Darius D. Gaskins
发明人： G. Glenn Henry , Darius D. Gaskins
IPC分类号： G06F1/32
CPC分类号： G06F1/3206 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3253 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/151 , Y02D10/22
摘要： A multi-core processor provides a configurable resource shared by two or more cores, wherein configurations of the resource affect the power, speed, or efficiency with which the cores sharing the resource are able to operate. Internal core power state management logic configures each core to participate in a de-centralized inter-core power state discovery process to discover a composite target power state for the shared resource that is a most restrictive or power-conserving state that will not interfere with any of the corresponding target power states of each core sharing the resource. The internal core power state management logic determines whether the core is a master core authorized to configure the resource, and if so, configures that resource in the discovered composite power state. The de-centralized power state discovery process is carried out between the cores on sideband, non-system bus wires, without the assistance of centralized non-core logic.
摘要翻译：多核处理器提供由两个或多个核共享的可配置资源，其中该资源的配置影响共享该资源的核能够运行的功率，速度或效率。内部核心电源状态管理逻辑配置每个内核参与一个非集中式的核心间电源状态发现过程，以发现一个最不受干扰任何限制或功率节省状态的共享资源的复合目标电源状态的每个核心共享资源的相应目标电源状态。内部核心电源状态管理逻辑确定核心是否是授权配置资源的主核心，如果是，则在发现的组合电源状态下配置该资源。集中式电源状态发现过程在边带核心之间，非系统总线线路上进行，无需集中式非核心逻辑。

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