专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08499125B2 Control device for snoop tag 失效
标题翻译：窥探标签控制装置
公开(公告)号：US08499125B2
公开(公告)日：2013-07-30
申请号：US11790272
申请日：2007-04-24
申请人： Makoto Hataida , Toshikazu Ueki , Takaharu Ishizuka , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Makoto Hataida , Toshikazu Ueki , Takaharu Ishizuka , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0822 , G06F12/123
摘要： To prevent a decrease in performance of controlling a snoop tag. A queue is stored with REPLACE target WAY information and an index as an entry associated with a REPLACE request received from a processor, the index stored in the queue is compared with an index of a subsequent READ request, and, as a result of the comparison, a process based on the index-coincident READ request is executed with respect to the snoop tag corresponding to a content of a cache memory of the processor. Further, the REPLACE target WAY information of the READ request is replaced with the WAY information in the index-coincident entry within the queue.
摘要翻译：以防止控制snoop标签的性能下降。存储REPLACE目标WAY信息和索引作为与从处理器接收到的REPLACE请求相关联的条目的队列，将存储在队列中的索引与后续READ请求的索引进行比较，并且作为比较的结果相对于与处理器的高速缓冲存储器的内容相对应的窥探标签，执行基于索引一致的READ请求的处理。此外，READ请求的REPLACE目标WAY信息被队列中符合条件的条目中的WAY信息所替代。

2. 发明申请

US20120236843A1 INFORMATION PROCESSING APPARATUS AND METHOD OF SWITCHING SETTINGS THEREOF 审中-公开
标题翻译：信息处理装置及其切换方法
公开(公告)号：US20120236843A1
公开(公告)日：2012-09-20
申请号：US13424828
申请日：2012-03-20
申请人： Atsushi Morosawa , Takaharu Ishizuka , Takeshi Owaki , Susumu Akiu
发明人： Atsushi Morosawa , Takaharu Ishizuka , Takeshi Owaki , Susumu Akiu
IPC分类号： H04L12/28
CPC分类号： H04L45/42 , H04L45/02 , H04L45/06 , H04L49/101
摘要： A method of switching internal settings in an information processing apparatus including a plurality of processors, a crossbar switch connected to the plurality of processors and having a first routing table and a second routing table used for routing between the plurality of processors and an external apparatus, and a management unit managing the plurality of processors. The method includes performing, by the processors, data communication with the external apparatus using the first routing table, updating, by the management unit, configuration information in the second routing table when a configuration of the information processing apparatus is changed, instructing, by the management unit, any one of the processors to switch the updated second routing table and the first routing table, and switching, by the processor instructed by the management unit, a routing table to be used for the data communication from the first routing table to the updated second routing table.
摘要翻译：一种在包括多个处理器的信息处理设备中切换内部设置的方法，连接到所述多个处理器的交叉开关并具有用于在所述多个处理器之间路由的第一路由表和第二路由表以及外部设备，以及管理所述多个处理器的管理单元。该方法包括由处理器使用第一路由表与外部设备进行数据通信，当信息处理设备的配置改变时，由管理单元更新第二路由表中的配置信息，指示由管理单元，用于切换更新的第二路由表和第一路由表的处理器中的任一个，以及由管理单元指示的处理器切换要用于从第一路由表到第一路由表的数据通信的路由表更新了第二个路由表。

3. 发明授权

US07783840B2 Method and apparatus for controlling memory system 有权
标题翻译：用于控制存储器系统的方法和装置
公开(公告)号：US07783840B2
公开(公告)日：2010-08-24
申请号：US10999972
申请日：2004-12-01
申请人： Makoto Hataida , Takao Matsui , Daisuke Itoh , Seishi Okada , Takaharu Ishizuka
发明人： Makoto Hataida , Takao Matsui , Daisuke Itoh , Seishi Okada , Takaharu Ishizuka
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0833 , G06F12/0811 , G06F12/0817 , G06F2212/507
摘要： A cache-status maintaining unit stores address information of data stored in each entry of a cache memory, and maintains a status of each entry as any one of “strongly modified”, “weakly modified”, “shared”, and “Invalid”. A data-fetching-procedure selecting unit selects, upon receiving a data read request, at least one data fetching procedure based on the address information and the status. A read-data delivering unit selects latest data from among the data fetched, and delivers the latest data to a processor that issued the data read request. A cache-status updating unit updates, when registering the address information of the data, updates the status of the entry based on a type of the data read request.
摘要翻译：高速缓存状态维持单元存储存储在高速缓冲存储器的每个条目中的数据的地址信息，并将每个条目的状态保持为“强修改”，“弱修改”，“共享”和“无效”中的任何一个。数据获取过程选择单元在接收到数据读取请求时，基于地址信息和状态来选择至少一个数据获取过程。读取数据传送单元从获取的数据中选择最新数据，并将最新数据传送到发出数据读取请求的处理器。缓存状态更新单元在注册数据的地址信息时根据数据读取请求的类型来更新条目的状态。

4. 发明授权

US06615304B1 Processing unit in which access to system memory is controlled 失效
标题翻译：其中控制对系统存储器的访问的处理单元
公开(公告)号：US06615304B1
公开(公告)日：2003-09-02
申请号：US09603880
申请日：2000-06-26
申请人： Takaharu Ishizuka
发明人： Takaharu Ishizuka
IPC分类号： G06F948
CPC分类号： G06F9/30029 , G06F9/3834 , G06F9/3836 , G06F9/3857
摘要： Has an instruction issuing unit that monitors a change in a memory access sequencing model as well as monitoring a change in an interruption level. When the memory access sequencing model has been changed following a change in the interruption level, the instruction issuing unit restricts the issuing of memory access instructions corresponding to the interruption level after the change until when the execution of all the instructions issued before the change in the interruption level has been finished.
摘要翻译：具有指令发布单元，用于监视存储器访问排序模型的变化以及监视中断级别的变化。当存储器访问顺序模型在中断级别改变之后被改变时，指令发布单元限制在更改之后发出与中断级别相对应的存储器访问指令，直到执行在更改之前发生的所有指令中断级别已经完成。

5. 发明申请

US20100191942A1 Information processor and control method 失效
标题翻译：信息处理器和控制方法
公开(公告)号：US20100191942A1
公开(公告)日：2010-07-29
申请号：US12659896
申请日：2010-03-24
申请人： Takeshi Owaki , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Atsushi Morosawa , Takashi Yamamoto , Daisuke Itou
发明人： Takeshi Owaki , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Atsushi Morosawa , Takashi Yamamoto , Daisuke Itou
IPC分类号： G06F9/30
CPC分类号： G06F11/1658 , G06F11/165 , G06F11/1679 , G06F2201/81
摘要： A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in an FWH instructs the northbridge to inhibit an external instruction. In addition, the firmware save the inside information of a normal CPU connected to a normal CPU bus and cache data on a memory and the northbridge issues reset to all CPUs in the home system board. The firmware then restores the inside information of the CPU save on the memory to the all CPUs and instructs the northbridge to cancel the inhibition of the external instruction.
摘要翻译：北桥在检测到冗余CPU的同步中断时，停止发生错误的异常CPU总线的运行，FWH中的固件指示北桥禁止外部指令。此外，固件还保存连接到普通CPU总线的正常CPU的内部信息，并将存储器上的数据缓存，并将北桥问题重置到家庭系统板中的所有CPU。然后，固件将CPU的内部信息恢复到所有CPU的存储器上，并指示北桥取消对外部指令的禁止。

6. 发明申请

US20080046695A1 System controller, identical-address-request-queuing preventing method, and information processing apparatus having identical-address-request-queuing preventing function 有权
标题翻译：系统控制器，相同地址请求排队防止方法和具有相同地址请求排队防止功能的信息处理装置
公开(公告)号：US20080046695A1
公开(公告)日：2008-02-21
申请号：US11790266
申请日：2007-04-24
申请人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F9/30 , G06F12/00
CPC分类号： G06F13/1642
摘要： In a system controller including a CPU-issued request queue having a circuit that processes plural requests having identical addresses not to be inputted to the CPU-issued request queue, a latest request other than a cache replace request is retained by an input-request retaining section. Consequently, even if an address of an issued request for cache replace request matches an address of a request retained by the CPU-issued request queue, the issued request for the cache replace request is not retried but is queued in the CPU-issued request queue when the address of the issued request for the cache replace request does not match the entire address retained by the input-request retaining section.
摘要翻译：在包括CPU发出的请求队列的系统控制器中，具有处理具有相同地址的多个请求的电路不被输入到CPU发出的请求队列，除了高速缓存替换请求以外的最新请求被保留部分。因此，即使发出的请求高速缓存替换请求的地址与CPU发出的请求队列所保留的请求的地址相匹配，也不会重新发出对高速缓存替换请求的发出请求，而是在CPU发出的请求队列中排队当发出的缓存替换请求的地址与输入请求保留部分保留的整个地址不匹配时。

7. 发明申请

US20080046663A1 System controller, snoop tag modification method and information processing apparatus having snoop tag modificaton function 有权
标题翻译：系统控制器，snoop标签修改方法和具有snoop标签修改功能的信息处理设备
公开(公告)号：US20080046663A1
公开(公告)日：2008-02-21
申请号：US11790263
申请日：2007-04-24
申请人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F12/08
CPC分类号： G06F12/0822 , G06F12/0831
摘要： In a multiprocessor system, a system controller includes snoop tags which are copy information on cache tags retained by respective CPUs. If the same address is registered in S (Shared state) in the cache tag of each of the CPUs connected to the same CPU bus, the address is registered in S (Shared state) in only any one of the snoop tags corresponding to the CPUs in which the same address is registered.
摘要翻译：在多处理器系统中，系统控制器包括窥探标签，这些标签是由各个CPU保留的缓存标签上的复制信息。如果在连接到同一CPU总线的每个CPU的缓存标签中的S（共享状态）中登记相同的地址，则只在与CPU对应的任何一个snoop标签中的S（共享状态）中注册该地址其中注册了相同的地址。

8. 发明申请

US20060212656A1 Dual storage apparatus and control method for the dual storage apparatus 有权
标题翻译：双存储设备的双存储设备和控制方法
公开(公告)号：US20060212656A1
公开(公告)日：2006-09-21
申请号：US11237934
申请日：2005-09-29
申请人： Toshikazu Ueki , Takaharu Ishizuka , Takao Matsui , Makoto Hataida , Yuka Hosokawa
发明人： Toshikazu Ueki , Takaharu Ishizuka , Takao Matsui , Makoto Hataida , Yuka Hosokawa
IPC分类号： G06F12/00
CPC分类号： G06F11/1008 , G06F11/1666 , G06F11/20 , G11C5/005
摘要： A dual storage apparatus is provided that comprises a first and a second memories for respectively retaining a set of identical data and a selector for selecting either of the two (2) sets of the data respectively read from the first and the second memory based on a read control signal inputted into the selector, having a request management unit for, when the read control signal has been inputted, attaching an identifier for identifying the read control signal to the inputted read control signal and outputting the signal and the identifier; and a plurality of memory control units for each of the first and the second memories. The dual storage apparatus detects a synchronization error by verifying coincidence of the identifier attached by the request management unit and controls the selector such that the data from a system from which no synchronization error has been detected.
摘要翻译：提供了一种双存储装置，其包括用于分别保存一组相同数据的第一和第二存储器，以及用于选择从第一和第二存储器分别读取的两（2）组数据中的任何一个基于读取控制信号输入到选择器中，具有请求管理单元，当输入了读取控制信号时，将用于识别读取控制信号的标识符附加到所输入的读取控制信号并输出该信号和标识符; 以及用于第一和第二存储器中的每一个的多个存储器控制单元。双存储装置通过验证由请求管理单元附加的标识符的一致性来检测同步错误，并且控制选择器使得来自未检测到同步错误的系统的数据。

9. 发明申请

US20110320885A1 TRANSMISSION/RECEPTION DEVICE, TRANSMISSION DEVICE, RECEPTION DEVICE, AND DATA TRANSMISSION/RECEPTION METHOD 失效
标题翻译：传输/接收设备，传输设备，接收设备和数据传输/接收方法
公开(公告)号：US20110320885A1
公开(公告)日：2011-12-29
申请号：US13224995
申请日：2011-09-02
申请人： Takeshi OWAKI , Takaharu Ishizuka , Susumu Akiu , Atsushi Morosawa
发明人： Takeshi OWAKI , Takaharu Ishizuka , Susumu Akiu , Atsushi Morosawa
IPC分类号： G06F11/00 , G06F13/00
CPC分类号： G06F11/277
摘要： A transmission/reception device includes a transmission device that divides a plurality of connection lines into a plurality of groups, determines corresponding connection lines in the plurality of groups, determines a correspondence between test pattern and the connection line, and outputs the test pattern to the plurality of connection lines based on the correspondence between the test pattern and the connection line, and a reception device that receives the test pattern from the transmission device, compares bits in a same position of the test pattern received through a corresponding connection line in the plurality of groups based on the correspondence between the test pattern and the connection line, and generates erroneous connection line information indicating an erroneous connection line as a connection line in which an error has occurred in the plurality of connection lines based on a result of the comparison.
摘要翻译：发送/接收装置包括：将多条连接线划分为多个组的发送装置，确定多个组中的对应连接线，确定测试模式与连接线的对应关系，并将测试模式输出到基于测试图案和连接线之间的对应关系的多个连接线以及从发送装置接收测试图案的接收装置比较通过多个对应连接线接收的测试图案的相同位置中的比特基于测试图案和连接线之间的对应关系，并且基于比较结果，生成指示错误连接线的错误连接线信息作为连接线，其中已经在多条连接线中发生错误。

10. 发明授权

US08078920B2 Information processing device and error processing method 失效
标题翻译：信息处理装置和误差处理方法
公开(公告)号：US08078920B2
公开(公告)日：2011-12-13
申请号：US12554318
申请日：2009-09-04
申请人： Atsushi Morosawa , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Takeshi Owaki , Takashi Yamamoto , Daisuke Itou
发明人： Atsushi Morosawa , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Takeshi Owaki , Takashi Yamamoto , Daisuke Itou
IPC分类号： G06F11/00
CPC分类号： G06F11/1658 , G06F11/1641 , G06F11/165 , G06F11/1687
摘要： An information processing device having two processing units capable of operating in synchronization with each other, includes: a common unit capable of outputting an identical signal to the two processing units; detection units that are respectively provided for the processing units and each detects errors occurred in corresponding processing unit respectively; a comparison unit that compares outputs from the two processing units; and a control unit that controls signals from the processing units to the common unit, based on a detection result of the detection units and a comparison result of the comparison unit, and determines, if errors of an identical type are simultaneously detected by the detection units, that the errors are due to an error of the common unit.
摘要翻译：具有能够彼此同步操作的两个处理单元的信息处理装置包括：能够向两个处理单元输出相同信号的公共单元; 分别提供给处理单元的检测单元，并分别检测相应处理单元中发生的错误; 比较来自两个处理单元的输出的比较单元; 以及控制单元，其基于检测单元的检测结果和比较单元的比较结果来控制从处理单元到公共单元的信号，并且如果检测单元同时检测到相同类型的错误，则确定，错误是由于公共单元的错误。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式