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1. 发明授权

US06829730B2 Method of designing circuit having multiple test access ports, circuit produced thereby and method of using same 有权
标题翻译：设计具有多个测试接入端口的电路的方法，由此产生的电路及其使用方法
公开(公告)号：US06829730B2
公开(公告)日：2004-12-07
申请号：US09843307
申请日：2001-04-27
申请人： Benoit Nadeau-Dostie , Jean-François Côté
发明人： Benoit Nadeau-Dostie , Jean-François Côté
IPC分类号： G06F1127
CPC分类号： G01R31/318563 , G01R31/318555
摘要： In a circuit with multiple Test Access Port (TAP) interfaces, the TAPs are arranged into groups, with secondary TAPs in one or more groups and a master TAP in another group, the master TAP having an instruction register with bits for storing a group selection code; a Test Data Output (TDO) circuit responsive to the group selection code connects the group TDO of one of the groups to the circuit TDO; and, for each secondary TAP group, a group Test Data Input (TDI) circuit responsive to a shift state signal for selectively connecting the group TDI to the circuit TDI or to the output of a padding register having its input connected to the circuit TDI, and its output connected to an input of the group TDI circuit; and a group TMS circuit responsive to a predetermined TAP selection code associated with the group for producing a group TMS signal for each TAP in the group.
摘要翻译：在具有多个测试访问端口（TAP）接口的电路中，TAP被分成组，其中一个或多个组中的辅助TAP和另一个组中的主TAP，主TAP具有指令寄存器，其中存储组选择码; 响应于组选择代码的测试数据输出（TDO）电路将组中的一组的组TDO连接到电路TDO; 并且对于每个次级TAP组，响应于用于选择性地将组TDI连接到电路TDI或其输入连接到电路TDI的填充寄存器的输出的移位状态信号的组测试数据输入（TDI）电路，其输出连接到组TDI电路的输入端; 以及组TMS电路，其响应于与该组相关联的预定TAP选择代码，用于为该组中的每个TAP产生组TMS信号。

2. 发明授权

US06550031B1 Transparently gathering a chips multiple internal states via scan path and a trigger 有权
标题翻译：通过扫描路径和触发器透明地收集多个内部状态的芯片
公开(公告)号：US06550031B1
公开(公告)日：2003-04-15
申请号：US09413119
申请日：1999-10-06
申请人： Gary M. Godfrey , Floyd Goodrich, III
发明人： Gary M. Godfrey , Floyd Goodrich, III
IPC分类号： G06F1127
CPC分类号： G06F11/27 , G01R31/3177 , G01R31/318533
摘要： A microcontroller has many miscellaneous logics. The miscellaneous logic can include input/outputs of combinational logic or peripheral devices of the microcontroller, storage devices such as latches, or registers. The miscellaneous logic is coupled to multiple stages of scan cells. The multiple stages can be used as a buffer while the last stage of scan cells are scanned out. A predetermined stage of scan cells are coupled together to form a scan path where data from the miscellaneous logic can be outputted to an external memory. In one embodiment, the predetermined stage is the last stage of scan cells. A trigger signal is used to shift the data from the miscellaneous logic to the next stage of scan cells. Once the last stage of scan cells are loaded, a clocking signal can be provided so that the data in the predetermined stage of scan cells is scanned out. The present invention provides among other things, a graceful way to capture data from miscellaneous logic of the microcontroller using scan hardware.
摘要翻译：微控制器具有许多杂项逻辑。该杂项逻辑可以包括微控制器的组合逻辑或外围设备的输入/输出，诸如锁存器或寄存器的存储设备。杂项逻辑耦合到多个扫描单元级。扫描单元的最后一个阶段可以将多个阶段用作缓冲区。扫描单元的预定阶段被耦合在一起以形成扫描路径，其中来自该杂项逻辑的数据可被输出到外部存储器。在一个实施例中，预定阶段是扫描单元的最后阶段。触发信号用于将数据从杂逻辑移位到扫描单元的下一级。一旦扫描单元的最后阶段被加载，就可以提供时钟信号，以便扫描单元的预定级的数据被扫描出来。本发明尤其提供了使用扫描硬件从微控制器的各种逻辑中捕获数据的优雅方式。

3. 发明授权

US06789160B2 Multi-threaded random access storage device qualification tool 有权
标题翻译：多线程随机存取设备鉴定工具
公开(公告)号：US06789160B2
公开(公告)日：2004-09-07
申请号：US09824929
申请日：2001-04-03
申请人： Tanjore K. Suresh
发明人： Tanjore K. Suresh
IPC分类号： G06F1127
CPC分类号： G06F11/2289 , G06F3/0601 , G06F2003/0697
摘要： A method for qualifying random access storage devices is disclosed which includes determining qualification parameters for each of the random access storage devices, determining a configuration for each of the random access storage devices, and qualifying each of the random access storage devices based on the determined qualification parameters and configuration. A tool for qualifying random access storage devices is disclosed which includes a parser for determining qualification parameters, a machine configuration collector for determining random access storage device configuration, and a thread spawner for qualifying each of the random access storage devices based on the determined qualification parameters and configuration.
摘要翻译：公开了一种用于限定随机存取存储设备的方法，其包括确定每个随机存取存储设备的资格参数，确定每个随机存取存储设备的配置，以及基于所确定的资格参数和配置。公开了一种用于限定随机存取存储设备的工具，其包括用于确定限定参数的解析器，用于确定随机存取存储设备配置的机器配置收集器，以及用于基于所确定的限定参数来限定每个随机存取存储设备的线程选择器和配置。

4. 发明授权

US06691242B1 SYSTEM TEST AND METHOD FOR CHECKING PROCESSOR OVER-CLOCKING BY RETRIEVING AN ASSIGNED SPEED FROM AN REGISTER INTERNAL TO THE PROCESSOR, COMPARING WITH RUNNING SPEED, AND DISPLAYING CAUTION MESSAGE TO USER 失效
标题翻译：通过从处理器内部向处理器检索指定的速度，与运行速度进行比较，以及向用户显示小心信息来检查处理器过时的系统测试和方法
公开(公告)号：US06691242B1
公开(公告)日：2004-02-10
申请号：US09585860
申请日：2000-06-01
申请人： Steven L. Pollock , Ted T. Honma
发明人： Steven L. Pollock , Ted T. Honma
IPC分类号： G06F1127
CPC分类号： G06F11/2284
摘要： The present invention is designed to test whether a Central Processing Unit (CPU) in a computer system is being overclocked. That is, being run at a speed higher than its rated or assigned speed. An important feature of the present invention is that it is internal to the computer system on which it operates. That is, the test of the present invention is implemented in the computer system's Basic Input/Output System or as microcode stored directly on the CPU. The end user need not resort to any external means such as a floppy or CD disk to test the CPU included in his/her computer system. If the CPU is not overclocked, the test runs invisible to the end user. If, on the other hand, the CPU is overclocked, the test allows the user to either continue with the normal boot up process or exit the boot up process to adjust the running speed to substantially match the assigned speed of the CPU.
摘要翻译：本发明旨在测试计算机系统中的中央处理单元（CPU）是否超频。也就是说，以高于其额定值或分配速度的速度运行。本发明的一个重要特征是它在其运行的计算机系统的内部。也就是说，本发明的测试在计算机系统的基本输入/输出系统中实现，或者直接存储在CPU上。最终用户不需要使用任何外部手段，例如软盘或CD盘来测试他/她的计算机系统中包含的CPU。如果CPU没有超频，则测试对最终用户不可见。另一方面，如果CPU超频，则测试允许用户继续正常启动过程或退出引导过程，以调整运行速度以与CPU的分配速度基本匹配。

5. 发明授权

US06496947B1 Built-in self repair circuit with pause for data retention coverage 有权
标题翻译：内置自修复电路，暂停数据保留
公开(公告)号：US06496947B1
公开(公告)日：2002-12-17
申请号：US09426034
申请日：1999-10-25
申请人： William D. Schwarz
发明人： William D. Schwarz
IPC分类号： G06F1127
CPC分类号： G11C29/12015 , G11C11/41 , G11C29/14 , G11C29/46 , G11C29/50016 , G11C29/70
摘要： A single-chip integrated circuit includes a memory array, a built-in self test circuit and a pause circuit. The built-in self test circuit is coupled to the memory array and is adapted to execute a sequence of write and read operations on the memory array. The pause circuit is coupled to and activated by the built-in self test circuit. When activated, the pause circuit pauses the sequence of write and read operations for a pause time period.
摘要翻译：单片集成电路包括存储器阵列，内置自检电路和暂停电路。内置自检电路耦合到存储器阵列，并且适于在存储器阵列上执行写入和读取操作的序列。暂停电路通过内置自检电路耦合并激活。当激活时，暂停电路在暂停时间段内暂停写入和读取操作的顺序。

6. 发明授权

US06691252B2 Cache test sequence for single-ported row repair CAM 失效
标题翻译：单端口行修复CAM的缓存测试序列
公开(公告)号：US06691252B2
公开(公告)日：2004-02-10
申请号：US09792476
申请日：2001-02-23
申请人： Brian William Hughes , Warren Kurt Howlett
发明人： Brian William Hughes , Warren Kurt Howlett
IPC分类号： G06F1127
CPC分类号： G11C29/72 , G11C15/00 , G11C29/12
摘要： The present invention incorporates built-in self test and self repair functionality into a semiconductor memory device in which reconfiguration data used to replace faulty memory is stored at the same time testing to identify other faulty memory cells continues. To avoid access contention conflicts to a content addressable memory used to identify rows or groups of rows having faulty memory cells, the built in test function writes test data to each cell at least twice before reading the stored data. By writing twice before reading, contention problems caused by simultaneous updating of the content addressable memory are avoided. That is, even if the content addressable memory is initially unavailable to process address information used to access a memory cell to be tested, repetition of the write process ensure that the data will be properly stored when the memory again becomes available after being updated.
摘要翻译：本发明将内置的自检和自修复功能集成到半导体存储器件中，其中用于替换故障存储器的重新配置数据被同时存储在测试中以识别其他故障存储器单元继续。为了避免将访问冲突与用于识别具有故障存储单元的行或组的行的内容可寻址存储器进行访问冲突，内置测试功能在读取存储的数据之前至少将测试数据写入每个单元格至少两次。在阅读之前两次写入，避免了同时更新内容可寻址存储器引起的争用问题。也就是说，即使内容可寻址存储器最初不可用于处理用于访问待测试的存储器单元的地址信息，所以写入过程的重复确保当存储器在更新之后再次变得可用时，数据将被适当地存储。

7. 发明授权

US06539338B1 Self-diagnostic testing of a network interface adapter 失效
标题翻译：网络接口适配器的自诊断测试
公开(公告)号：US06539338B1
公开(公告)日：2003-03-25
申请号：US09591045
申请日：2000-06-09
申请人： Heidi R. Pickreign , Laxminarayan Krishnamurthy , Christopher J. Duguay
发明人： Heidi R. Pickreign , Laxminarayan Krishnamurthy , Christopher J. Duguay
IPC分类号： G06F1127
CPC分类号： G06F11/27
摘要： A method and apparatus for implementing a self-diagnostic capability in a network interface adapter in which failure data is provided to a host processor. The host processor may report the failure data to a user or additionally the host processor may attempt to correct predetermined faults in code images by writing a valid code image to a memory on the network interface adapter.
摘要翻译：一种在网络接口适配器中实现自诊断能力的方法和装置，其中故障数据被提供给主机处理器。主处理器可以向用户报告故障数据，或者另外主机处理器可以尝试通过向网络接口适配器上的存储器写入有效的代码图像来修正代码图像中的预定故障。

8. 发明授权

US06421789B1 Synchronous semiconductor memory device capable of reducing test cost and method of testing the same 失效
标题翻译：能够降低测试成本的同步半导体存储器件及其测试方法
公开(公告)号：US06421789B1
公开(公告)日：2002-07-16
申请号：US09333649
申请日：1999-06-16
申请人： Tsukasa Ooishi
发明人： Tsukasa Ooishi
IPC分类号： G06F1127
CPC分类号： G11C29/14 , G11C29/12015
摘要： A match detection circuit detecting match of data outputted to a plurality of data terminals is provided on an input/output circuit part. In a test, the same result is written in two latches, and alternately read in response to a clock signal. From a terminal outputting data at a double data rate in general, therefore, a test result can be outputted at a lower data rate. Observation is enabled with a tester having low performance, for reducing the cost for the test.
摘要翻译：检测输出到多个数据端子的数据的匹配的匹配检测电路被提供在输入/输出电路部分上。在测试中，相同的结果写入两个锁存器，并且响应于时钟信号交替地读取。因此，从通常以双重数据速率输出数据的终端，可以以较低的数据速率输出测试结果。使用具有低性能的测试仪进行观察，以降低测试成本。

9. 发明授权

US06178524B1 Information processing system hardware test 失效
标题翻译：信息处理系统硬件测试
公开(公告)号：US06178524B1
公开(公告)日：2001-01-23
申请号：US09070832
申请日：1998-04-30
申请人： James Leigh Taylor
发明人： James Leigh Taylor
IPC分类号： G06F1127
CPC分类号： G06F11/2284 , G06F11/2273
摘要： An information processing system includes a plurality of different hardware component types (e.g. interface chip, chip port and chip port DMA channel hardware). The chip may include for example two chip ports, each of which includes twelve DMA channels. The system further includes software for controlling the operation of the hardware, the software providing a software class for each hardware type. Each software class defines a constructor for creating instances of each class, one instance for each member of the type e.g. twelve instances of the chip port DMA class. The constructor further includes or references test code for testing each type member. Thus, on construction of each instance of the chip port DMA class, the associated constructor tests the operation of the DMA channel. If there is a failure, the constructor throws an exception to the chip port constructor which then determines how to handle the error.
摘要翻译：信息处理系统包括多种不同的硬件组件类型（例如，接口芯片，芯片端口和芯片端口DMA通道硬件）。芯片可以包括例如两个芯片端口，每个芯片端口包括十二个DMA通道。该系统还包括用于控制硬件操作的软件，软件为每种硬件类型提供软件类。每个软件类定义一个构造器，用于创建每个类的实例，每个类型的每个成员的一个实例。十二个实例的芯片端口DMA类。构造函数还包括或引用测试每个类型成员的测试代码。因此，在构建芯片端口DMA类的每个实例时，相关联的构造器测试DMA通道的操作。如果出现故障，构造函数会向芯片端口构造函数引发异常，然后确定如何处理该错误。

10. 发明授权

US06665817B1 Apparatus and method for implementing a wireless system-on-a-chip with a reprogrammable tester, debugger, and bus monitor 有权
标题翻译：用可重复编程的测试仪，调试器和总线监视器来实现无线片上系统的装置和方法
公开(公告)号：US06665817B1
公开(公告)日：2003-12-16
申请号：US09565688
申请日：2000-05-05
申请人： Keith Rieken
发明人： Keith Rieken
IPC分类号： G06F1127
CPC分类号： G01R31/3187 , G01R31/31705 , G01R31/318533 , G01R31/318555 , H04W24/00
摘要： A wireless communication system-on-a-chip comprises a system bus, a set of fixed function processors connected to the system bus, an embedded processor connected to the system bus, and reconfigurable logic connected to the system bus. The reconfigurable logic supports an operational mode and a diagnostic mode. In the operational mode, the system operates to support different air interface protocols and data rates. In the diagnostic mode, the system alternately tests the system, debugs the system, and monitors bus activity within the system.
摘要翻译：无线通信系统芯片包括系统总线，连接到系统总线的一组固定功能处理器，连接到系统总线的嵌入式处理器以及连接到系统总线的可重新配置的逻辑。可重构逻辑支持操作模式和诊断模式。在操作模式下，系统支持不同的空中接口协议和数据速率。在诊断模式下，系统交替测试系统，调试系统，并监控系统内的总线活动。

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