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1. 发明授权

US08076979B2 Lock detection circuit for phase locked loop 有权
标题翻译：锁相环锁定检测电路
公开(公告)号：US08076979B2
公开(公告)日：2011-12-13
申请号：US12416933
申请日：2009-04-02
申请人： Manan Kathuria , Kumar Abhishek , Suhas Chakravarty , Suri Roopak
发明人： Manan Kathuria , Kumar Abhishek , Suhas Chakravarty , Suri Roopak
IPC分类号： H03J7/04 , H03L7/02
CPC分类号： H03L7/095 , Y10S331/02
摘要： A lock detector circuit for detecting a lock condition between a reference signal and a feedback signal includes a first counter for outputting a first counter value indicative of a number of clock cycles of the reference signal, and a second counter for outputting a second counter value indicative of a number of clock cycles of the feedback signal. An asynchronous comparator receives the first and second counter values and provides an output signal having a pulse width that is proportional to the difference between the first and second counter values. A pulse width detector receives the comparator output signal and produces an output signal that is indicative of the relationship between the pulse width of the comparator output signal and a predetermined threshold value. A state machine controls the state of at least one lock indication signal according to the pulse width detector output signal.
摘要翻译：用于检测参考信号和反馈信号之间的锁定状态的锁定检测器电路包括用于输出指示参考信号的时钟周期数的第一计数器值的第一计数器和用于输出指示的第二计数器值的第二计数器的反馈信号的多个时钟周期。异步比较器接收第一和第二计数器值，并提供具有与第一和第二计数器值之间的差成比例的脉冲宽度的输出信号。脉冲宽度检测器接收比较器输出信号并产生指示比较器输出信号的脉冲宽度与预定阈值之间的关系的输出信号。状态机根据脉冲宽度检测器输出信号控制至少一个锁定指示信号的状态。

2. 发明申请

US20090251226A1 LOCK DETECTION CIRCUIT FOR PHASE LOCKED LOOP 有权
标题翻译：锁相环锁定检测电路
公开(公告)号：US20090251226A1
公开(公告)日：2009-10-08
申请号：US12416933
申请日：2009-04-02
申请人： Manan Kathuria , Kumar Abhishek , Suhas Chakravarty , Suri Roopak
发明人： Manan Kathuria , Kumar Abhishek , Suhas Chakravarty , Suri Roopak
IPC分类号： H03L7/095
CPC分类号： H03L7/095 , Y10S331/02
摘要： A lock detector circuit for detecting a lock condition between a reference signal and a feedback signal includes a first counter for outputting a first counter value indicative of a number of clock cycles of the reference signal, and a second counter for outputting a second counter value indicative of a number of clock cycles of the feedback signal. An asynchronous comparator receives the first and second counter values and provides an output signal having a pulse width that is proportional to the difference between the first and second counter values. A pulse width detector receives the comparator output signal and produces an output signal that is indicative of the relationship between the pulse width of the comparator output signal and a predetermined threshold value. A state machine controls the state of at least one lock indication signal according to the pulse width detector output signal.
摘要翻译：用于检测参考信号和反馈信号之间的锁定状态的锁定检测器电路包括用于输出指示参考信号的时钟周期数的第一计数器值的第一计数器和用于输出指示的第二计数器值的第二计数器的反馈信号的多个时钟周期。异步比较器接收第一和第二计数器值，并提供具有与第一和第二计数器值之间的差成比例的脉冲宽度的输出信号。脉冲宽度检测器接收比较器输出信号并产生指示比较器输出信号的脉冲宽度与预定阈值之间的关系的输出信号。状态机根据脉冲宽度检测器输出信号控制至少一个锁定指示信号的状态。

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