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1. 发明申请

US20100124894A1 Phase-Lock Loop 有权
标题翻译：锁相环
公开(公告)号：US20100124894A1
公开(公告)日：2010-05-20
申请号：US12272152
申请日：2008-11-17
申请人： Chin Yeong Koh , Kar Ming Yong
发明人： Chin Yeong Koh , Kar Ming Yong
IPC分类号： H04B1/06
CPC分类号： H03L7/095 , H03L7/0995 , H03L7/113 , H03L7/18 , Y10S331/02
摘要： A phase-lock loop having a reduced lock time in comparison with the conventional art. The phase-lock loop compares an output signal thereof with a reference signal, and alters a control signal in response thereto such that the output signal may have a desired frequency.
摘要翻译：与常规技术相比，锁相环具有减少的锁定时间。锁相环路将其输出信号与参考信号进行比较，并响应于此而改变控制信号，使得输出信号可以具有期望的频率。

2. 发明授权

US07298191B2 Reset-free delay-locked loop 有权
标题翻译：无复位延迟锁定环路
公开(公告)号：US07298191B2
公开(公告)日：2007-11-20
申请号：US11353790
申请日：2006-02-14
申请人： Hai Jie Wu , Kiat How Tan , Chin Yeong Koh
发明人： Hai Jie Wu , Kiat How Tan , Chin Yeong Koh
IPC分类号： H03L7/06
CPC分类号： H03L7/0891 , H03L7/0812 , H03L7/10 , H03L2207/14
摘要： A delay locked loop (DLL) includes a delay unit configured to delay an input clock signal by a specified amount to produce a delayed clock signal. A phase detector receives as input the input clock signal and the delayed clock signal and outputs a signal proportional to the phase difference between the input clock signal and the delayed clock signal to provide a control voltage for adjusting the delay to the specified amount. A pulse swallower removes a pulse from the input clock signal or from the delayed clock signal to reverse the direction of the control signal.
摘要翻译：延迟锁定环（DLL）包括被配置为将输入时钟信号延迟指定量以产生延迟的时钟信号的延迟单元。相位检测器接收输入时钟信号和延迟的时钟信号作为输入，并输出与输入时钟信号和延迟的时钟信号之间的相位差成比例的信号，以提供用于将延迟调整到指定量的控制电压。脉冲吞吐器从输入时钟信号或延迟的时钟信号中去除脉冲以反转控制信号的方向。

3. 发明申请

US20060132205A1 Reset-free delay-locked loop 有权
标题翻译：无复位延迟锁定环路
公开(公告)号：US20060132205A1
公开(公告)日：2006-06-22
申请号：US11353790
申请日：2006-02-14
申请人： Hai Jie Wu , Kiat How Tan , Chin Yeong Koh
发明人： Hai Jie Wu , Kiat How Tan , Chin Yeong Koh
IPC分类号： H03L7/06
CPC分类号： H03L7/0891 , H03L7/0812 , H03L7/10 , H03L2207/14
摘要： A delay locked loop (DLL) includes a delay unit configured to delay an input clock signal by a specified amount to produce a delayed clock signal. A phase detector receives as input the input clock signal and the delayed clock signal and outputs a signal proportional to the phase difference between the input clock signal and the delayed clock signal to provide a control voltage for adjusting the delay to the specified amount. A pulse swallower removes a pulse from the input clock signal or from the delayed clock signal to reverse the direction of the control signal.
摘要翻译：延迟锁定环（DLL）包括被配置为将输入时钟信号延迟指定量以产生延迟的时钟信号的延迟单元。相位检测器接收输入时钟信号和延迟的时钟信号作为输入，并输出与输入时钟信号和延迟的时钟信号之间的相位差成比例的信号，以提供用于将延迟调整到指定量的控制电压。脉冲吞吐器从输入时钟信号或延迟的时钟信号中去除脉冲以反转控制信号的方向。

4. 发明授权

US08704563B2 Phase-lock loop 有权
标题翻译：锁相环路
公开(公告)号：US08704563B2
公开(公告)日：2014-04-22
申请号：US13347586
申请日：2012-01-10
申请人： Chin Yeong Koh , Kar Ming Yong
发明人： Chin Yeong Koh , Kar Ming Yong
IPC分类号： H03L7/087
CPC分类号： H03L7/095 , H03L7/0995 , H03L7/113 , H03L7/18 , Y10S331/02
摘要： In one implementation an output signal of an oscillator is varied to be within a desired frequency band with respect to a reference signal, the output signal having a plurality of phases. The implementation may include comparing the output signal with the reference signal, counting falling edges about each phase of the number of phases in a predetermined time period and summing to define a count output; comparing the count output with a product of the number of phases of the output signal and the factor to define a comparison, generating a control signal based upon the comparison, and inputting the control signal to the oscillator to alter the output signal thereof.
摘要翻译：在一个实现中，振荡器的输出信号相对于参考信号变化在期望的频带内，输出信号具有多个相位。该实现可以包括将输出信号与参考信号进行比较，对在预定时间段内的相位数的每个相位的下降沿进行计数，并且相加以定义计数输出; 将计数输出与输出信号的相位数和因子的乘积进行比较以定义比较，基于比较生成控制信号，并将控制信号输入到振荡器以改变其输出信号。

5. 发明授权

US08258880B2 Ring oscillator for providing constant oscillation frequency 有权
标题翻译：环形振荡器，用于提供恒定的振荡频率
公开(公告)号：US08258880B2
公开(公告)日：2012-09-04
申请号：US12713326
申请日：2010-02-26
申请人： Chin Yeong Koh , Kar Ming Yong
发明人： Chin Yeong Koh , Kar Ming Yong
IPC分类号： H03L7/099 , H03L1/00
CPC分类号： H03K3/0322 , H03K3/011 , H03K2005/00032 , H03L7/0995
摘要： Some embodiments disclosed herein relate to techniques for providing a relatively constant oscillation frequency. In some instances, these techniques can make use of a ring oscillator that is powered by an adaptive voltage supply. The adaptive voltage supply provides a temperature-dependent supply voltage to respective delay elements in the ring oscillator, such that the oscillation frequency of the ring oscillator is approximately constant over a predetermined temperature range. For example, if temperature increases, the supply voltage can be increased proportionally, thereby tending to limit variation in the oscillation frequency delivered by the ring oscillator.
摘要翻译：本文公开的一些实施例涉及用于提供相对恒定的振荡频率的技术。在某些情况下，这些技术可以利用由自适应电压源供电的环形振荡器。自适应电压电源为环形振荡器中的相应延迟元件提供与温度相关的电源电压，使得环形振荡器的振荡频率在预定温度范围内近似恒定。例如，如果温度升高，则电源电压可以成比例地增加，从而倾向于限制由环形振荡器传递的振荡频率的变化。

6. 发明申请

US20120105117A1 Phase-Lock Loop 有权
标题翻译：锁相环
公开(公告)号：US20120105117A1
公开(公告)日：2012-05-03
申请号：US13347586
申请日：2012-01-10
申请人： Chin Yeong Koh , Kar Ming Yong
发明人： Chin Yeong Koh , Kar Ming Yong
IPC分类号： H03L7/06
CPC分类号： H03L7/095 , H03L7/0995 , H03L7/113 , H03L7/18 , Y10S331/02
摘要： A phase-lock loop having a reduced lock time in comparison with the conventional art. The phase-lock loop compares an output signal thereof with a reference signal, and alters a control signal in response thereto such that the output signal may have a desired frequency.
摘要翻译：与常规技术相比，锁相环具有减少的锁定时间。锁相环路将其输出信号与参考信号进行比较，并响应于此而改变控制信号，使得输出信号可以具有期望的频率。

7. 发明授权

US08095102B2 Phase-lock loop 有权
标题翻译：锁相环路
公开(公告)号：US08095102B2
公开(公告)日：2012-01-10
申请号：US12272152
申请日：2008-11-17
申请人： Chin Yeong Koh , Kar Ming Yong
发明人： Chin Yeong Koh , Kar Ming Yong
IPC分类号： H03L7/087 , H03L7/085
CPC分类号： H03L7/095 , H03L7/0995 , H03L7/113 , H03L7/18 , Y10S331/02
摘要： In one implementation an output signal of an oscillator is varied to be within a desired frequency band with respect to a reference signal, the output signal having a plurality of phases. The implementation may include comparing the output signal with the reference signal, counting falling edges about each phase of the number of phases in a predetermined time period and summing to define a count output; comparing the count output with a product of the number of phases of the output signal and the factor to define a comparison, generating a control signal based upon the comparison, and inputting the control signal to the oscillator to alter the output signal thereof.
摘要翻译：在一个实现中，振荡器的输出信号相对于参考信号变化在期望的频带内，输出信号具有多个相位。该实现可以包括将输出信号与参考信号进行比较，对在预定时间段内的相位数的每个相位的下降沿进行计数，并且相加以定义计数输出; 将计数输出与输出信号的相位数和因子的乘积进行比较以定义比较，基于比较生成控制信号，并将控制信号输入到振荡器以改变其输出信号。

8. 发明申请

US20110210798A1 Ring Oscillator for Providing Constant Oscillation Frequency 有权
标题翻译：振荡器提供恒定振荡频率
公开(公告)号：US20110210798A1
公开(公告)日：2011-09-01
申请号：US12713326
申请日：2010-02-26
申请人： Chin Yeong Koh , Kar Ming Yong
发明人： Chin Yeong Koh , Kar Ming Yong
IPC分类号： H03K3/03
CPC分类号： H03K3/0322 , H03K3/011 , H03K2005/00032 , H03L7/0995
摘要： Some embodiments disclosed herein relate to techniques for providing a relatively constant oscillation frequency. In some instances, these techniques can make use of a ring oscillator that is powered by an adaptive voltage supply. The adaptive voltage supply provides a temperature-dependent supply voltage to respective delay elements in the ring oscillator, such that the oscillation frequency of the ring oscillator is approximately constant over a predetermined temperature range. For example, if temperature increases, the supply voltage can be increased proportionally, thereby tending to limit variation in the oscillation frequency delivered by the ring oscillator.
摘要翻译：本文公开的一些实施例涉及用于提供相对恒定的振荡频率的技术。在某些情况下，这些技术可以利用由自适应电压源供电的环形振荡器。自适应电压电源为环形振荡器中的相应延迟元件提供与温度相关的电源电压，使得环形振荡器的振荡频率在预定温度范围内近似恒定。例如，如果温度升高，则电源电压可以成比例地增加，从而倾向于限制由环形振荡器传递的振荡频率的变化。

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