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1. 发明授权

US5116780A Method of manufacturing a semiconductor device having improved contact resistance characteristics 失效
标题翻译：制造具有改进的接触电阻特性的半导体器件的制造方法
公开(公告)号：US5116780A
公开(公告)日：1992-05-26
申请号：US596732
申请日：1990-10-16
申请人： Shuichi Samata , Yoshiaki Matsushita
发明人： Shuichi Samata , Yoshiaki Matsushita
IPC分类号： H01L21/283 , H01L21/28 , H01L21/316 , H01L21/3205 , H01L21/336 , H01L29/41 , H01L29/45 , H01L29/78
CPC分类号： H01L29/456
摘要： A multi-layered insulation film of non-doped CVD SiO.sub.2 (silicon dioxide) film and BPSG (boro-phospho-silicate glass) film is formed on a silicon substrate. Films have a contact hole exposing impurity diffused region formed in silicon substrate. A semiconductor layer is formed in the contact hole. An Al (aluminum) film is formed on the semiconductor layer. The semiconductor layer contacts the BPSG film so that the contact resistance between the semiconductor layer and the Al (aluminum) film can be reduced, and a variation of the contact resistance between respective semiconductor devices can also be reduced.
摘要翻译：在硅衬底上形成非掺杂CVD SiO 2（二氧化硅）膜和BPSG（硼磷硅酸盐玻璃）膜的多层绝缘膜。膜具有暴露在硅衬底中形成的杂质扩散区的接触孔。在接触孔中形成半导体层。在半导体层上形成Al（铝）膜。半导体层与BPSG膜接触，能够降低半导体层与Al（铝）膜之间的接触电阻，能够降低各半导体器件之间的接触电阻的变化。

2. 发明授权

US5004702A Preparation method of selective growth silicon layer doped with impurities 失效
标题翻译：选择性生长硅掺杂杂质的方法
公开(公告)号：US5004702A
公开(公告)日：1991-04-02
申请号：US338794
申请日：1989-04-17
申请人： Shuichi Samata , Yoshiaki Matsushita
发明人： Shuichi Samata , Yoshiaki Matsushita
IPC分类号： H01L21/225 , H01L21/285 , H01L21/8238
CPC分类号： H01L21/28525 , H01L21/2257 , H01L21/823814
摘要： A semiconductor substrate having a surface region of P type and a surface region of N type is formed, then an insulating membrane is formed on the semiconductor substrate. The first contact hole which is formed in said region of P type and the second contact hole which is connected to said region of N type are formed by the same process as that for said insulating membrane. Non-doped silicon layer is grown in said first and second contact holes by the same selective growth process, in a single reactive furnace. A diffusion source layer containing impurities of P type is formed on said first contact hole and a diffusion source layer containing impurities of N type on said second contact hole. Impurities are diffused from said diffusion layers to said silicon layers, and said diffusion source layer is then removed. A metal wire layer is formed by connecting it to said silicon layer.
摘要翻译：形成具有P型表面区域和N型表面区域的半导体衬底，然后在半导体衬底上形成绝缘膜。在所述P型区域中形成的第一接触孔和与所述N型区域连接的第二接触孔通过与所述绝缘膜相同的工艺形成。在单个反应炉中，非掺杂硅层通过相同的选择性生长工艺在所述第一和第二接触孔中生长。在所述第一接触孔上形成含有P型杂质的扩散源层和在所述第二接触孔上含有N型杂质的扩散源层。杂质从所述扩散层扩散到所述硅层，然后去除所述扩散源层。通过将金属线层连接到所述硅层而形成金属线层。

3. 发明申请

US20080192345A1 Iodine Polarizing Film, a Method for Producing the Same, and a Polarizing Plate Using the Same 审中-公开
标题翻译：碘偏光膜，其制造方法和使用其的偏光板
公开(公告)号：US20080192345A1
公开(公告)日：2008-08-14
申请号：US11885685
申请日：2006-03-09
申请人： Noriaki Mochizuki , Kenichiro Yoshioka , Kouichi Tanaka , Yoshiaki Matsushita
发明人： Noriaki Mochizuki , Kenichiro Yoshioka , Kouichi Tanaka , Yoshiaki Matsushita
IPC分类号： G02B5/30 , B29D11/00 , G02F1/1335
CPC分类号： G02B5/3033 , B29C55/026 , B29C55/04 , B29K2029/04 , B29K2995/0034 , G02F1/133528 , Y10T428/1041
摘要： The present invention relates to a polarizing film obtained by stretching a polyvinyl alcohol resin film containing iodine, an iodide a cross-linking agent and/or waterproofing agent and then treating the film with a solution containing 0.0001 to 5.0 wt % of inorganic acid except for boric acid or a salt thereof and/or organic acid and having a pH of preferably 2≦pH≦5, more preferably 2.2≦pH≦5. Said polarizing film is excellent in wet heat durability and shows less decrease in polarization characteristics in wet heat test and said polarizing film obtained in a further preferable embodiment is also excellent in dry heat durability.
摘要翻译：本发明涉及通过拉伸含碘的聚乙烯醇树脂膜，碘化物，交联剂和/或防水剂获得的偏振膜，然后用含有0.0001至5.0重量％的无机酸的溶液处理该膜，除了硼酸或其盐和/或有机酸，并且pH优选为2 <= pH <= 5，更优选2.2 <= pH <= 5。所述偏振膜的湿热耐久性优异，在湿热试验中偏振特性的降低较少，在另一优选实施方式中所获得的偏光膜的干热耐久性也优异。

4. 发明授权

US5994756A Substrate having shallow trench isolation 失效
标题翻译：衬底具有浅沟槽隔离
公开(公告)号：US5994756A
公开(公告)日：1999-11-30
申请号：US751438
申请日：1996-11-20
申请人： Kaori Umezawa , Norihiko Tsuchiya , Yoshiaki Matsushita , Hiroyuki Kamijou , Atsushi Yagishita , Tsunehiro Kita
发明人： Kaori Umezawa , Norihiko Tsuchiya , Yoshiaki Matsushita , Hiroyuki Kamijou , Atsushi Yagishita , Tsunehiro Kita
IPC分类号： H01L21/762 , H01L27/04 , H01L23/58
CPC分类号： H01L21/76232 , H01L21/76264 , H01L21/76275 , H01L21/76283
摘要： A semiconductor substrate having a shallow trench isolation (STI) structure and a method of manufacturing the same are provided, i.e., an isolation substrate in which grooves are selectively formed at predetermined locations of the semiconductor substrate and oxide films using organic silicon source as material are buried in the grooves as buried oxide films. The present invention is characterized in that the buried oxide films are annealed at a predetermined temperature within the range of 1100 to 1350.degree. C. before or after planarization of the semiconductor substrate such that ring structures of more than 5-fold ring and ring structures of less than 4-fold ring are formed at predetermined rates in the buried oxide films. The above annealing allows stress of the oxide film buried in the grooves to be relaxed. Hence, the generation of dislocation is suppressed.
摘要翻译：提供具有浅沟槽隔离（STI）结构的半导体衬底及其制造方法，即，在半导体衬底的预定位置选择性地形成沟槽并且使用有机硅源作为材料的氧化物膜的隔离衬底埋在凹槽中作为掩埋氧化膜。本发明的特征在于，在半导体衬底的平坦化之前或之后，在1100〜1350℃的范围内的预定温度下对所述埋入氧化物膜进行退火，使得所述半导体衬底的环结构超过5倍，在掩埋氧化膜中以预定的速率形成小于4倍的环。通过上述退火，能够缓和埋入槽内的氧化膜的应力。因此，错位的产生被抑制。

5. 发明授权

US5246500A Vapor phase epitaxial growth apparatus 失效
标题翻译：气相外延生长装置
公开(公告)号：US5246500A
公开(公告)日：1993-09-21
申请号：US937743
申请日：1992-09-01
申请人： Shuichi Samata , Yoshiaki Matsushita
发明人： Shuichi Samata , Yoshiaki Matsushita
IPC分类号： C30B25/10 , C23C16/455 , C30B25/14 , H01L21/00 , H01L21/205
CPC分类号： H01L21/67115 , C23C16/455 , C30B25/14
摘要： A vapor phase growth apparatus is disclosed, which comprises a boat accommodating therein a plurality of semiconductor substrates, an inner tube surrounding the boat, an outer tube disposed outside the inner tube, a heater disposed outside the outer tube, a reaction gas injection nozzle disposed inside the inner tube and operating to eject a reaction gas against the semiconductor substrates, and a hydrogen halide gas injection nozzle disposed between the inner tube and the outer tube and operating to inject the hydrogen halide gas, wherein exhaust openings for exhausting the reaction gas are formed through a wall of the inner tube, thereby suppressing deposition of a reactant on an outer surface of the inner tube and an inner surface of the outer tube. The reaction gas injected from the reaction gas injection nozzle flows in the portion formed between the inner tube and the outer tube along with in the inner tube. Since the portion between the inner tube and the outer tube is heated by the heater disposed outside the outer tube, a reactant tends to be deposited on the outer surface of the inner tube and the inner surface of the outer tube. By injecting the hydrogen halide gas from the hydrogen halide gas injection nozzle to the portion formed between the inner tube and the outer tube, the deposition of the reactant can be suppressed.
摘要翻译：公开了一种气相生长装置，其包括容纳多个半导体衬底的舟皿，围绕舟皿的内管，设置在内管外部的外管，设置在外管外部的加热器，设置在反应气体注入喷嘴在内管内部并且操作以将反应气体喷射到半导体基板上;以及卤化氢气体注入喷嘴，其设置在内管和外管之间并且操作以喷射卤化氢气体，其中用于排出反应气体的排气口为通过内管的壁形成，从而抑制反应物沉积在内管的外表面和外管的内表面上。从反应气体喷射喷嘴喷射的反应气体与内管一起流入形成在内管和外管之间的部分。由于内管和外管之间的部分被设置在外管外部的加热器加热，反应物倾向于沉积在内管的外表面和外管的内表面上。通过将卤化氢气体从卤化氢气体注入喷嘴注入到形成在内管和外管之间的部分，可以抑制反应物的沉积。

6. 发明授权

US5148457A System for analyzing metal impurity on the surface of a single crystal semiconductor by using total reflection of X-rays fluorescence 失效
标题翻译：利用X射线荧光全面反射分析单晶半导体表面金属杂质的系统
公开(公告)号：US5148457A
公开(公告)日：1992-09-15
申请号：US719706
申请日：1991-06-27
申请人： Atsuko Kubota , Norihiko Tsuchiya , Shuichi Samata , Yoshiaki Matsushita , Mokuji Kageyama
发明人： Atsuko Kubota , Norihiko Tsuchiya , Shuichi Samata , Yoshiaki Matsushita , Mokuji Kageyama
IPC分类号： G01N23/223
CPC分类号： G01N23/223 , G01N2223/076
摘要： A system for analyzing a metal impurity at the surface of a single crystal semiconductor comprising: an incident device for allowing X-ray to be incident, at an incident angle less than a total reflection angle, onto the surface of a wafer in the form of a thin plate comprised of a single crystal semiconductor (e.g., silicon); a wafer fixing/positioning stage wherein when it is assumed that the wafer surface is partitioned by a lattice having an interval d, and that the wavelength of the X-ray from the incident device is .lambda., an angle that the X-ray and the wafer surface form is .theta., and an arbitrary integer is n, the stage is adapted to fix the crystal orientation of the wafer so as to satisfy the condition of "2d sin .theta..noteq.n.lambda.", and to allow sample points to which X-ray is incident to be subjected to positioning by a horizontal movement; and analyzing device for measuring a light quantity of a fluorescent X-ray generated as the result of the fact that the incident X-ray excites atoms at the wafer surface to analyze a quantity of the metal impurity attached on the wafer surface under the condition that the Bragg reflection causing measurement noises does not take place.

7. 发明授权

US4894206A Crystal pulling apparatus 失效
标题翻译：水晶拉机
公开(公告)号：US4894206A
公开(公告)日：1990-01-16
申请号：US91947
申请日：1987-09-01
申请人： Youji Yamashita , Masakatu Kojima , Yoshiaki Matsushita , Masanobu Ogino
发明人： Youji Yamashita , Masakatu Kojima , Yoshiaki Matsushita , Masanobu Ogino
IPC分类号： C30B15/12 , H01L21/18
CPC分类号： C30B15/12 , Y10S117/90 , Y10T117/1052
摘要： The present invention discloses a crystal pulling apparatus having a double-crucible structure, wherein an inner crucible is located in an outer crucible. An end of a pipe-like passage is located in a through hole formed in a side wall of an inner crucible located in an outer crucible, and a melt is supplied from the outer crucible to the inner crucible through the pipe-like passage, during crystal pulling. During melting or neckdown, prior to crystal pulling, diffusion of an impurity between the melts in the outer crucible and the inner crucible, and exchange of the melts between the outer crucible and the inner crucible are prevented by the pipe-like passage.
摘要翻译：本发明公开了一种具有双坩埚结构的晶体拉制装置，其中内坩埚位于外坩埚中。管状通道的端部位于形成在位于外坩埚内坩埚的侧壁中的通孔中，熔融物通过管状通道从外坩埚供应到内坩埚中水晶拉。在熔融或颈缩期间，在晶体拉伸之前，通过管状通道来防止杂质在外坩埚和内坩埚之间的熔体的扩散以及外坩埚和内坩埚之间的熔体的交换。

8. 发明授权

US4787997A Etching solution for evaluating crystal faults 失效
标题翻译：用于评估晶体缺陷的蚀刻解决方案
公开(公告)号：US4787997A
公开(公告)日：1988-11-29
申请号：US163033
申请日：1988-03-02
申请人： Yoshihiko Saito , Yoshiaki Matsushita
发明人： Yoshihiko Saito , Yoshiaki Matsushita
IPC分类号： H01L21/66 , B62L1/00 , H01L21/306 , H01L21/308 , B44C1/22
CPC分类号： C09K13/08 , G01N1/32
摘要： An etching solution used for evaluating crystal defects in a silicon wafer is disclosed. The etching solution is characterized by consisting of acetic acid, hydrofluoric acid, nitric acid, silver nitrate, and copper nitrate, and is very advantageous in consideration of the operator's health, since it does not contain Cr.sup.6+. The etching solution has a sufficiently high etching rate and detection properties.

9. 发明授权

US4645546A Semiconductor substrate 失效
标题翻译：半导体衬底
公开(公告)号：US4645546A
公开(公告)日：1987-02-24
申请号：US754298
申请日：1985-07-12
申请人： Yoshiaki Matsushita
发明人： Yoshiaki Matsushita
IPC分类号： H01L21/02 , H01L21/322 , H01L21/324 , H01L29/04
CPC分类号： H01L21/3221 , Y10S148/06
摘要： Disclosed is a silicon semiconductor substrate for a semiconductor integrated circuit such as LSI or VLSI. The silicon semiconductor substrate has an oxygen concentration ranging from 3.times.10.sup.17 cm.sup.-3 to 7.times.10.sup.17 cm.sup.-3 and a gettering layer on its backside. This gettering layer may comprise a nonsingle crystalline silicon layer such as polycrystalline silicon layer or amorphous silicon layer, or a layer having stacking fault density of more than 3.times.10.sup.4 cm.sup.-2.
摘要翻译：公开了一种用于诸如LSI或VLSI的半导体集成电路的硅半导体衬底。硅半导体衬底的氧浓度范围为3×10 17 cm -3至7×10 17 cm -3，背面为吸气层。这个吸气层可以包括非单一晶体硅层，例如多晶硅层或非晶硅层，或者具有大于3×104cm -2的堆垛层错密度的层。

10. 发明授权

US4579601A Method of growing a resistive epitaxial layer on a short lifetime epi-layer 失效
标题翻译：在短寿命外延层上生长电阻性外延层的方法
公开(公告)号：US4579601A
公开(公告)日：1986-04-01
申请号：US635434
申请日：1984-07-27
申请人： Shuichi Samata , Yoshiaki Matsushita
发明人： Shuichi Samata , Yoshiaki Matsushita
IPC分类号： H01L21/70 , H01L21/322 , H01L21/324 , H01L21/8242 , H01L27/10 , H01L29/167 , H01L21/20 , H01L21/225 , H01L21/265
CPC分类号： H01L27/10844 , H01L21/322 , H01L21/324 , H01L29/167 , Y10S438/934 , Y10S438/953
摘要： A method for manufacturing a semiconductor device has the steps of: forming a first thin single-crystal semiconductor layer on a semiconductor substrate of one conductivity type which contains oxygen, the first thin single-crystal semiconductor layer having a higher resistivity than that of the semiconductor substrate and having the same conductivity type as that of the semiconductor substrate; ion-implanting an electrically inactive impurity in the first thin single-crystal semiconductor layer; forming a second thin single-crystal semiconductor layer on the first thin single-crystal semiconductor layer, the second thin single-crystal semiconductor layer having the same conductivity type as that of the semiconductor substrate and having a higher resistivity than that of the semiconductor substrate; performing annealing for not less than four hours at a temperature of 550.degree. C. to 900.degree. C. after the electrically inactive impurity is ion-implanted; and forming a cell of a dynamic random access memory in the second thin single-crystal semiconductor layer, the cell having one transistor and one capacitor.
摘要翻译：半导体器件的制造方法具有以下步骤：在含有氧的一种导电型的半导体衬底上形成第一薄型单晶半导体层，第一薄型单晶半导体层的电阻率高于半导体并且具有与半导体衬底相同的导电类型; 在第一薄单晶半导体层中离子注入电惰性杂质; 在所述第一薄单晶半导体层上形成第二薄单晶半导体层，所述第二薄单晶半导体层具有与所述半导体衬底相同的导电类型并且具有比所述半导体衬底更高的电阻率; 在离子注入不活泼的杂质后，在550〜900℃的温度下进行不少于4小时的退火。以及在所述第二薄单晶半导体层中形成动态随机存取存储器的单元，所述单元具有一个晶体管和一个电容器。

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