专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

US20240339527A1 LOW CAPACITANCE AND LOW RESISTANCE DEVICES 审中-公开
公开(公告)号：US20240339527A1
公开(公告)日：2024-10-10
申请号：US18296521
申请日：2023-04-06
申请人： GlobalFoundries U.S. Inc.
发明人： Judson R. HOLT , John J. PEKARIK , Anindya NATH , Souvick MITRA
IPC分类号： H01L29/737 , H01L21/322
CPC分类号： H01L29/7371 , H01L21/322 , H01L29/747 , H01L29/78
摘要： The present disclosure relates to semiconductor structures and, more particularly, to low capacitance, low resistance devices and methods of manufacture. The structure includes: a semiconductor substrate; a device having an active region; and a porous semiconductor material within the semiconductor substrate and surrounding the active region of the device.

2. 发明授权

US11764071B2 Apparatus for stressing semiconductor substrates 有权
公开(公告)号：US11764071B2
公开(公告)日：2023-09-19
申请号：US16437988
申请日：2019-06-11
申请人： GlobalWafers Co., Ltd
发明人： Robert J. Falster , Vladimir V. Voronkov , John A. Pitney , Peter D. Albrecht
IPC分类号： H01L21/322 , H01L21/683 , H01L21/67 , H01L21/02 , H01L21/687 , C30B25/12 , H01L21/302
CPC分类号： H01L21/322 , C30B25/12 , H01L21/302 , H01L21/67092 , H01L21/6838 , H01L21/6875 , H01L21/68735
摘要： Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.

3. 发明公开

US20230215737A1 Method of annealing out silicon defectivity 审中-公开
公开(公告)号：US20230215737A1
公开(公告)日：2023-07-06
申请号：US17566942
申请日：2021-12-31
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Abbas Ali , Christopher Scott Whitesell , Pushpa Mahalingam , Uma Aghoram , Eddie Dee Pylant
IPC分类号： H01L21/322
CPC分类号： H01L21/322 , H01L21/76224
摘要： A method of forming an integrated circuit that includes placing a semiconductor substrate in a process chamber at an initial temperature, wherein one or more trenches are located within the semiconductor substrate. The temperature of the substrate is increased in a substantially oxygen-free ambient to an oxide-growth temperature. The temperature is then maintained at the oxide growth temperature while providing an oxidizing ambient, thereby forming an oxide layer on sidewalls of the trench. The temperature of the semiconductor wafer is then reduced to a final temperature below the initial temperature and removed from the process chamber.

4. 发明申请

US20180204735A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM 审中-公开
公开(公告)号：US20180204735A1
公开(公告)日：2018-07-19
申请号：US15921249
申请日：2018-03-14
申请人： HITACHI KOKUSAI ELECTRIC INC.
发明人： Kazuhiro YUASA , Noriaki MICHITA
IPC分类号： H01L21/322 , H01L21/324 , H01L21/02 , H01L21/268 , H01L21/67
CPC分类号： H01L21/322 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02494 , H01L21/02532 , H01L21/02667 , H01L21/02675 , H01L21/2686 , H01L21/324 , H01L21/67115 , H01L21/67248 , H01L21/67757
摘要： There is provide a technique that includes preparing a substrate, in which an insulating film is formed on a pattern having an aspect ratio of 20 or greater and a process target film having a thickness of 200 Å or smaller is formed on the insulating film, in a process chamber; raising a temperature of the substrate to a first temperature with an electromagnetic wave; crystallizing the process target film for a first process time period while maintaining the first temperature; raising the temperature of the substrate to a second temperature, which is higher than the first temperature, with the electromagnetic wave, after the act of crystallizing the process target film; and repairing a crystal defect of the crystallized process target film for a second process time period, which is shorter than the first process time period, while maintaining the second temperature.

5. 发明授权

US09768086B2 Methods and devices for fabricating and assembling printable semiconductor elements 有权
公开(公告)号：US09768086B2
公开(公告)日：2017-09-19
申请号：US15084211
申请日：2016-03-29
申请人： The Board of Trustees of the University of Illinois
发明人： Ralph G. Nuzzo , John A. Rogers , Etienne Menard , Keon Jae Lee , Dahl-Young Khang , Yugang Sun , Matthew Meitl , Zhengtao Zhu
IPC分类号： H01L23/02 , H01L21/322 , B82Y10/00 , H01L29/06 , H01L29/786 , H01L31/0392 , H01L31/18 , H01L21/02 , H01L21/308 , H01L29/12 , H01L29/04 , H01L23/00 , H01L21/683 , H01L27/12 , H01L25/075 , H01L33/00 , H01L33/32
CPC分类号： H01L29/76 , B81C2201/0185 , B82Y10/00 , H01L21/02521 , H01L21/02603 , H01L21/02628 , H01L21/308 , H01L21/322 , H01L21/6835 , H01L23/02 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/29 , H01L24/32 , H01L24/80 , H01L24/83 , H01L24/94 , H01L24/97 , H01L25/0753 , H01L27/1285 , H01L27/1292 , H01L29/04 , H01L29/06 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/12 , H01L29/78603 , H01L29/78681 , H01L29/78696 , H01L31/0392 , H01L31/03926 , H01L31/1804 , H01L31/1864 , H01L31/1896 , H01L33/007 , H01L33/0079 , H01L33/32 , H01L2221/68368 , H01L2221/68381 , H01L2224/03 , H01L2224/0332 , H01L2224/0345 , H01L2224/03614 , H01L2224/0362 , H01L2224/05073 , H01L2224/05082 , H01L2224/05124 , H01L2224/05144 , H01L2224/05155 , H01L2224/05166 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05555 , H01L2224/05644 , H01L2224/05666 , H01L2224/08225 , H01L2224/2919 , H01L2224/32225 , H01L2224/80 , H01L2224/80006 , H01L2224/80121 , H01L2224/80862 , H01L2224/80895 , H01L2224/83 , H01L2224/83005 , H01L2224/83121 , H01L2224/83192 , H01L2224/83193 , H01L2224/8385 , H01L2224/83862 , H01L2224/9202 , H01L2224/94 , H01L2224/95 , H01L2224/97 , H01L2924/00012 , H01L2924/01032 , H01L2924/0665 , H01L2924/10253 , H01L2924/10329 , H01L2924/12032 , H01L2924/12036 , H01L2924/12041 , H01L2924/12042 , H01L2924/12043 , H01L2924/12044 , H01L2924/1305 , H01L2924/1306 , H01L2924/13063 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15159 , H01L2924/15162 , H01L2924/15788 , H01L2924/1579 , Y02E10/547 , Y02P70/521 , Y10S977/707 , Y10S977/724 , H01L2924/00014 , H01L2924/00
摘要： The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

6. 发明申请

US20170194145A1 CONTROLLED CONFINED LATERAL III-V EPITAXY 有权
公开(公告)号：US20170194145A1
公开(公告)日：2017-07-06
申请号：US15237114
申请日：2016-08-15
申请人： International Business Machines Corporation
发明人： Karthik Balakrishnan , Lukas Czornomaz , Pouya Hashemi , Alexander Reznicek
IPC分类号： H01L21/02 , H01L21/306 , H01L21/322 , H01L21/84 , H01L21/311
CPC分类号： H01L21/02645 , H01L21/02164 , H01L21/02236 , H01L21/02255 , H01L21/0245 , H01L21/02488 , H01L21/02538 , H01L21/02609 , H01L21/02639 , H01L21/02647 , H01L21/30604 , H01L21/30612 , H01L21/308 , H01L21/31116 , H01L21/322 , H01L21/8258 , H01L21/84 , H01L27/1203
摘要： After forming a seed layer over a first end of a sacrificial semiconductor layer composed of silicon germanium, a remaining portion of the sacrificial semiconductor layer is removed to provide a trench. Next, a semiconductor barrier layer is formed on a sidewall of the seed layer that is exposed by the trench. A III-V compound semiconductor layer is formed within the trench by a lateral epitaxial semiconductor regrowth process.

7. 发明申请

US20170062561A1 STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE 有权
标题翻译：半导体器件结构的结构与形成方法
公开(公告)号：US20170062561A1
公开(公告)日：2017-03-02
申请号：US14840904
申请日：2015-08-31
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Cheng-Yi PENG , Chih-Chieh YEH , Hung-Li CHIANG , Hung-Ming CHEN , Yee-Chia YEO
IPC分类号： H01L29/06 , H01L21/322
CPC分类号： H01L29/7853 , H01L21/322 , H01L21/324 , H01L21/823431 , H01L23/3171 , H01L27/0886 , H01L29/0649 , H01L29/0657 , H01L29/66795 , H01L29/785
摘要： Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The fin structure includes a first surface and a second surface. The first surface is inclined to the second surface. The semiconductor device structure also includes a passivation layer covering the first surface and the second surface of the fin structure. The thickness of a first portion of the passivation layer covering the first surface is substantially the same as that of a second portion of the passivation layer covering the second surface.
摘要翻译：提供半导体器件结构的结构和形成方法。半导体器件结构包括在半导体衬底上的鳍结构。翅片结构包括第一表面和第二表面。第一表面倾斜于第二表面。半导体器件结构还包括覆盖翅片结构的第一表面和第二表面的钝化层。覆盖第一表面的钝化层的第一部分的厚度与覆盖第二表面的钝化层的第二部分的厚度基本相同。

8. 发明申请

US20170047319A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：US20170047319A1
公开(公告)日：2017-02-16
申请号：US15335440
申请日：2016-10-27
申请人： FUJI ELECTRIC CO., LTD.
发明人： Tatsuya NAITO , Masahito OTSUKI
IPC分类号： H01L27/06 , H01L21/304 , H01L21/265 , H01L29/06 , H01L29/739
CPC分类号： H01L27/0623 , H01L21/265 , H01L21/304 , H01L21/322 , H01L21/8234 , H01L27/04 , H01L27/0629 , H01L27/0727 , H01L27/08 , H01L27/088 , H01L29/06 , H01L29/0619 , H01L29/0634 , H01L29/739 , H01L29/7395 , H01L29/78 , H01L29/861 , H01L29/868
摘要： An SJ-MOSFET and IGBT are provided in a single semiconductor chip. Furthermore, a balance is made between a carrier amount of n-type columns and a carrier amount of p-type columns, to encourage formation of a depletion layer in when a reverse voltage is applied in the SJ-MOSFET section. Provided is a includes a semiconductor substrate, a super junction structure formed on a front surface side of the semiconductor substrate, and a field stop layer formed at a position overlapping with the super junction structure on a back surface side of the semiconductor substrate, in a manner to not contact an end of the super junction structure on the back surface side.
摘要翻译：在单个半导体芯片中提供SJ-MOSFET和IGBT。此外，在n型列的载体量和p型列的载流量之间取得平衡，以在SJ-MOSFET部中施加反向电压时促进形成耗尽层。提供了一种半导体衬底，形成在半导体衬底的前表面侧上的超结结构，以及形成在与半导体衬底的背面侧上的与超结结构重叠的位置的场阻挡层，不会在背面侧接触超结结构的一端。

9. 发明授权

US09570297B1 Elimination of defects in long aspect ratio trapping trench structures 有权
标题翻译：消除长宽比捕获沟槽结构中的缺陷
公开(公告)号：US09570297B1
公开(公告)日：2017-02-14
申请号：US14963283
申请日：2015-12-09
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L21/02 , H01L21/20
CPC分类号： H01L21/02636 , H01L21/02 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02639 , H01L21/02647 , H01L21/027 , H01L21/20 , H01L21/2015 , H01L21/2018 , H01L21/322 , H01L29/06
摘要： A method of forming a semiconductor in a long trench. The method may include; forming a first semiconductor on a substrate and in a long trench; forming a first spacer along sidewalls of the long trench and above the first semiconductor, a portion of the first semiconductor remains exposed; recessing the exposed portion of the first semiconductor; forming an insulator layer on the recessed portion of the first semiconductor; forming a second semiconductor on the insulator layer; forming a second spacer on sidewalls of the first spacer and above the second semiconductor, a portion of the second semiconductor remains exposed; removing the exposed portion of the second semiconductor; and removing a frond end and a back end of the first semiconductor and the second semiconductor, wherein the front end and back end are separated by a central region and the central region extends across the width of the long trench.
摘要翻译：在长沟槽中形成半导体的方法。该方法可以包括：在衬底和长沟槽中形成第一半导体; 在所述长沟槽的侧壁和所述第一半导体之上形成第一间隔物，所述第一半导体的一部分保持暴露; 使第一半导体的暴露部分凹陷; 在所述第一半导体的凹部上形成绝缘体层; 在所述绝缘体层上形成第二半导体; 在所述第一间隔物的侧壁上形成第二间隔物，在所述第二半导体之上形成第二间隔物，所述第二半导体的一部分保持暴露; 去除所述第二半导体的暴露部分; 以及去除所述第一半导体和所述第二半导体的边缘和后端，其中所述前端和后端由中心区域分开，并且所述中心区域延伸穿过所述长沟槽的宽度。

10. 发明授权

US09517530B2 Wafer producing method 有权
标题翻译：晶圆生产方法
公开(公告)号：US09517530B2
公开(公告)日：2016-12-13
申请号：US14988310
申请日：2016-01-05
申请人： DISCO CORPORATION
发明人： Kazuya Hirata , Kunimitsu Takahashi , Yoko Nishino
IPC分类号： H01L21/30 , H01L21/322 , B23K26/00 , B28D5/00
CPC分类号： B23K26/0057 , B23K26/0006 , B23K26/53 , B23K2103/56 , B28D5/0011 , H01L21/30 , H01L21/322
摘要： A hexagonal single crystal wafer is produced from a hexagonal single crystal ingot. A separation start point is formed by setting a focal point of a laser beam inside the ingot at a predetermined depth from the upper surface of the ingot, which depth corresponds to the thickness of the wafer to be produced, and next applying the laser beam to the upper surface of the ingot while relatively moving the focal point and the ingot to thereby form a modified layer parallel to the upper surface of the ingot and form cracks extending from the modified layer along a c-plane, thus forming a separation start point. The focal point is indexed by relatively moving the focal point in the direction where an off angle is formed and the c-plane is inclined downward.
摘要翻译：六角形单晶晶片由六方晶单晶锭制成。通过将晶锭内部的激光束的焦点从锭的上表面设定在规定的深度，形成分离起始点，该深度对应于待制造的晶片的厚度，接下来将激光束施加到铸锭的上表面，同时相对移动焦点和锭，从而形成平行于锭的上表面的改性层，并形成沿着c平面从修饰层延伸的裂纹，从而形成分离开始点。通过在形成偏角的方向上相对移动焦点并且c平面向下倾斜来指向焦点。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式