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1. 发明授权

US11856710B2 Method of manufacturing an electronic device 有权
公开(公告)号：US11856710B2
公开(公告)日：2023-12-26
申请号：US17752868
申请日：2022-05-25
申请人： Innolux Corporation
发明人： Kai Cheng , Fang-Ying Lin , Tsau-Hua Hsieh
IPC分类号： H05K1/00 , H05K1/02 , H05K1/16 , H05K3/00 , H05K3/30 , H01L21/00 , H01L21/48 , H01L23/00 , H01L23/48 , H01L33/62 , H05K1/18
CPC分类号： H05K3/301 , H05K1/183 , H05K2203/16
摘要： A method of manufacturing an electronic device including the following steps is provided herein. A plurality of first electronic components is provided. The plurality of first electronic components is transferred onto a plurality of pickup sites. An empty pickup site from the plurality of pickup sites may be figured out, wherein the plurality of first electronic components is absent at the empty pickup site. A second electronic component is transferred onto the empty pickup site. A target substrate is provided. The plurality of first electronic components and the second electronic component are transferred onto the target substrate.

2. 发明授权

US11647591B2 Compliant pin surface mount technology pad for rework 有权
公开(公告)号：US11647591B2
公开(公告)日：2023-05-09
申请号：US17343857
申请日：2021-06-10
申请人： International Business Machines Corporation
发明人： Theron Lee Lewis , David J. Braun , John R. Dangler
IPC分类号： H05K3/22 , H05K3/34 , H01R12/58 , B23K1/00 , B23K1/20 , B23K3/06 , B23K101/42
CPC分类号： H05K3/225 , B23K1/0016 , B23K1/203 , B23K3/0653 , H01R12/58 , H05K3/3447 , B23K2101/42 , H05K2203/044 , H05K2203/143 , H05K2203/16 , H05K2203/173
摘要： Aspects of the invention include a press-fit pin for mechanically and electrically connecting to a through-hole of a substrate. The press-fit pin can include a press-fit portion configured to be deformed upon insertion into the through-hole against a plated surface of the through-hole. A surface mount technology (SMT) pad can be coupled to a first end of the press-fit portion. The SMT pad can include a conductive material. The press-fit pin can further include a trace extension coupled to the SMT pad. The trace extension can extend from the SMT pad in a direction perpendicular to the press-fit portion. The press-fit pin can include a tip portion coupled to a second end of the press-fit portion.

3. 发明授权

US10064271B2 PCB processing method and PCB 有权
公开(公告)号：US10064271B2
公开(公告)日：2018-08-28
申请号：US15108405
申请日：2014-05-21
申请人： ZTE CORPORATION
发明人： Bi Yi , Fengchao Ma , Yonghui Ren , Wang Xiong , Yingxin Wang
IPC分类号： H05K1/02 , H05K1/09 , H05K3/46 , H05K1/11 , H05K3/42 , H05K3/00
CPC分类号： H05K1/0298 , H05K1/09 , H05K1/115 , H05K3/0047 , H05K3/424 , H05K3/429 , H05K3/4611 , H05K3/4623 , H05K2201/10303 , H05K2203/0207 , H05K2203/16
摘要： The present disclosure discloses a PCB processing method and a PCB. The method includes: respectively carrying out laminating processing on a plurality of PCB daughter boards constituting a PCB, and drilling and electroplating the top-most PCB daughter board to form a via hole; and laminating the plurality of PCB daughter boards together to form the PCB, and drilling and electroplating the formed PCB to form a through hole for mounting a connector, wherein a blind hole for mounting a connector is formed by the via hole, and a depth of the blind hole is greater than or equal to the length of a signal pin of the connector. By virtue of the technical scheme of the present disclosure, a space between wafers of the lower layer of PCBs may be doubled, and the space for layout between wafers may be doubled.

4. 发明授权

US09883582B2 Circuit boards and circuit board assemblies 有权
公开(公告)号：US09883582B2
公开(公告)日：2018-01-30
申请号：US14947437
申请日：2015-11-20
申请人： Hamilton Sundstrand Corporation
发明人： Tran Lin
IPC分类号： H05K1/02 , H01L23/15 , H01L23/367 , H01L23/50 , H01L23/498 , H05K1/18 , H05K1/11 , G01R31/02 , G01R31/04 , H05K3/22
CPC分类号： H05K1/0268 , G01R31/026 , G01R31/046 , H01L23/15 , H01L23/3675 , H01L23/49827 , H01L23/50 , H05K1/0206 , H05K1/0215 , H05K1/111 , H05K1/181 , H05K3/225 , H05K3/3421 , H05K2201/094 , H05K2201/10628 , H05K2201/10689 , H05K2203/16 , H05K2203/162 , Y02P70/613
摘要： A printed circuit board includes a body and a belly pad seated within with the body. The belly pad is electrically separated into a first pad and a second pad. The first pad and the second pad are arranged to be electrically connected to one another by an interconnect electrically connecting the belly pad to a conductive plane of an electrical component, thereby allowing continuity testing across an interface between the first pad and the interconnect.

5. 发明申请

US20160323995A1 PCB PROCESSING METHOD AND PCB 审中-公开
标题翻译： PCB加工方法和PCB
公开(公告)号：US20160323995A1
公开(公告)日：2016-11-03
申请号：US15108405
申请日：2014-05-21
申请人： ZTE CORPORATION
发明人： Bi YI , Fengchao MA , Yonghui REN , Wang XIONG , Yingxin WANG
IPC分类号： H05K1/02 , H05K1/09 , H05K3/46 , H05K1/11 , H05K3/42 , H05K3/00
CPC分类号： H05K1/0298 , H05K1/09 , H05K1/115 , H05K3/0047 , H05K3/424 , H05K3/429 , H05K3/4611 , H05K3/4623 , H05K2201/10303 , H05K2203/0207 , H05K2203/16
摘要： The present disclosure discloses a PCB processing method and a PCB. The method includes: respectively carrying out laminating processing on a plurality of PCB daughter boards constituting a PCB, and drilling and electroplating the top-most PCB daughter board to form a via hole; and laminating the plurality of PCB daughter boards together to form the PCB, and drilling and electroplating the formed PCB to form a through hole for mounting a connector, wherein a blind hole for mounting a connector is formed by the via hole, and a depth of the blind hole is greater than or equal to the length of a signal pin of the connector. By virtue of the technical scheme of the present disclosure, a space between wafers of the lower layer of PCBs may be doubled, and the space for layout between wafers may be doubled.
摘要翻译：本公开公开了一种PCB处理方法和PCB。该方法包括：分别在构成PCB的多个PCB子板上进行层压处理，以及对最顶层的PCB子板进行钻孔和电镀以形成通孔; 并且将多个PCB子板层压在一起以形成PCB，并且对所形成的PCB进行钻孔和电镀以形成用于安装连接器的通孔，其中用于安装连接器的盲孔由通孔形成，并且深度盲孔大于或等于连接器的信号针的长度。由于本公开的技术方案，PCB的下层的晶片之间的间隔可以加倍，并且晶片之间的布局空间可以加倍。

6. 发明授权

US09155198B2 Electronic module allowing fine tuning after assembly 有权
标题翻译：组装后电子模块允许微调
公开(公告)号：US09155198B2
公开(公告)日：2015-10-06
申请号：US14339477
申请日：2014-07-24
申请人： Eagantu Ltd.
发明人： Michael Dakhiya , Eran Shaked
IPC分类号： H05K1/18 , H05K3/32 , H05K1/11 , H01L23/13 , H01L21/66 , H01L23/04 , H01L23/15 , H01L23/538 , H01L25/065 , H01L25/10 , H01C17/22 , H01L23/66 , H01L23/00
CPC分类号： H05K1/183 , H01C17/22 , H01L22/14 , H01L22/20 , H01L23/04 , H01L23/13 , H01L23/15 , H01L23/5381 , H01L23/5383 , H01L23/5384 , H01L23/66 , H01L24/16 , H01L24/81 , H01L25/0652 , H01L25/105 , H01L2223/6655 , H01L2224/16225 , H01L2224/81439 , H01L2224/81447 , H01L2224/8149 , H01L2224/81493 , H01L2225/1023 , H01L2225/1047 , H01L2924/12042 , H01L2924/14 , H01L2924/15156 , H01L2924/15311 , H01L2924/15313 , H01L2924/15787 , H01L2924/1579 , H01L2924/16195 , H01L2924/1627 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3011 , H05K3/32 , H05K2203/16 , H05K2203/171 , Y10T29/49004 , Y10T29/4913 , Y10T29/53022 , Y10T29/53174 , H01L2924/00
摘要： An electronic module includes a substrate, which includes a dielectric material having multiple sides, including first and second sides, and first and second cavities indented respectively within the first and second sides. First and second conductive contacts within the first and second cavities are configured for contact with at least first and second electronic components that are mounted respectively in the first and second cavities. Conductive traces within the substrate are in electrical communication with the first and second conductive contacts.
摘要翻译：电子模块包括基板，其包括具有多个侧面的电介质材料，所述电介质材料包括第一侧面和第二侧面，以及分别在所述第一侧面和所述第二侧面中的第一和第二空腔。第一和第二空腔内的第一和第二导电触点构造成与分别安装在第一和第二腔中的至少第一和第二电子部件接触。衬底内的导电迹线与第一和第二导电触点电连通。

7. 发明申请

US20150131248A1 THREE-DIMENSIONAL MODULES FOR ELECTRONIC INTEGRATION 审中-公开
标题翻译：用于电子整合的三维模块
公开(公告)号：US20150131248A1
公开(公告)日：2015-05-14
申请号：US14397903
申请日：2013-05-09
申请人： Eagantu Ltd.
发明人： Michael Dakhiya , Eran Shaked
IPC分类号： H05K1/02 , H05K3/36 , H05K3/30 , H05K1/18 , H05K1/14
CPC分类号： H05K1/0284 , H01L23/13 , H01L23/15 , H01L23/5381 , H01L23/5383 , H01L23/5384 , H01L25/0652 , H01L25/105 , H01L2224/16225 , H01L2924/1461 , H01L2924/15156 , H01L2924/15311 , H01L2924/1627 , H05K1/144 , H05K1/183 , H05K3/306 , H05K3/32 , H05K3/36 , H05K3/4697 , H05K2203/16 , H05K2203/171 , Y10T29/49004 , Y10T29/49126 , Y10T29/4913 , Y10T29/49139 , Y10T29/53022 , H01L2924/00
摘要： An electronic module (20, 39, 60, 80, 132, 140, 144) includes a substrate (21), which includes a dielectric material having a cavity (40, 42, 134, 142) formed therein. First conductive contacts (44) within the cavity are configured for contact with at least one first electronic component (32) that is mounted in the cavity. Second conductive contacts (44) on a surface of the substrate that surrounds the cavity are configured for contact with at least a second electronic component (28, 30) that is mounted over the cavity. Conductive traces (36, 48) within the substrate are in electrical communication with the first and second conductive contacts.
摘要翻译：电子模块（20,39,60,80,120,140,144）包括衬底（21），其包括形成在其中的空腔（40,42,134,142）的电介质材料。空腔内的第一导电触点（44）构造成与安装在空腔中的至少一个第一电子部件（32）接触。围绕空腔的基板的表面上的第二导电触点（44）构造成与安装在空腔上的至少第二电子部件（28,30）接触。衬底内的导电迹线（36,48）与第一和第二导电触点电连通。

8. 发明授权

US08851356B1 Flexible circuit board interconnection and methods 有权
标题翻译：灵活的电路板互连和方法
公开(公告)号：US08851356B1
公开(公告)日：2014-10-07
申请号：US13158149
申请日：2011-06-10
申请人： Henry V. Holec , Wm. Todd Crandell , Eric Henry Holec
发明人： Henry V. Holec , Wm. Todd Crandell , Eric Henry Holec
IPC分类号： B23K31/02
CPC分类号： H05K3/363 , B23K1/0016 , B23K37/04 , F21Y2107/30 , F21Y2115/10 , H01R4/02 , H01R12/61 , H05K1/0269 , H05K1/118 , H05K1/144 , H05K1/147 , H05K1/189 , H05K2201/0311 , H05K2201/058 , H05K2201/09481 , H05K2201/09918 , H05K2201/10106 , H05K2203/0195 , H05K2203/0228 , H05K2203/043 , H05K2203/16
摘要： Embodiments of the invention include flexible circuit board interconnections and methods regarding the same. In an embodiment, the invention includes a method of connecting a plurality of flexible circuit boards together comprising the steps applying a solder composition between an upper surface of a first flexible circuit board and a lower surface of a second flexible circuit board; holding the upper surface of the first flexible circuit board and the lower surface of the second flexible circuit board together; and reflowing the solder composition with a heat source to bond the first flexible circuit board and the second flexible circuit board together to form a flexible circuit board strip having a length longer than either of the first flexible circuit board or second flexible circuit board separately. In an embodiment the invention includes a circuit board clamp for holding flexible circuit boards together, the clamp including a u-shaped fastener; a spring tension arm connected to the u-shaped fastener; and an attachment mechanism connected to the spring tension arm. Other embodiments are also included herein.
摘要翻译：本发明的实施例包括柔性电路板互连和相关的方法。在一个实施例中，本发明包括将多个柔性电路板连接在一起的方法，包括在第一柔性电路板的上表面和第二柔性电路板的下表面之间施加焊料组合物的步骤; 将第一柔性电路板的上表面和第二柔性电路板的下表面保持在一起; 并且用热源回流焊料组合物，以将第一柔性电路板和第二柔性电路板结合在一起，以分别形成长度大于第一柔性电路板或第二柔性电路板的长度的柔性电路板条。在一个实施例中，本发明包括用于将柔性电路板保持在一起的电路板夹，所述夹具包括u形紧固件; 连接到U形紧固件的弹簧张力臂; 以及连接到弹簧张力臂的连接机构。本文还包括其它实施例。

9. 发明申请

US20130016465A1 Plated Through Hole Void Detection in Printed Circuit Boards by Detecting A pH-Sensitive Component 有权
标题翻译：通过检测pH敏感元件在印刷电路板中镀覆通孔检测
公开(公告)号：US20130016465A1
公开(公告)日：2013-01-17
申请号：US13182906
申请日：2011-07-14
申请人： Bruce John Chamberlin , Chang-Min Chu , Gao-Bin Hu , Joseph Kuczynski , Kaspar Ka Chung Tsang
发明人： Bruce John Chamberlin , Chang-Min Chu , Gao-Bin Hu , Joseph Kuczynski , Kaspar Ka Chung Tsang
IPC分类号： G06F1/16 , G01R31/28 , H05K1/00
CPC分类号： G01N21/80 , H05K1/0269 , H05K3/22 , H05K3/225 , H05K3/42 , H05K2203/16 , H05K2203/161 , Y10T29/49004
摘要： An approach is provided in which a pH-indicating compound is incorporated in a printed circuit board. The printed circuit board includes a number of layers with the pH-sensitive indicator being incorporated in one of the layers. Conductive pathways are formed from a conductive sheet laminated onto an outer surface of the printed circuit board. The printed circuit board is exposed to a pH-activating solution. Plated-through hole defects in the printed circuit board are identified by detecting a color formation at a surface location of the printed circuit board that corresponds to the plated-through hole defect. Another approach is also provided where a pH-activating compound is incorporated in one of the layers of the printed circuit board which is then exposed to a pH-indicating solution to produce the color formation that identifies the location of the plated-through hole defect.
摘要翻译：提供了其中将pH指示化合物并入印刷电路板中的方法。印刷电路板包括多个层，其中pH敏感指示器被结合在一个层中。导电路径由层叠在印刷电路板的外表面上的导电片形成。将印刷电路板暴露于pH活化溶液。通过检测印刷电路板的与镀通孔缺陷相对应的表面位置处的颜色形成来识别印刷电路板中的通孔缺陷。还提供另一种方法，其中将pH活化化合物并入印刷电路板的一个层中，然后暴露于pH指示溶液以产生识别电镀通孔缺陷位置的着色层。

10. 发明公开

US20240159517A1 OPTICAL SYSTEM FOR MEASURING THE DEPTH OF AN INNER LAYER OF A PRINTED CIRCUIT BOARD 审中-公开
公开(公告)号：US20240159517A1
公开(公告)日：2024-05-16
申请号：US18281303
申请日：2021-03-24
申请人： NANJING TALIANG TECHNOLOGY CO., LTD.
发明人： Chen-Chi CHIEN
IPC分类号： G01B11/22 , H05K3/00
CPC分类号： G01B11/22 , H05K3/00 , H05K2203/16
摘要： An optical system for measuring the depth of an inner layer of a PCB, includes a light source transmitter used to emit an incident light, a controller, a CCD lens module, a pellicle mirror module, a depth measuring device, a reflective mirror module set at one end of the depth measuring device at an angle of 45 degrees, and a processor. When the incident light is incident on the surface copper of the PCB, a first reflected light is generated to pass through the reflective mirror module and the pellicle mirror module to the CCD lens module, then, the depth measuring device starts to move in the PCB until the incident light is incident on the inner layer copper of the PCB to generate a second reflected light that passes through the reflective mirror module and the pellet mirror module to the CCD lens module.

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