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1. 发明授权

US08704377B2 Compliant conductive nano-particle electrical interconnect 有权
标题翻译：符合导电纳米颗粒电气互连
公开(公告)号：US08704377B2
公开(公告)日：2014-04-22
申请号：US13969953
申请日：2013-08-19
申请人： HSIO Technologies, LLC
发明人： James Rathburn
IPC分类号： H01L23/48
CPC分类号： H01L23/48 , B82Y10/00 , H01R23/722 , H05K1/0231 , H05K1/113 , H05K1/141 , H05K3/32 , H05K3/3436 , H05K3/4038 , H05K3/4069 , H05K7/1069 , H05K7/1092 , H05K2201/049 , Y10T29/4913 , Y10T29/49147
摘要： An electrical interconnect providing an interconnect between contacts on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a resilient substrate with a plurality of through holes extending from a first surface to a second surface. A resilient material is located in the through holes. The resilient material includes an opening extending from the first surface to the second surface. A plurality of discrete, free-flowing conductive nano-particles are located in the openings of the resilient material. The conductive particles are substantially free of non-conductive materials. A plurality of first contact members are located in the through holes adjacent the first surface and a plurality of second contact members are located in the through holes adjacent the second surface. The first and second contact members are electrically coupled to the nano-particles.
摘要翻译：提供IC器件上的触点与印刷电路板（PCB）上的接触焊盘之间的互连的电互连。电互连包括具有从第一表面延伸到第二表面的多个通孔的弹性基底。弹性材料位于通孔中。弹性材料包括从第一表面延伸到第二表面的开口。多个离散的自由流动的导电纳米颗粒位于弹性材料的开口中。导电颗粒基本上不含非导电材料。多个第一接触构件位于邻近第一表面的通孔中，并且多个第二接触构件位于与第二表面相邻的通孔中。第一和第二接触构件电耦合到纳米颗粒。

2. 发明授权

US09076884B2 Compliant printed circuit semiconductor package 有权
标题翻译：符合印刷电路半导体封装
公开(公告)号：US09076884B2
公开(公告)日：2015-07-07
申请号：US14086029
申请日：2013-11-21
申请人： HSIO TECHNOLOGIES, LLC
发明人： James Rathburn
IPC分类号： H01L21/00 , H01L23/00 , H01L23/498 , H01L23/538 , H05K1/18
CPC分类号： H01L24/82 , H01L23/49811 , H01L23/5389 , H01L24/18 , H01L24/19 , H01L24/20 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/20 , H01L2224/73267 , H01L2224/92244 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/12044 , H01L2924/1306 , H01L2924/14 , H01L2924/15153 , H01L2924/15174 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3011 , H01L2924/3025 , H05K1/185 , H01L2924/00
摘要： A method of making a package for a semiconductor device having electrical terminals. At least one semiconductor device is located on a substrate. A first dielectric layer is printed on at least a portion of the semiconductor device to include first recesses aligned with a plurality of the electrical terminals. A conductive material is deposited in the first recesses forming contact members. A second dielectric layer is printed on at least a portion of the first dielectric layer to include second recesses aligned with a plurality of the first recesses. A conductive material is deposited in at least a portion of the second recesses to include a circuit geometry and a plurality of exposed terminals. A compliant material is deposited in recesses in one or more of the first and second dielectric layers adjacent to a plurality of the exposed terminals.
摘要翻译：一种制造具有电端子的半导体器件的封装的方法。至少一个半导体器件位于衬底上。在半导体器件的至少一部分上印刷第一电介质层以包括与多个电端子对准的第一凹部。在形成接触构件的第一凹部中沉积导电材料。第二电介质层印刷在第一电介质层的至少一部分上，以包括与多个第一凹槽对准的第二凹槽。导电材料沉积在第二凹槽的至少一部分中以包括电路几何形状和多个暴露端子。兼容材料沉积在与多个暴露端子相邻的第一和第二电介质层中的一个或多个中的凹槽中。

3. 发明申请

US20140043782A1 COMPLIANT CORE PERIPHERAL LEAD SEMICONDUCTOR SOCKET 有权
标题翻译：合格的核心外围导线半导体插座
公开(公告)号：US20140043782A1
公开(公告)日：2014-02-13
申请号：US14058863
申请日：2013-10-21
申请人： HSIO TECHNOLOGIES, LLC
发明人： James Rathburn
IPC分类号： H01L23/522 , H05K3/40
CPC分类号： H01L23/34 , G01R1/0416 , H01L23/522 , H01L2224/13 , H05K3/325 , H05K3/4007 , H05K2201/0133 , H05K2201/0187 , H05K2201/09036 , H05K2201/09481 , H05K2201/0949 , H05K2201/10378 , H05K2203/162 , Y10T29/49165
摘要： An electrical interconnect between terminals on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a substrate with a first surface having a plurality of openings arranged to correspond to the terminals on the IC device. A compliant material is located in the openings. A plurality of first conductive traces extend along the first surface of the substrate and onto the compliant material. The compliant material provides a biasing force that resists flexure of the first conductive traces into the openings. Vias extending through the substrate are electrically coupled the first conductive traces. A plurality of second conductive traces extend along the second surface of the substrate and are electrically coupled to a vias. The second conductive traces are configured to electrical couple with the contact pads on the PCB.
摘要翻译： IC器件上的端子和印刷电路板（PCB）上的接触焊盘之间的电气互连。电互连包括具有第一表面的基板，该第一表面具有多个开口，其布置成对应于IC器件上的端子。柔性材料位于开口中。多个第一导电迹线沿着衬底的第一表面延伸到柔性材料上。柔性材料提供抵抗第一导电迹线弯曲到开口中的偏压力。延伸穿过衬底的通孔电耦合第一导电迹线。多个第二导电迹线沿着衬底的第二表面延伸并且电耦合到通孔。第二导电迹线被配置为与PCB上的接触焊盘电耦合。

4. 发明授权

US10159154B2 Fusion bonded liquid crystal polymer circuit structure 有权
公开(公告)号：US10159154B2
公开(公告)日：2018-12-18
申请号：US14864215
申请日：2015-09-24
申请人： HSIO TECHNOLOGIES, LLC
发明人： James Rathburn
IPC分类号： H05K3/46 , C25D7/12 , H05K1/03 , C25D5/02 , C23C18/16 , H05K3/42 , B23K103/12 , B23K103/00 , C23C18/38
摘要： A method of making a multilayered, fusion bonded circuit structure. A first circuitry layer is attached to a first major surface of a first LCP substrate. A plurality of first recesses are formed that extend from a second major surface of the first substrate to the first circuitry layer. The first recesses are then plated to form a plurality of first conductive pillars of solid metal that substantially fill the first recesses. A plurality of second recesses are formed in a second LCP substrate corresponding to a plurality of the first conductive pillars. The second recess are plated to form a plurality of second conductive structures that extend between first and second major surfaces of the second substrate. The second major surface of the first substrate is positioned adjacent to the second major surface of the second substrate. The first conductive pillars are aligned with the second conductive structures. The stack is then fusion bonded to mechanically couple the first conductive pillars to the second conductive structures.

5. 发明授权

US09699906B2 Hybrid printed circuit assembly with low density main core and embedded high density circuit regions 有权
公开(公告)号：US09699906B2
公开(公告)日：2017-07-04
申请号：US14408205
申请日：2013-03-13
申请人： HSIO TECHNOLOGIES, LLC
发明人： James Rathburn
IPC分类号： H05K3/02 , H05K3/10 , H05K1/18 , H05K3/46 , H05K1/02 , H05K1/16
CPC分类号： H05K1/181 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H05K1/0216 , H05K1/0256 , H05K1/0284 , H05K1/16 , H05K3/107 , H05K3/4664 , H05K3/4694 , H05K2201/0344 , H05K2201/10674 , H05K2201/10734 , Y10T29/49155 , H01L2924/00014
摘要： A high density region for a low density circuit. At least a first liquid dielectric layer is deposited on the first surface of a first circuitry layer. The dielectric layer is imaged to create plurality of first recesses. Surfaces of the first recesses are plated electro-lessly with a conductive material to form first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. A plating resist is applied. A conductive material is electro-plated to the first conductive structure to substantially fill the first recesses, and the plating resist is removed.

6. 发明授权

US09689897B2 Performance enhanced semiconductor socket 有权
公开(公告)号：US09689897B2
公开(公告)日：2017-06-27
申请号：US14565724
申请日：2014-12-10
申请人： HSIO TECHNOLOGIES, LLC
发明人： James Rathburn
IPC分类号： G01R1/04
CPC分类号： G01R1/0466 , Y10T29/49222
摘要： A test socket for IC devices includes a multi-layered socket housing with at least one center layer and first and second surface layers. The first and second surface layers have a thickness and dielectric constant less than that of the center layers. A plurality of contact members are located in center openings in the center layer with distal ends extending into openings in the first and second layers. The distal ends of the contact members having at least one dimension greater than the openings in the first and second surface layers to retain the contact members in the socket housing. The contact members include center portions with major diameters less than the diameters of the center openings, such that an air gap is maintained between the contact members and the center layer.

7. 发明授权

US09660368B2 High performance surface mount electrical interconnect 有权
公开(公告)号：US09660368B2
公开(公告)日：2017-05-23
申请号：US14621663
申请日：2015-02-13
申请人： HSIO TECHNOLOGIES, LLC
发明人： James Rathburn
IPC分类号： H01R12/00 , H01R12/70 , H01R12/57
CPC分类号： H01R12/7082 , H01R12/57 , Y10T29/4913 , Y10T29/49144 , Y10T29/49165
摘要： An interconnect assembly including a substrate with a plurality of through holes extending from a first surface to a second surface. A plurality of discrete contact member are located in the plurality of through holes. The contact members include proximal ends that are accessible from the second surface, distal ends extending above the first surface, and intermediate portions engaged with an engagement region of the substrate located between the first surface and the recesses. Retention members are coupled with at least a portion of the proximal ends to retain the contact members in the through holes. The retention members can be made from a variety of materials with different levels of conductivity, ranging from highly conductive to non-conductive.

8. 发明授权

US09536815B2 Semiconductor socket with direct selective metalization 有权
标题翻译：半导体插座具有直接选择性金属化
公开(公告)号：US09536815B2
公开(公告)日：2017-01-03
申请号：US14408338
申请日：2013-03-14
申请人： HSIO TECHNOLOGIES, LLC
发明人： James Rathburn
IPC分类号： H01R12/00 , H01L23/498 , H01L23/64 , H01L25/065 , H01L23/522 , H01L21/48 , H01L23/66 , H01L23/00 , H01L23/50
CPC分类号： H01L23/49811 , H01L21/4857 , H01L21/486 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/49861 , H01L23/50 , H01L23/5222 , H01L23/642 , H01L23/66 , H01L24/16 , H01L24/72 , H01L25/0657 , H01L2223/6616 , H01L2223/6666 , H01L2223/6677 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16227 , H01L2224/81192 , H01L2224/81385 , H01L2224/81801 , H01L2224/81901 , H01L2225/06517 , H01L2225/06527 , H01L2225/06531 , H01L2225/06572 , H01L2924/00014 , H01L2924/12042 , Y10T29/49204 , H01L2924/00 , H01L2224/05599
摘要： A semiconductor socket including a substrate with a plurality of through holes extending from a first surface to a second surface. A conductive structure is disposed within the through holes A plurality of discrete contact members are located in the plurality of the through holes, within the conductive structure. The plurality of contact members each include a proximal end accessible from the second surface, and a distal end extending above the first surface. The conductive structure can be electrically coupled to circuit geometry. At least one dielectric layer is bonded to the second surface of the substrate with recesses corresponding to desired circuit geometry. A conductive material deposited in at least a portion of the recesses to form conductive traces redistributing terminal pitch of the proximal ends of the contact members.
摘要翻译：一种半导体插座，包括具有从第一表面延伸到第二表面的多个通孔的基板。导电结构设置在通孔内，在导电结构内，多个离散接触构件位于多个通孔中。多个接触构件各自包括可从第二表面接近的近端和在第一表面上方延伸的远端。导电结构可以电耦合到电路几何形状。至少一个电介质层与基板的第二表面结合，凹槽对应于所需的电路几何形状。沉积在至少一部分凹陷中的导电材料以形成重新分布接触构件的近端的端子间距的导电迹线。

9. 发明申请

US20150181710A1 HYBRID PRINTED CIRCUIT ASSEMBLY WITH LOW DENSITY MAIN CORE AND EMBEDDED HIGH DENSITY CIRCUIT REGIONS 有权
标题翻译：低密度主芯片和嵌入式高密度电路区混合印刷电路组件
公开(公告)号：US20150181710A1
公开(公告)日：2015-06-25
申请号：US14408205
申请日：2013-03-13
申请人： HSIO TECHNOLOGIES, LLC
发明人： James Rathburn
IPC分类号： H05K1/18 , H05K3/10 , H05K1/02
CPC分类号： H05K1/181 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H05K1/0216 , H05K1/0256 , H05K1/0284 , H05K1/16 , H05K3/107 , H05K3/4664 , H05K3/4694 , H05K2201/0344 , H05K2201/10674 , H05K2201/10734 , Y10T29/49155 , H01L2924/00014
摘要： A high density region for a low density circuit. At least a first liquid dielectric layer is deposited on the first surface of a first circuitry layer. The dielectric layer is imaged to create plurality of first recesses. Surfaces of the first recesses are plated electro-lessly with a conductive material to form first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. A plating resist is applied. A conductive material is electro-plated to the first conductive structure to substantially fill the first recesses, and the plating resist is removed.
摘要翻译：低密度电路的高密度区域。至少第一液体介电层沉积在第一电路层的第一表面上。对电介质层进行成像以产生多个第一凹槽。第一凹槽的表面电镀不良地与导电材料电镀以形成电耦合到第一电路层并且大致垂直于第一电路层延伸的第一导电结构。应用电镀抗蚀剂。将导电材料电镀到第一导电结构以基本上填充第一凹部，并且去除电镀抗蚀剂。

10. 发明授权

US09350124B2 High speed circuit assembly with integral terminal and mating bias loading electrical connector assembly 有权
标题翻译：具有集成端子和配合偏置负载电连接器组件的高速电路组件
公开(公告)号：US09350124B2
公开(公告)日：2016-05-24
申请号：US14408039
申请日：2013-03-13
申请人： HSIO TECHNOLOGIES, LLC
发明人： James Rathburn
IPC分类号： H01R12/68 , H01R12/50 , H01R13/24 , H01R12/82 , H05K3/36 , H05K3/40 , H01R12/73 , H01L23/00 , H05K1/09 , H05K1/11 , H05K1/18 , H05K3/00 , H05K3/42 , H05K3/46
CPC分类号： H01R23/6813 , H01L24/16 , H01L24/48 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01R12/73 , H01R12/82 , H01R13/2457 , H01R13/2485 , H01R31/06 , H05K1/092 , H05K1/111 , H05K1/141 , H05K1/182 , H05K3/0094 , H05K3/10 , H05K3/1291 , H05K3/326 , H05K3/363 , H05K3/365 , H05K3/4007 , H05K3/4015 , H05K3/4092 , H05K3/425 , H05K3/4694 , H05K7/1076 , H05K2201/0397 , H05K2201/048 , H05K2201/09381 , H05K2201/09545 , H05K2201/09563 , H05K2201/09854 , H05K2201/10378 , H05K2201/10386 , H05K2201/2072 , H05K2201/209 , H05K2203/041 , H05K2203/1476 , Y10T29/49165 , H01L2224/45099 , H01L2924/00
摘要： A method of making an array of integral terminals on a circuit assembly. The method includes the steps of depositing at least a first liquid dielectric layer on the first surface of a first circuit member, imaged to include a plurality of first recesses corresponding to the array of integral terminals. The selected surfaces of the first recesses are processed to accept electro-less conductive plating deposition. Electro-lessly plating is applied to the selected surfaces of the first recesses to create a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. Electro-plating is applied to the electro-less plating to substantially first recesses with a conductive material. The steps of depositing, processing, electro-less plating, and electro-plating are repeated to form the integral terminals of a desired shape. The dielectric layers are removed to expose the terminals.
摘要翻译：一种在电路组件上制成集成端子阵列的方法。该方法包括以下步骤：在第一电路构件的第一表面上沉积至少第一液体电介质层，成像为包括与集成端子阵列相对应的多个第一凹部。处理第一凹槽的选定表面以接受无电导电电镀沉积。对所述第一凹槽的所选择的表面施加无电镀以产生电耦合到所述第一电路层并且大致垂直于所述第一电路层延伸的多个第一导电结构。使用导电材料将电镀施加到基本上第一凹部的无电镀。重复沉积，加工，无电镀和电镀的步骤以形成所需形状的整体端子。去除电介质层以露出端子。

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