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1. 发明申请

US20180270399A1 LOW LATENCY TEARING WITHOUT USER PERCEPTION 审中-公开
公开(公告)号：US20180270399A1
公开(公告)日：2018-09-20
申请号：US15628292
申请日：2017-06-20
申请人： Microsoft Technology Licensing, LLC
发明人： Bennett SORBO , Steve Pronovost
IPC分类号： H04N5/073 , H04N5/12
CPC分类号： H04N5/0736 , G02B27/0172 , G09G5/395 , G09G5/399 , G09G2320/0247 , H04N5/073 , H04N5/12 , H04N5/268
摘要： Methods and devices for presenting a virtual reality image may include rendering at least one image frame received from an application for a virtual reality image for display on a display device. The methods and devices may include receiving a selection of one of a plurality of tear thresholds that define conditions for tearing in a displayed image. The methods and devices may include determining whether the rendered frame is received prior to the selected one of the plurality of tear thresholds, wherein the selected one of the plurality of tear thresholds occurs after a frame timing event that corresponds to a deadline for initiating display of a new frame. The methods and device may include communicating the rendered image frame to the display device for presentation on the display device when the rendered frame is received prior to the selected one of the plurality of tear thresholds.

2. 发明授权

US10038827B2 Semiconductor device, electronic device module and network system 有权
公开(公告)号：US10038827B2
公开(公告)日：2018-07-31
申请号：US14928662
申请日：2015-10-30
申请人： Renesas Electronics Corporation
发明人： Yuichi Takitsune , Kazunori Masaki , Motoshige Ikeda
IPC分类号： H04N5/067 , H04N5/04 , H04N5/12
CPC分类号： H04N5/067 , H04N5/04 , H04N5/12
摘要： A semiconductor device includes an adjusting circuit that transmits a control signal to a device to be controlled according to a transmission cycle synchronized with a reference clock. The device to be controlled has a first period during which the control signal is allowed to be supplied to the device to be controlled and a second period during which the supplying of the control signal to the device to be controlled is not preferable compared to that in the first period. The adjusting circuit is configured to, when a transmission timing of the control signal determined according to the transmission cycle is within the second period, adjust the transmission timing of the control signal so that the control signal will be transmitted in the first period.

3. 发明授权

US09723182B2 Image transmitting/receiving system, image transmitting apparatus, received image displaying apparatus, wireless control apparatus, and image transmitting/receiving method 有权
公开(公告)号：US09723182B2
公开(公告)日：2017-08-01
申请号：US15141160
申请日：2016-04-28
申请人： OLYMPUS CORPORATION
发明人： Kiyoshi Toyoda , Shinya Kawasaki
IPC分类号： H04N5/12 , H04N21/43 , H04N21/4363 , H04N5/073 , G06F3/14
CPC分类号： H04N5/12 , G06F3/1423 , H04N5/0733 , H04N21/4307 , H04N21/43637
摘要： A received image displaying apparatus comprises: a wireless communication unit that wirelessly receives the frame images transmitted by the image transmitting apparatus with which the received image displaying apparatus has established a connection of wireless communication; and a displaying unit that displays the frame images, which were wirelessly received by the wireless communication unit, in an order in which the frame images were captured. At least one of the image transmitting apparatus and the received image displaying apparatus comprises: a reference sync signal generating unit that generates the reference sync signals; and a control unit that, if the wireless communication unit has received no reference sync signals for a certain time interval, controls the reference sync signal generating unit to generate reference sync signals and that further controls the wireless communication unit to wirelessly transmit the reference sync signals to the other apparatus included in the image transmitting/receiving system.

4. 发明授权

US07924964B2 Receiver with the function of adjusting clock signal and an adjusting method therefor 有权
标题翻译：具有调整时钟信号功能的接收机及其调整方法
公开(公告)号：US07924964B2
公开(公告)日：2011-04-12
申请号：US11882982
申请日：2007-08-08
申请人： Chao-Kuei Tseng , Shih-Ta Hsu
发明人： Chao-Kuei Tseng , Shih-Ta Hsu
IPC分类号： H03D3/24
CPC分类号： H04N5/4401 , H04N5/04 , H04N5/12 , H04N21/4305
摘要： A receiver having a first clock signal is provided. The first frequency of the first clock signal is adjusted to be close to a second frequency of a second clock signal of a transmitter. The receiver includes a clock generator, a processor and a controller. The clock generator is for generating the first clock signal. The processor is for outputting a first control signal to control the clock generator to adjust the first frequency to be close to the second frequency when an absolute value of a current difference between the first and the second frequencies at a current time point is larger than a threshold. The controller is for outputting a second control signal to control the clock generator when the absolute value of the current difference is smaller than the threshold, so as to reduce the load of the processor.
摘要翻译：提供具有第一时钟信号的接收机。第一时钟信号的第一频率被调整为接近发射机的第二时钟信号的第二频率。接收机包括时钟发生器，处理器和控制器。时钟发生器用于产生第一个时钟信号。当当前时间点的第一和第二频率之间的电流差的绝对值大于a时，处理器用于输出第一控制信号以控制时钟发生器以将第一频率调整为接近于第二频率阈。当电流差的绝对值小于阈值时，控制器用于输出第二控制信号以控制时钟发生器，从而减小处理器的负载。

5. 发明申请

US20070182850A1 APPARATUS FOR DETECTING SYNCHRONIZATION 失效
标题翻译：用于检测同步的装置
公开(公告)号：US20070182850A1
公开(公告)日：2007-08-09
申请号：US11671815
申请日：2007-02-06
申请人： E-woo Chon , Jae-hong Park , Woon Na , Hyung-jun Lim , Jae-hong Park , Sung-cheol Park , Mi-kyoung Seo , Eui-jin Kwon
发明人： E-woo Chon , Jae-hong Park , Woon Na , Hyung-jun Lim , Jae-hong Park , Sung-cheol Park , Mi-kyoung Seo , Eui-jin Kwon
IPC分类号： H04N5/06
CPC分类号： H04N5/04 , H04N5/12
摘要： A synchronization detecting apparatus includes a counter, an error detector, and a line length generator. The counter counts to a predetermined counter value in response to a clock signal. The error detector generates an error, which is the difference between a current counter value received from the counter and a previous line length, in response to a synchronization flag signal. The line length generator generates a current line length based on a compensated error and the predetermined counter value. The synchronization flag signal has an active level at a transitioning edge of a synchronization pulse signal contained in an input signal.
摘要翻译：同步检测装置包括计数器，误差检测器和线长度发生器。计数器响应于时钟信号计数到预定的计数器值。误差检测器响应于同步标记信号产生误差，其是从计数器接收的当前计数器值与前一行长度之间的差。线长发生器基于补偿误差和预定计数器值产生电流线路长度。同步标志信号在包含在输入信号中的同步脉冲信号的转变边缘处具有有效电平。

6. 发明申请

US20060232352A1 Timing generator 失效
公开(公告)号：US20060232352A1
公开(公告)日：2006-10-19
申请号：US10564940
申请日：2004-07-07
申请人： Jeffery Lendaro
发明人： Jeffery Lendaro
IPC分类号： H03C3/09 , H03C3/06
CPC分类号： H03K5/1252 , H03K5/19 , H04N5/06 , H04N5/12 , H04N5/123
摘要： A timing generator and method of developing drive signals which, when input sync signals are present, delivers the leading and trailing edges of the input pulses directly to a drive output and which generates a free-running signal when input sync pulses are not present.

7. 发明申请

US20060174294A1 Digital broadcasting receiver for receiving analog broadcasting and a method thereof 审中-公开
标题翻译：用于接收模拟广播的数字广播接收机及其方法
公开(公告)号：US20060174294A1
公开(公告)日：2006-08-03
申请号：US11319579
申请日：2005-12-29
申请人： Kyoung-su Kim , Jae-kyoung Shim
发明人： Kyoung-su Kim , Jae-kyoung Shim
IPC分类号： H04N7/173 , H04N7/16
CPC分类号： H04N5/46 , H04N5/08 , H04N5/12 , H04N5/4401 , H04N21/42638 , H04N21/488
摘要： A broadcasting receiver of a display receiver and method thereof receives a digital broadcasting signal and an analog broadcasting signal. A tuning unit selectively receives the digital and analog broadcasting signals. A processing unit processes the digital and analog broadcasting signals in accordance with the selection by said tuning unit, and includes an additional information processing unit to generate additional information corresponding to the digital and analog broadcast signals, and a video mix unit to selectively output the processed digital broadcasting signal with the additional information and the processed analog broadcasting signal with the additional information. The additional information corresponding to the digital broadcasting signal and the analog broadcasting signal are the same.
摘要翻译：显示接收机的广播接收机及其方法接收数字广播信号和模拟广播信号。调谐单元有选择地接收数字和模拟广播信号。处理单元根据所述调谐单元的选择来处理数字和模拟广播信号，并且包括附加信息处理单元以产生对应于数字和模拟广播信号的附加信息，以及视频混合单元，用于选择性地输出处理过的具有附加信息的数字广播信号和具有附加信息的经处理的模拟广播信号。对应于数字广播信号和模拟广播信号的附加信息是相同的。

8. 发明申请

US20040085309A1 Method and apparatus for coordinating horizontal and vertical synchronization signals 有权
标题翻译：用于协调水平和垂直同步信号的方法和装置
公开(公告)号：US20040085309A1
公开(公告)日：2004-05-06
申请号：US10287580
申请日：2002-11-05
申请人： Amtran Technology Co., Ltd.
发明人： Jui-Ming Wang , Chien-Chou Chen
IPC分类号： G09G005/00
CPC分类号： G09G5/006 , H04N5/12
摘要： In a signal coordinating method and apparatus, a pulse generating circuit receives a VSYNC signal and generates a plurality of critical pulses that define critical time periods from fields can control edges of the VSYNC signal. A determining circuit receives an HSYNC signal and the critical pulses, and generates a trigger signal upon detecting that a line scan control edge of the HSYNC signal appears during one of the critical time periods. A time delay loop introduces a time delay into the VSYNC signal upon receipt of the trigger signal to cause the critical time period to appear after the line scan control edge of the HSYNC signal.
摘要翻译：在信号协调方法和装置中，脉冲发生电路接收VSYNC信号并产生多个关键脉冲，其定义关键时间周期，从场可控制VSYNC信号的边沿。确定电路接收HSYNC信号和临界脉冲，并且在检测到HSYNC信号的行扫描控制边缘在一个关键时间段期间出现时产生触发信号。时间延迟循环在接收到触发信号时将延时引入VSYNC信号，以使临界时间段出现在HSYNC信号的行扫描控制沿之后。

9. 发明授权

US6005634A Method and apparatus for controlling the display of a video image 失效
标题翻译：控制视频图像显示的方法和装置
公开(公告)号：US6005634A
公开(公告)日：1999-12-21
申请号：US889805
申请日：1997-07-08
申请人： Kut Hing Lam , Kwok Ban Nip , Gerald Lunn
发明人： Kut Hing Lam , Kwok Ban Nip , Gerald Lunn
IPC分类号： H04N5/08 , G09G1/00 , G09G1/04 , H04N3/16 , H04N3/227 , H04N5/12
CPC分类号： G09G1/04 , H04N3/227 , H04N5/12 , H04N5/126
摘要： A control circuit (100) which receives horizontal synchronising pulses (265) and generates a horizontal drive output signal (455) for a cathode ray tube (CRT) display. The horizontal control circuit (100) generates two ramp signals. A first ramp signal (410) for horizontal position adjustment of an image on the CRT display, and a second ramp signal (440) for propagation delay compensation of a deflection circuit (155) coupled to the CRT display. The control circuit (100) also provides digital of control of the duty cycle of the horizontal drive signal (455).
摘要翻译：一种接收水平同步脉冲（265）并产生阴极射线管（CRT）显示器的水平驱动输出信号（455）的控制电路（100）。水平控制电路（100）产生两个斜坡信号。用于CRT显示器上的图像的水平位置调整的第一斜坡信号（410）和用于耦合到CRT显示器的偏转电路（155）的传播延迟补偿的第二斜坡信号（440）。控制电路（100）还提供水平驱动信号（455）占空比的控制数字。

10. 发明授权

US5889421A Device for detecting the locking of an automatic gain control circuit 失效
标题翻译：用于检测自动增益控制电路的锁定的装置
公开(公告)号：US5889421A
公开(公告)日：1999-03-30
申请号：US922612
申请日：1997-09-03
申请人： Eric Cirot , Nicolas Lebouleux
发明人： Eric Cirot , Nicolas Lebouleux
IPC分类号： H03L5/00 , H04N5/12 , H03L7/00
CPC分类号： H03L5/00 , H04N5/12
摘要： The present invention relates to a device for detecting the locking of an automatic gain control circuit, the automatic gain control circuit receiving a signal to be regulated, a check signal and a sampling control signal for driving the operation of the circuit. The detection device includes a comparator receiving the check signal and the signal to be regulated or a signal representative of the signal to be regulated. The comparator generates two logic signals, the states of which form a specific combination of logic states when the value of the signal to be regulated is in a range of values including the value of the check signal. A logic comparator circuit generates a logic comparison signal, the state of which is representative of the presence or absence of this specific combination, and a storage means, driven by the sampling control signal, stores the state of the signal provided by the logic circuit.
摘要翻译：本发明涉及一种用于检测自动增益控制电路的锁定的装置，接收待调节信号的自动增益控制电路，用于驱动电路的操作的检查信号和采样控制信号。检测装置包括比较器，其接收检查信号和被调节信号，或者表示要被调节的信号的信号。比较器产生两个逻辑信号，当待调节信号的值在检测信号的值的范围内时，其状态形成逻辑状态的特定组合。逻辑比较器电路产生逻辑比较信号，其状态代表该特定组合的存在或不存在，并且由采样控制信号驱动的存储装置存储由逻辑电路提供的信号的状态。

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