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1. 发明申请

US20090041091A1 Receiver with the function of adjusting clock signal and an adjusting method therefor 有权
标题翻译：具有调整时钟信号功能的接收机及其调整方法
公开(公告)号：US20090041091A1
公开(公告)日：2009-02-12
申请号：US11882982
申请日：2007-08-08
申请人： Chao-Kuei Tseng , Shih-Ta Hsu
发明人： Chao-Kuei Tseng , Shih-Ta Hsu
IPC分类号： H04B1/707
CPC分类号： H04N5/4401 , H04N5/04 , H04N5/12 , H04N21/4305
摘要： A receiver having a first clock signal is provided. The first frequency of the first clock signal is adjusted to be close to a second frequency of a second clock signal of a transmitter. The receiver includes a clock generator, a processor and a controller. The clock generator is for generating the first clock signal. The processor is for outputting a first control signal to control the clock generator to adjust the first frequency to be close to the second frequency when an absolute value of a current difference between the first and the second frequencies at a current time point is larger than a threshold. The controller is for outputting a second control signal to control the clock generator when the absolute value of the current difference is smaller than the threshold, so as to reduce the load of the processor.
摘要翻译：提供具有第一时钟信号的接收机。第一时钟信号的第一频率被调整为接近发射机的第二时钟信号的第二频率。接收机包括时钟发生器，处理器和控制器。时钟发生器用于产生第一个时钟信号。当当前时间点的第一和第二频率之间的电流差的绝对值大于a时，处理器用于输出第一控制信号以控制时钟发生器以将第一频率调整为接近于第二频率阈。当电流差的绝对值小于阈值时，控制器用于输出第二控制信号以控制时钟发生器，从而减小处理器的负载。

2. 发明授权

US07924964B2 Receiver with the function of adjusting clock signal and an adjusting method therefor 有权
标题翻译：具有调整时钟信号功能的接收机及其调整方法
公开(公告)号：US07924964B2
公开(公告)日：2011-04-12
申请号：US11882982
申请日：2007-08-08
申请人： Chao-Kuei Tseng , Shih-Ta Hsu
发明人： Chao-Kuei Tseng , Shih-Ta Hsu
IPC分类号： H03D3/24
CPC分类号： H04N5/4401 , H04N5/04 , H04N5/12 , H04N21/4305
摘要： A receiver having a first clock signal is provided. The first frequency of the first clock signal is adjusted to be close to a second frequency of a second clock signal of a transmitter. The receiver includes a clock generator, a processor and a controller. The clock generator is for generating the first clock signal. The processor is for outputting a first control signal to control the clock generator to adjust the first frequency to be close to the second frequency when an absolute value of a current difference between the first and the second frequencies at a current time point is larger than a threshold. The controller is for outputting a second control signal to control the clock generator when the absolute value of the current difference is smaller than the threshold, so as to reduce the load of the processor.
摘要翻译：提供具有第一时钟信号的接收机。第一时钟信号的第一频率被调整为接近发射机的第二时钟信号的第二频率。接收机包括时钟发生器，处理器和控制器。时钟发生器用于产生第一个时钟信号。当当前时间点的第一和第二频率之间的电流差的绝对值大于a时，处理器用于输出第一控制信号以控制时钟发生器以将第一频率调整为接近于第二频率阈。当电流差的绝对值小于阈值时，控制器用于输出第二控制信号以控制时钟发生器，从而减小处理器的负载。

3. 发明申请

US20090225768A1 CENTRALIZED TS PACKET BUFFER MANAGEMENT IN MULTIPLE TRANSPORT STREAM MPEG-2 DEMUX 审中-公开
标题翻译：多媒体传输流MPEG-2 DEMUX中的TS包缓冲区管理
公开(公告)号：US20090225768A1
公开(公告)日：2009-09-10
申请号：US12043824
申请日：2008-03-06
申请人： Shih-Ta Hsu , Bo-Ting Lin
发明人： Shih-Ta Hsu , Bo-Ting Lin
IPC分类号： H04L12/56
CPC分类号： H04N21/440281 , H04N21/42615 , H04N21/4305 , H04N21/434 , H04N21/44004
摘要： A de-multiplexer is disclosed. A transport stream de-multiplexer includes a plurality of input buffers (211-21N) each receiving bytes from a plurality of packets in a corresponding transport stream, a main buffer (230) for temporal storage of said packets and an input arbiter temporally allotting a space of at least one packet in the main buffer to one of said packets when receiving a request to store a first byte of said packets into said main buffer.
摘要翻译：公开了解复用器。传输流解复用器包括多个输入缓冲器（211-21N），每个输入缓冲器从相应传输流中的多个分组接收字节;主缓冲器（230），用于暂时存储所述分组;以及输入仲裁器，其在时间上分配当接收到将所述分组的第一字节存储到所述主缓冲器中的请求时，主缓冲器中的至少一个分组的空间到所述分组之一。

4. 发明申请

US20090238069A1 DEVICE AND METHOD FOR CONTROLLING PROGRAM STREAM FLOW 审中-公开
标题翻译：用于控制程序流流量的装置和方法
公开(公告)号：US20090238069A1
公开(公告)日：2009-09-24
申请号：US12051751
申请日：2008-03-19
申请人： Bo-Ting Lin , Shih-Ta Hsu
发明人： Bo-Ting Lin , Shih-Ta Hsu
IPC分类号： G01R31/08
CPC分类号： G06F9/3824 , G06F13/28 , Y02D10/14
摘要： A device for controlling program stream flow is described. The device is capable of saving power during computation. The device may include a de-multiplex unit and a direct memory access controller. The de-multiplex unit, for de-multiplexing a plurality of data, may include a request module for generating a request signal. The direct memory access controller is for receiving the request signal. The direct memory access controller obtains a plurality of data from a bus and sends the plurality of data to the de-multiplex unit according to the request signal.
摘要翻译：描述用于控制节目流流的设备。该设备在计算过程中能够节省电力。该设备可以包括解复用单元和直接存储器访问控制器。用于解复用多个数据的解复用单元可以包括用于生成请求信号的请求模块。直接存储器存取控制器用于接收请求信号。直接存储器访问控制器从总线获取多个数据，并根据请求信号将多个数据发送到解复用单元。

5. 发明授权

US08498341B2 Decoder and operation method thereof 有权
标题翻译：解码器及其操作方法
公开(公告)号：US08498341B2
公开(公告)日：2013-07-30
申请号：US11861816
申请日：2007-09-26
申请人： Po-Ting Lin , Shih-Ta Hsu
发明人： Po-Ting Lin , Shih-Ta Hsu
IPC分类号： H04B1/66
CPC分类号： H04N21/435 , H04N21/235 , H04N21/4345
摘要： A decoder and an operation method thereof are provided. The decoder includes a pre-unit, a database, a data filter, and a scheduler. The pre-unit provides packet information of a data stream. The database records a plurality of parameter sets. The scheduler fetches the corresponding parameter sets from the database according to the packet information, and saves the parameter sets into the data filter. The data filter compares the data stream with the saved parameter sets and outputs a comparing result. Therefore, the present invention reduces the cost of the decoder.
摘要翻译：提供了解码器及其操作方法。解码器包括预单元，数据库，数据过滤器和调度器。预单元提供数据流的分组信息。数据库记录多个参数集。调度器根据分组信息从数据库中取出相应的参数集，并将参数集保存到数据过滤器中。数据过滤器将数据流与保存的参数集进行比较，并输出比较结果。因此，本发明降低了解码器的成本。

6. 发明申请

US20090041127A1 FLEXIBLE LENGTH DECODER 审中-公开
标题翻译：灵活长度解码器
公开(公告)号：US20090041127A1
公开(公告)日：2009-02-12
申请号：US11854332
申请日：2007-09-12
申请人： Po-Ting Lin , Shih-Ta Hsu
发明人： Po-Ting Lin , Shih-Ta Hsu
IPC分类号： H04N7/26
CPC分类号： H04N21/435 , H04N21/235 , H04N21/2368 , H04N21/42615 , H04N21/434 , H04N21/4341 , H04N21/4345 , H04N21/44008 , H04N21/8106
摘要： A flexible length decoder including a plurality of data filter units and a control unit is provided. The data filter units perform a comparing operation on a data stream according its corresponding pattern and output a comparing result. The control unit controls the configurations of the data filter units. If the space of any one of the data filter units for storing the pattern is not enough to record the required pattern, the control unit combines two or more data filter units into an equivalent data filter unit, such that the equivalent data filter unit stores the pattern and performs the comparing operation.
摘要翻译：提供了包括多个数据滤波器单元和控制单元的灵活长度解码器。数据滤波器单元根据其对应的模式对数据流进行比较操作，并输出比较结果。控制单元控制数据滤波器单元的配置。如果用于存储图案的任何一个数据滤波器单元的空间不足以记录所需的图案，则控制单元将两个或更多个数据滤波器单元组合成等效数据滤波器单元，使得等效数据滤波器单元存储模式并执行比较操作。

7. 发明申请

US20090074376A1 APPARATUS AND METHOD FOR EFFICIENT AV SYNCHRONIZATION 审中-公开
标题翻译：用于高效AV同步的装置和方法
公开(公告)号：US20090074376A1
公开(公告)日：2009-03-19
申请号：US11856477
申请日：2007-09-17
申请人： Po-Ting Lin , Shih-Ta Hsu
发明人： Po-Ting Lin , Shih-Ta Hsu
IPC分类号： H04N5/91
CPC分类号： H04N9/8042 , H04N9/8211
摘要： An apparatus and a method for an efficient audio/video (AV) synchronization are provided. The apparatus includes a parser, a frame memory, a video start code (VSC) detector and a video decoder. The parser is used for analyzing a packetized elementary stream (PES) and outputting a video stream, an address information and at least one time stamp, in which the video stream includes a frame and at least one VSC corresponding to the frame. The frame memory is used for temporarily storing the video stream according to the address information. The VSC detector is used for retrieving the VSC of the video stream. The video decoder is used for selecting the frame from the frame memory according to the VSC and the address information provided by the VSC detector.
摘要翻译：提供了一种用于高效音频/视频（AV）同步的装置和方法。该装置包括解析器，帧存储器，视频起始码（VSC）检测器和视频解码器。解析器用于分析分组化基本流（PES）并输出视频流，地址信息和至少一个时间戳，其中视频流包括帧和至少一个对应于该帧的VSC。帧存储器用于根据地址信息临时存储视频流。 VSC检测器用于检索视频流的VSC。视频解码器用于根据VSC和由VSC检测器提供的地址信息从帧存储器中选择帧。

8. 发明申请

US20090043787A1 DECODER AND OPERATION METHOD THEREOF 有权
标题翻译：解码器及其操作方法
公开(公告)号：US20090043787A1
公开(公告)日：2009-02-12
申请号：US11861816
申请日：2007-09-26
申请人： Po-Ting Lin , Shih-Ta Hsu
发明人： Po-Ting Lin , Shih-Ta Hsu
IPC分类号： G06F17/30
CPC分类号： H04N21/435 , H04N21/235 , H04N21/4345
摘要： A decoder and an operation method thereof are provided. The decoder includes a pre-unit, a database, a data filter, and a scheduler. The pre-unit provides packet information of a data stream. The database records a plurality of parameter sets. The scheduler fetches the corresponding parameter sets from the database according to the packet information, and saves the parameter sets into the data filter. The data filter compares the data stream with the saved parameter sets and outputs a comparing result. Therefore, the present invention reduces the cost of the decoder.
摘要翻译：提供了解码器及其操作方法。解码器包括预单元，数据库，数据过滤器和调度器。预单元提供数据流的分组信息。数据库记录多个参数集。调度器根据分组信息从数据库中取出相应的参数集，并将参数集保存到数据过滤器中。数据过滤器将数据流与保存的参数集进行比较，并输出比较结果。因此，本发明降低了解码器的成本。

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