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1. 发明申请

US20090041091A1 Receiver with the function of adjusting clock signal and an adjusting method therefor 有权
标题翻译：具有调整时钟信号功能的接收机及其调整方法
公开(公告)号：US20090041091A1
公开(公告)日：2009-02-12
申请号：US11882982
申请日：2007-08-08
申请人： Chao-Kuei Tseng , Shih-Ta Hsu
发明人： Chao-Kuei Tseng , Shih-Ta Hsu
IPC分类号： H04B1/707
CPC分类号： H04N5/4401 , H04N5/04 , H04N5/12 , H04N21/4305
摘要： A receiver having a first clock signal is provided. The first frequency of the first clock signal is adjusted to be close to a second frequency of a second clock signal of a transmitter. The receiver includes a clock generator, a processor and a controller. The clock generator is for generating the first clock signal. The processor is for outputting a first control signal to control the clock generator to adjust the first frequency to be close to the second frequency when an absolute value of a current difference between the first and the second frequencies at a current time point is larger than a threshold. The controller is for outputting a second control signal to control the clock generator when the absolute value of the current difference is smaller than the threshold, so as to reduce the load of the processor.
摘要翻译：提供具有第一时钟信号的接收机。第一时钟信号的第一频率被调整为接近发射机的第二时钟信号的第二频率。接收机包括时钟发生器，处理器和控制器。时钟发生器用于产生第一个时钟信号。当当前时间点的第一和第二频率之间的电流差的绝对值大于a时，处理器用于输出第一控制信号以控制时钟发生器以将第一频率调整为接近于第二频率阈。当电流差的绝对值小于阈值时，控制器用于输出第二控制信号以控制时钟发生器，从而减小处理器的负载。

2. 发明申请

US20100231788A1 PLAYBACK SYSTEM AND METHOD SYNCHRONIZING AUDIO AND VIDEO SIGNALS 审中-公开
标题翻译：播放系统和方法同步音频和视频信号
公开(公告)号：US20100231788A1
公开(公告)日：2010-09-16
申请号：US12401625
申请日：2009-03-11
申请人： Chao-Kuei Tseng , Lin-Kai Bu
发明人： Chao-Kuei Tseng , Lin-Kai Bu
IPC分类号： H04N9/475 , H04N7/26
CPC分类号： H04N19/44
摘要： A playback system that utilizes a serial link for transmitting video and audio data from a host to a playback device includes a host and a playback device. The host is utilized to generating graphic packets, video packets, and audio packets according to input data, and to generating control packets according to a host clock. Then, the host transmits the packets through a serial port, wherein the graphic packets are transmitted only when the host receives a request. The playback device is coupled to the host via the serial port, and is implemented to decoding the received packets from the serial port to generate decoded data, and to generate a playback clock according to the control packets. Then the playback device performs a playback operation according to the decoded data and the playback clock.
摘要翻译：利用串行链路从主机向播放设备发送视频和音频数据的播放系统包括主机和播放设备。该主机用于根据输入数据产生图形数据包，视频数据包和音频数据包，并根据主机时钟产生控制数据包。然后，主机通过串行端口发送数据包，其中仅当主机接收到请求时才传输图形数据包。播放装置经由串行端口耦合到主机，并且被实现为从串行端口对接收的分组进行解码以产生解码的数据，并根据控制分组生成重放时钟。然后，重放装置根据解码数据和重放时钟执行重放操作。

3. 发明授权

US07924964B2 Receiver with the function of adjusting clock signal and an adjusting method therefor 有权
标题翻译：具有调整时钟信号功能的接收机及其调整方法
公开(公告)号：US07924964B2
公开(公告)日：2011-04-12
申请号：US11882982
申请日：2007-08-08
申请人： Chao-Kuei Tseng , Shih-Ta Hsu
发明人： Chao-Kuei Tseng , Shih-Ta Hsu
IPC分类号： H03D3/24
CPC分类号： H04N5/4401 , H04N5/04 , H04N5/12 , H04N21/4305
摘要： A receiver having a first clock signal is provided. The first frequency of the first clock signal is adjusted to be close to a second frequency of a second clock signal of a transmitter. The receiver includes a clock generator, a processor and a controller. The clock generator is for generating the first clock signal. The processor is for outputting a first control signal to control the clock generator to adjust the first frequency to be close to the second frequency when an absolute value of a current difference between the first and the second frequencies at a current time point is larger than a threshold. The controller is for outputting a second control signal to control the clock generator when the absolute value of the current difference is smaller than the threshold, so as to reduce the load of the processor.
摘要翻译：提供具有第一时钟信号的接收机。第一时钟信号的第一频率被调整为接近发射机的第二时钟信号的第二频率。接收机包括时钟发生器，处理器和控制器。时钟发生器用于产生第一个时钟信号。当当前时间点的第一和第二频率之间的电流差的绝对值大于a时，处理器用于输出第一控制信号以控制时钟发生器以将第一频率调整为接近于第二频率阈。当电流差的绝对值小于阈值时，控制器用于输出第二控制信号以控制时钟发生器，从而减小处理器的负载。

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