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1. 发明授权

US06992606B2 Method and circuit for multi-standard sigma-delta modulator 有权
标题翻译：多标准Σ-Δ调制器的方法和电路
公开(公告)号：US06992606B2
公开(公告)日：2006-01-31
申请号：US10865275
申请日：2004-06-10
申请人： Thomas Nicholas Zogakis , Himamshu G. Khasnis , Baireddy Vijayavardhan
发明人： Thomas Nicholas Zogakis , Himamshu G. Khasnis , Baireddy Vijayavardhan
IPC分类号： H03M1/20 , H03M3/00
CPC分类号： H03M7/3008 , H03M7/3011 , H03M7/3028 , H03M7/3035 , H03M7/304
摘要： System and method for a multi-standard sigma-delta modulator. A preferred embodiment comprises an integrator coupled to a signal input, wherein the integrator is configured to sum a difference between an input signal and an output of the sigma-delta modulator. A dithering circuit, also coupled to the signal input, is used to produce a dithering sequence. A summing point combines an output of the integrator and the dithering circuit while a quantizer converts the combined outputs into one of several discrete levels. The sigma-delta modulator further comprises a reset circuit to reset the sigma-delta modulator if the integrator becomes saturated. The sigma-delta modulator, as described, is compatible with G.Lite, ADSL, and ADSL+ variants of the digital subscriber line technical standards.
摘要翻译：用于多标准Σ-Δ调制器的系统和方法。优选实施例包括耦合到信号输入的积分器，其中积分器被配置为对输入信号和Σ-Δ调制器的输出之间的差进行求和。也耦合到信号输入端的抖动电路用于产生抖动序列。求和点将积分器和抖动电路的输出相结合，而量化器将组合的输出转换成几个离散电平之一。 Σ-Δ调制器还包括复位电路，以便在积分器变饱和时复位Σ-Δ调制器。所描述的Σ-Δ调制器与数字用户线技术标准的G.Lite，ADSL和ADSL +变体兼容。

2. 发明授权

US06993099B2 Communications receiver architectures and algorithms permitting hardware adjustments for optimizing performance 有权
公开(公告)号：US06993099B2
公开(公告)日：2006-01-31
申请号：US10011203
申请日：2001-11-07
申请人： Thomas Nicholas Zogakis , Michael Locke , Brian Robert Wiese
发明人： Thomas Nicholas Zogakis , Michael Locke , Brian Robert Wiese
IPC分类号： H04L27/06
CPC分类号： H03G1/0088 , H04L27/08
摘要： A receiver architecture featuring a decimation filter and a bypass around said decimation filter is disclosed along with a method for optimizing said receiver's sampling phase and programmable gain amplifier. Said method utilizes said receiver architecture to modify said receiver's receive path to simplify optimizations.

3. 发明授权

US07499505B2 Trellis decoding with finite constellation boundaries 有权
标题翻译：网格解码有限的星座边界
公开(公告)号：US07499505B2
公开(公告)日：2009-03-03
申请号：US10740251
申请日：2003-12-18
申请人： Thomas Nicholas Zogakis
发明人： Thomas Nicholas Zogakis
IPC分类号： H04L27/00
CPC分类号： H04L27/3416 , H04L27/38
摘要： System and method for improving trellis decoding in communications systems with finite constellation boundaries. A preferred embodiment for a received point of a tone when the tone represents a number of bits greater than three comprises determining if a received point lies outside of a specified region, wherein the specified region is dependent upon the number of bits, and transforming the received point if the received point lies outside of the specified region. The transformation moves the received point onto a boundary of the specified region, which can help in the correct decoding of the received point.
摘要翻译：用于改善具有有限星座边界的通信系统中的网格解码的系统和方法。当音调表示大于3的位数时，用于接收到的音调点的优选实施例包括确定接收点是否位于指定区域之外，其中指定区域取决于位数，并且变换所接收的如果接收点位于指定区域之外。该转换将接收点移动到指定区域的边界上，这有助于对接收点的正确解码。

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