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1. 发明授权

US07532138B2 Delta-sigma modulator and DA converter apparatus including delta-sigma modulator changing order of filter 有权
标题翻译： Δ-Σ调制器和DA转换器装置包括Δ-Σ调制器改变滤波器的阶数
公开(公告)号：US07532138B2
公开(公告)日：2009-05-12
申请号：US12035344
申请日：2008-02-21
申请人： Taiji Akizuki , Tomoaki Maeda , Masahiko Sagisaka
发明人： Taiji Akizuki , Tomoaki Maeda , Masahiko Sagisaka
IPC分类号： H03M3/00
CPC分类号： H03M3/394 , H03M3/422 , H03M3/454 , H03M7/3015 , H03M7/3024 , H03M7/304
摘要： In a delta-sigma modulator including first and second subtractors, first and second integrators, a quantizer, and a DA converter, a first feedback circuit includes first charge holding circuits which hold charges of the analog signal from the DA converter for different sampling intervals, can change a feedback amount of the analog signal from the DA converter, and outputs the analog signal from each first charge holding circuits to the second subtractor. A second feedback circuit includes second charge holding circuits which hold charges of the analog signal from the second integrator for different sampling intervals, can change a feedback amount of the analog signal from the second integrator, and outputs an analog signal from each of the second charge holding circuits to the second subtractor. A controller switches an order of filter characteristic of the delta sigma modulator by changing feedback amounts of the first and second feedback circuits.
摘要翻译：在包括第一和第二减法器的Δ-Σ调制器中，第一和第二积分器，量化器和DA转换器，第一反馈电路包括第一电荷保持电路，其保持来自DA转换器的模拟信号的电荷用于不同的采样间隔，可以改变来自DA转换器的模拟信号的反馈量，并将来自每个第一电荷保持电路的模拟信号输出到第二减法器。第二反馈电路包括第二电荷保持电路，其保持来自第二积分器的模拟信号的电荷用于不同的采样间隔，可以改变来自第二积分器的模拟信号的反馈量，并且从第二电荷中的每一个输出模拟信号保持电路到第二减法器。控制器通过改变第一和第二反馈电路的反馈量来切换Δ-Σ调制器的滤波器特性的顺序。

2. 发明授权

US07146144B2 Frequency agile exciter 有权
标题翻译：频率敏捷激励器
公开(公告)号：US07146144B2
公开(公告)日：2006-12-05
申请号：US10689296
申请日：2003-10-20
申请人： Ian Robinson , Jack Macek , Frank Winter
发明人： Ian Robinson , Jack Macek , Frank Winter
IPC分类号： H04B7/00 , H04B1/06 , H04B1/26
CPC分类号： H03M3/50 , H03M7/3017 , H03M7/3024
摘要： Systems and methods are provided for providing high dynamic range operation over a variable range of frequencies. A delta-sigma modulator, having associated frequency characteristics, produces a digital output signal. A digital-to-analog converter converts the digital output signal into an analog signal. A clock circuit provides a clock signal to the delta-sigma modulator and the digital-to-analog converter. A frequency control controls one or more of the clock circuit, the delta-sigma modulator, and the digital-to-analog converter to alter the frequency characteristics of the delta-sigma modulator. A filter circuit can provide one or more passbands to one or more downstream amplifiers ensuring that out of band quantization noise is removed before amplification.
摘要翻译：提供了用于在可变频率范围内提供高动态范围操作的系统和方法。具有相关频率特性的Δ-Σ调制器产生数字输出信号。数模转换器将数字输出信号转换为模拟信号。时钟电路向Δ-Σ调制器和数模转换器提供时钟信号。频率控制控制时钟电路，Δ-Σ调制器和数 - 模转换器中的一个或多个以改变Δ-Σ调制器的频率特性。滤波器电路可以向一个或多个下游放大器提供一个或多个通带，确保在放大之前去除带外量化噪声。

3. 发明授权

US06879275B1 Signal processing with a look-ahead modulator having time weighted error values 失效
标题翻译：具有时间加权误差值的先行调制器的信号处理
公开(公告)号：US06879275B1
公开(公告)日：2005-04-12
申请号：US10875920
申请日：2004-06-24
申请人： John L. Melanson
发明人： John L. Melanson
IPC分类号： H03M3/00 , H03M7/32
CPC分类号： H03M7/3011 , H03M7/3024
摘要： A signal processing system includes a look-ahead delta sigma modulator that processes multiple output candidate vectors and an input vector to determine an error vector for each output candidate vector. The error vector is weighted by a weight vector. The weight vector includes, for example, at least one non-unity, non-zero weight element that is different from another weight element to obtain lower signal-to-noise ratios than conventional look-ahead delta-sigma modulators while maintaining linearity associated with the conventional look-ahead delta-sigma modulators. The magnitudes of the weight vector can follow any window function.
摘要翻译：信号处理系统包括处理多个输出候选向量的前瞻delta-Σ调制器和输入向量，以确定每个输出候选向量的误差向量。误差向量由权重向量加权。权重向量包括例如至少一个不同于另一个权重元素的非一体非零权重元素，以获得比传统前瞻delta-sigma调制器更低的信噪比，同时保持与传统的前瞻delta-Σ调制器。权重向量的大小可以跟随任何窗口函数。

4. 发明授权

US08633842B2 Methods and apparatus for direct synthesis of RF signals using delta-sigma modulator 有权
标题翻译：使用Δ-Σ调制器直接合成RF信号的方法和装置
公开(公告)号：US08633842B2
公开(公告)日：2014-01-21
申请号：US13254397
申请日：2009-03-31
申请人： Kameran Azadet , Samer Hijazi , Joseph H. Othmer
发明人： Kameran Azadet , Samer Hijazi , Joseph H. Othmer
IPC分类号： H03M3/00
CPC分类号： H03M7/3042 , H03M7/3024
摘要： Methods and apparatus are provided for direct synthesis of RF signals using a delta-sigma modulator. An RF signal is synthesized from an input signal by quantizing the input signal using a quantizer, such as a one bit quantizer; determining a quantization error associated with the quantizer; generating an error prediction value using an error predictive filter, wherein the error predictive filter comprises one or more filter zeroes on a unit circle for one or more desired frequencies of f1, f2, . . . fn and one or more filter poles having a magnitude inside the unit circle and a frequency substantially equal to the one or more desired frequencies of f1, f2, . . . fn; and subtracting the error prediction value from the input signal. The filter poles have a magnitude that reduces a boost provided out-of-band.
摘要翻译：提供了使用Δ-Σ调制器直接合成RF信号的方法和装置。通过使用诸如一位量化器的量化器量化输入信号，从输入信号合成RF信号; 确定与所述量化器相关联的量化误差; 使用误差预测滤波器生成误差预测值，其中所述误差预测滤波器包括在f1，f2的一个或多个期望频率的单位圆上的一个或多个滤波器零点。。。 fn和一个或多个具有在单位圆内的幅度的滤波器极，并且频率基本上等于f1，f2的一个或多个期望频率。。。 fn 并从输入信号中减去误差预测值。滤波器极具有降低带外提升的幅度。

5. 发明授权

US07859444B2 D-A converter and D-A converting method 有权
标题翻译： D-A转换器和D-A转换方法
公开(公告)号：US07859444B2
公开(公告)日：2010-12-28
申请号：US12512958
申请日：2009-07-30
申请人： Kazuhiro Yamamoto , Toshiyuki Okayasu
发明人： Kazuhiro Yamamoto , Toshiyuki Okayasu
IPC分类号： H03M1/66
CPC分类号： H03M3/51 , H03M3/502 , H03M7/3024 , H03M7/3031
摘要： Provided is a DA converter that converts an input digital signal into an analog signal, comprising an integrator that outputs an integration value of the digital signal for each cycle of a constant period; a level comparing section that makes a comparison to detect whether the integration value output by the integrator is in an excessive state of being greater than a prescribed reference value; a feedback section that subtracts a predetermined value from the integration value, based on the comparison result from the level comparing section; a timing information generating section that generates, for each cycle, timing information of a change point, at which a transition to the excessive state occurs, with units of temporal resolution shorter than the constant period, based on the integration value output by the integrator for the cycle and the integration value output by the integrator for an immediately prior cycle; a timing generating section that generates a pulse signal with units of temporal resolution shorter than the constant period based on the timing information; and a signal processing section that generates the analog signal based on the pulse signal.
摘要翻译：提供了一种将输入数字信号转换为模拟信号的DA转换器，包括：对于恒定周期的每个周期输出数字信号的积分值的积分器; 电平比较部，进行比较以检测积分器输出的积分值是否处于大于规定基准值的过度状态; 基于来自所述电平比较部的比较结果，从所述积分值中减去预定值的反馈部; 定时信息生成部，基于积分器输出的积分值，对于每个周期，基于积分器输出的积分值，生成以过渡状态发生的变化点的定时信息，其中时间分辨率比恒定周期短积分器输出的循环和积分值用于紧接在前的循环; 定时生成部，其基于所述定时信息，生成具有比所述恒定周期短的时间分辨单位的脉冲信号; 以及基于脉冲信号生成模拟信号的信号处理部。

6. 发明申请

US20060233234A1 Tri-state pulse density modulator 有权
标题翻译：三态脉冲密度调制器
公开(公告)号：US20060233234A1
公开(公告)日：2006-10-19
申请号：US11107686
申请日：2005-04-15
申请人： Meoung-Jin Lim
发明人： Meoung-Jin Lim
IPC分类号： H03K9/04
CPC分类号： H03K7/08 , G06F1/022 , H03F3/217 , H03F2200/345 , H03M7/3024 , H03M7/3031
摘要： A tri-state pulse density modulator includes a first switch device coupled to a high voltage, and a second switch device coupled to a low voltage. An adder receives a pulse density modulation (PDM) input signal and a latched input signal to generate an output sum signal and a carry signal. A latch module coupled with the adder latches the output sum signal with a clock signal to generate the latched input signal. A control circuit module responsive to the carry signal for selectively turns off the first and second switch devices to generate the PDM output signal at a tri-state voltage between the first and second voltages, or turns on the first or second switch device to generate the PDM output signal at the first or second voltage, respectively. Thus, the PDM output signal only switches between the tri-state voltage and either the first voltage or the second voltage.
摘要翻译：三态脉冲密度调制器包括耦合到高电压的第一开关器件和耦合到低电压的第二开关器件。加法器接收脉冲密度调制（PDM）输入信号和锁存的输入信号，以产生输出和信号和进位信号。与加法器耦合的锁存模块将输出和信号与时钟信号锁存以产生锁存的输入信号。响应于进位信号的控制电路模块选择性地关闭第一和第二开关装置，以在第一和第二电压之间的三态电压下产生PDM输出信号，或者打开第一或第二开关装置以产生 PDM输出信号分别为第一或第二电压。因此，PDM输出信号仅在三态电压和第一电压或第二电压之间切换。

7. 发明申请

US20060028364A1 Analog signal generation using a delta-sigma modulator 有权
标题翻译：使用Δ-Σ调制器的模拟信号生成
公开(公告)号：US20060028364A1
公开(公告)日：2006-02-09
申请号：US11197252
申请日：2005-08-04
申请人： Jochen Rivoir
发明人： Jochen Rivoir
IPC分类号： H03M3/00
CPC分类号： H03M7/3013 , H03M3/344 , H03M3/50 , H03M7/3024 , H03M7/3031
摘要： A method for generating an analog signal based on samples representing the analog signal, includes feeding the samples into a delta-sigma modulator, the delta-sigma modulator outputting a sequence of bits, and introducing a non-linear time-discrete function into a feedback loop between a quantizer element and a delta element of the delta-sigma modulator, where arguments of the non-linear time-discrete function include a current bit and at least one bit previous to the current bit.
摘要翻译：一种用于基于表示模拟信号的样本产生模拟信号的方法，包括将样本馈送到Δ-Σ调制器中，Δ-Σ调制器输出比特序列，并将非线性时间离散函数引入反馈量化器元件和Δ-Σ调制器的delta元件之间的环路，其中非线性时间离散函数的参数包括当前位和当前位之前的至少一个位。

8. 发明申请

US20120014426A1 METHODS AND APPARATUS FOR DIRECT SYNTHESIS OF RF SIGNALS USING DELTA-SIGMA MODULATOR 有权
标题翻译：使用DELTA-SIGMA调制器直接合成RF信号的方法和装置
公开(公告)号：US20120014426A1
公开(公告)日：2012-01-19
申请号：US13254397
申请日：2009-03-31
申请人： Kameran Azadet , Samer Hijazi , Joseph H. Othmer
发明人： Kameran Azadet , Samer Hijazi , Joseph H. Othmer
IPC分类号： H04B17/00
CPC分类号： H03M7/3042 , H03M7/3024
摘要： Methods and apparatus are provided for direct synthesis of RF signals using a delta-sigma modulator. An RF signal is synthesized from an input signal by quantizing the input signal using a quantizer, such as a one bit quantizer; determining a quantization error associated with the quantizer; generating an error prediction value using an error predictive filter, wherein the error predictive filter comprises one or more filter zeroes on a unit circle for one or more desired frequencies of f1, f2, . . . fn and one or more filter poles having a magnitude inside the unit circle and a frequency substantially equal to the one or more desired frequencies of f1, f2, . . . fn; and subtracting the error prediction value from the input signal. The filter poles have a magnitude that reduces a boost provided out-of-band.
摘要翻译：提供了使用Δ-Σ调制器直接合成RF信号的方法和装置。通过使用诸如一位量化器的量化器量化输入信号，从输入信号合成RF信号; 确定与所述量化器相关联的量化误差; 使用误差预测滤波器生成误差预测值，其中所述误差预测滤波器包括在f1，f2的一个或多个期望频率的单位圆上的一个或多个滤波器零点。。。 fn和一个或多个具有在单位圆内的幅度的滤波器极，并且频率基本上等于f1，f2的一个或多个期望频率。。。 fn 并从输入信号中减去误差预测值。滤波器极具有降低带外提升的幅度。

9. 发明授权

US07876247B1 Signal dependent dither 有权
标题翻译：信号依赖抖动
公开(公告)号：US07876247B1
公开(公告)日：2011-01-25
申请号：US12325223
申请日：2008-11-30
申请人： Shawn David Hunt , Carlos Fabian Benitez-Quiroz
发明人： Shawn David Hunt , Carlos Fabian Benitez-Quiroz
IPC分类号： H03M1/20
CPC分类号： H03M7/3008 , H03M7/3024
摘要： A new technique on the dithering of one-dimensional signals is presented. The novel technique determines whether dither is needed when reducing the bit depth and evaluates whether the total error of the un-dithered quantization is white noise. If this is the case, then no undesired harmonics are added in the quantization or re-quantization process. The novel technique presents a state of the art signal-dependent dither having a lower quantization noise.
摘要翻译：提出了一种关于一维信号抖动的新技术。该新颖的技术确定了在减少比特深度时需要抖动，并且评估未抖动量化的总误差是否为白噪声。如果是这种情况，则在量化或重新量化过程中不会添加不期望的谐波。该新技术呈现出具有较低量化噪声的最先进的信号相关抖动。

10. 发明授权

US07847716B2 Asynchronous sigma-delta digital-analog converter 有权
标题翻译：异步Σ-Δ数模转换器
公开(公告)号：US07847716B2
公开(公告)日：2010-12-07
申请号：US12376121
申请日：2006-08-01
申请人： Jochen Rivoir
发明人： Jochen Rivoir
IPC分类号： H03M3/00
CPC分类号： H03M7/3024
摘要： An asynchronous sigma delta digital to analog converter for converting a digital input signal into an analog output signal, the digital to analog converter having an asynchronous sigma delta modulator having a low pass filter and a comparator and being supplied with the digital input signal, and a clock sample unit adapted to sample a signal processed by the comparator based on a clock signal, thereby generating the analog output signal.
摘要翻译：一种用于将数字输入信号转换为模拟输出信号的异步Σ-Δ数模转换器，所述数模转换器具有具有低通滤波器和比较器的异步Σ-Δ调制器，并且被提供有数字输入信号，以及时钟采样单元，其适于基于时钟信号对由比较器处理的信号进行采样，从而产生模拟输出信号。

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