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1. 发明授权

US10623014B2 Apparatuses and methods for sample rate conversion 有权
公开(公告)号：US10623014B2
公开(公告)日：2020-04-14
申请号：US16382535
申请日：2019-04-12
申请人： Syntropy Systems, LLC
发明人： Christopher Pagnanelli
IPC分类号： H03M3/00 , H03M1/10 , H03M1/66 , H03M1/12 , H03M1/78 , H03M9/00 , H04L27/36 , H03M7/32 , H03M7/36
CPC分类号： H03M3/358 , H03M1/1038 , H03M1/121 , H03M1/661 , H03M1/662 , H03M3/436 , H03M3/502 , H03M3/51 , H03M9/00 , H04L27/362 , H03M1/785 , H03M7/3026 , H03M7/3033
摘要： Provided, among other things, is an apparatus that converts a signal from one sampling domain to another, and which includes: an input line for accepting an input signal and a processing branch. The processing branch includes a branch input coupled to the input line for inputting data samples that are discrete in time and in value, a quadrature downconverter, a first and second lowpass filter, a first and second polynomial interpolator, and a rotation matrix multiplier that provides a phase rotation. The processing branch generates data samples at a sampling interval that differs from the sampling interval associated with the signal provided to the branch input, e.g., with the difference in the sampling intervals depending on fluctuations in the output period of a local oscillator. Certain embodiments include multiple such processing branches, e.g., operating on different frequency bands of the input signal.

2. 发明授权

US09571931B1 Systems and methods for reducing non-linearities of a microphone signal 有权
标题翻译：用于减少麦克风信号的非线性的系统和方法
公开(公告)号：US09571931B1
公开(公告)日：2017-02-14
申请号：US14247987
申请日：2014-04-08
申请人： Cirrus Logic, Inc.
发明人： John L. Melanson , John C. Tucker
IPC分类号： H04R3/02 , H04R3/00 , H04R29/00 , H04R19/04
CPC分类号： H04R3/02 , H03F1/26 , H03F3/16 , H03F2200/372 , H03M3/00 , H03M3/39 , H03M3/424 , H03M3/458 , H03M3/50 , H03M7/3026 , H03M7/3028 , H04R3/00 , H04R3/002 , H04R3/007 , H04R19/04 , H04R29/001
摘要： To correct for non-linearities in the response of a microphone as a function of sound pressure level incident upon the microphone, a displacement non-linearity function is applied to the signal path of the microphone, wherein the displacement non-linearity function is a function of the digital audio output signal and has a response modeling non-linearities of the displacement as a function of a sound pressure level incident upon the microphone.
摘要翻译：为了校正麦克风的响应中的非线性作为入射到麦克风的声压级的函数，位移非线性函数被施加到麦克风的信号路径，其中位移非线性函数是函数的数字音频输出信号，并且具有作为入射到麦克风的声压级的函数的位移的非线性的响应建模。

3. 发明授权

US09419562B1 Systems and methods for minimizing noise in an amplifier 有权
标题翻译：用于最小化放大器噪声的系统和方法
公开(公告)号：US09419562B1
公开(公告)日：2016-08-16
申请号：US14248054
申请日：2014-04-08
申请人： Cirrus Logic, Inc.
发明人： John L. Melanson , John C. Tucker
IPC分类号： H03F1/02 , H03F1/26 , H03F3/16
CPC分类号： H04R3/02 , H03F1/26 , H03F3/16 , H03F2200/372 , H03M3/00 , H03M3/39 , H03M3/424 , H03M3/458 , H03M3/50 , H03M7/3026 , H03M7/3028 , H04R3/00 , H04R3/002 , H04R3/007 , H04R19/04 , H04R29/001
摘要： An amplifier may include a plurality of stages, wherein each stage may have an amplifier stage output configured to generate an amplifier output signal and a transistor coupled at its gate terminal to the amplifier input and to the gate terminals of the transistors of the other amplifier stages. Each stage may be configured to periodically and cyclically operate in an amplifier mode in which the amplifier stage generates at its corresponding amplifier stage output a power-amplified version of a signal received at the amplifier input and a in reset mode in which the transistor of the stage operating in the reset mode has an electrical property thereof reset. At any given time, at least one amplifier stage is operating in the amplifier mode. The amplifier may be configured to output as an output signal one of the amplifier output signals corresponding to an amplifier stage operating in the amplifier mode.
摘要翻译：放大器可以包括多个级，其中每个级可以具有被配置为产生放大器输出信号的放大器级输出和在其栅极端耦合到放大器输入端和耦合到其它放大器级的晶体管的栅极端子的晶体管。每个级可以被配置为在放大器模式中周期性地和周期性地工作，其中放大器级在其相应的放大级产生输出在放大器输入处接收的信号的功率放大形式，在复位模式中，在复位模式下工作的电平具有电性能的复位。在任何给定时间，至少一个放大器级在放大器模式下工作。放大器可以被配置为输出对应于以放大器模式工作的放大器级的放大器输出信号之一作为输出信号。

4. 发明授权

US08896471B1 Conversion of a discrete-time quantized signal into a continuous-time, continuously variable signal 有权
标题翻译：将离散时间量化信号转换为连续时间连续可变信号
公开(公告)号：US08896471B1
公开(公告)日：2014-11-25
申请号：US13647301
申请日：2012-10-08
申请人： Syntropy Systems, LLC
发明人： Christopher Pagnanelli
IPC分类号： H03M3/00 , H03M1/74
CPC分类号： H03M3/30 , H03M1/747 , H03M3/358 , H03M3/50 , H03M3/502 , H03M7/3026 , H03M7/3033
摘要： Provided are, among other things, systems, apparatuses, methods and techniques for converting a discrete-time quantized signal into a continuous-time, continuously variable signal. An exemplary converter preferably includes: (1) multiple oversampling converters, each processing a different frequency band, operated in parallel; (2) multirate (i.e., polyphase) delta-sigma modulators (preferably second-order or higher); (3) multi-bit quantizers; (4) multi-bit-to-variable-level signal converters, such as resistor ladder networks or current source networks; (5) adaptive nonlinear, bit-mapping to compensate for mismatches in the multi-bit-to-variable-level signal converters (e.g., by mimicking such mismatches and then shifting the resulting noise to a frequently range where it will be filtered out by a corresponding bandpass (reconstruction) filter); (6) multi-band (e.g., programmable noise-transfer-function response) bandpass delta-sigma modulators; and/or (7) a digital pre-distortion linearizer (DPL) for canceling noise and distortion introduced by an analog signal bandpass (reconstruction) filter bank.
摘要翻译：尤其提供了用于将离散时间量化信号转换成连续时间连续可变信号的系统，装置，方法和技术。示例性转换器优选地包括：（1）多个过采样转换器，每个处理不同的频带，并行操作; （2）多速率（即多相）Δ-Σ调制器（优选二阶或更高）; （3）多位量化器; （4）多位到可变电平信号转换器，如电阻梯形网络或电流源网络; （5）自适应非线性比特映射以补偿多比特到可变电平信号转换器中的不匹配（例如，通过模拟这样的失配，然后将所得到的噪声移动到频率范围，其中将被滤波掉相应的带通（重建）滤波器）; （6）多频带（例如可编程噪声传递函数响应）带通Δ-Σ调制器; 和/或（7）用于消除由模拟信号带通（重构）滤波器组引入的噪声和失真的数字预失真线性化器（DPL）。

5. 发明授权

US08619882B2 Data modulation circuit 有权
标题翻译：数据调制电路
公开(公告)号：US08619882B2
公开(公告)日：2013-12-31
申请号：US12330279
申请日：2008-12-08
申请人： Uichi Sekimoto
发明人： Uichi Sekimoto
IPC分类号： H04B14/06
CPC分类号： H03M7/3026 , H03M7/3031
摘要： A data modulation circuit has an adder adding an input signal, and an output signal of a memory device; and an output circuit part discriminating and quantizing the output signal of the adder by a predetermined threshold value. The memory device receives and holds the output signal of the adder and a predetermined signal, and supplies the held signals to the adder as an output signal of the memory device.
摘要翻译：数据调制电路具有添加输入信号的加法器和存储器件的输出信号; 以及输出电路部分，将加法器的输出信号鉴别和量化预定阈值。存储器件接收并保持加法器的输出信号和预定信号，并将保持的信号作为存储器件的输出信号提供给加法器。

6. 发明申请

US20130064324A1 Digital Modulation With Arbitrary Input Sampling and Output Modulation Frequencies 有权
标题翻译：数字调制与任意输入采样和输出调制频率
公开(公告)号：US20130064324A1
公开(公告)日：2013-03-14
申请号：US13484485
申请日：2012-05-31
申请人： Bernard Ginetti , Zhongxuan Zhang
发明人： Bernard Ginetti , Zhongxuan Zhang
IPC分类号： H04B15/00 , H04L27/12
CPC分类号： H03M3/41 , H03C3/00 , H03M7/3017 , H03M7/3026 , H03M7/304 , H04L27/04
摘要： An arbitrary modulation frequency of a modulating signal is selected. The modulating signal is applied to an information-bearing signal, where such modulation is carried out through digital signal processing operations. The digitally modulated signal is resolution-reduced and the quantization noise introduced by such is shaped to locate a spectral null in the noise transfer function of the resolution reducing modulator at the modulation frequency. Thus, the modulation frequency can be selected independently of the clock frequency at which the resolution-reduced samples are converted to an analog signal.
摘要翻译：选择调制信号的任意调制频率。调制信号被应用于信息承载信号，其中通过数字信号处理操作进行这种调制。数字调制信号是分辨率降低的，并且由此引入的量化噪声被形成为在调制频率下在分辨率降低调制器的噪声传递函数中定位频谱零点。因此，可以独立于将分辨率降低的采样转换为模拟信号的时钟频率来选择调制频率。

7. 发明申请

US20110140942A1 Conversion of a Discrete Time Quantized Signal into a Continuous Time, Continuously Variable Signal 有权
标题翻译：将离散时间量化信号转换为连续时间，连续可变信号
公开(公告)号：US20110140942A1
公开(公告)日：2011-06-16
申请号：US12970379
申请日：2010-12-16
申请人： Christopher Pagnanelli
发明人： Christopher Pagnanelli
IPC分类号： H03M1/66
CPC分类号： H03M3/50 , H03M3/358 , H03M3/502 , H03M7/3026 , H03M7/3033
摘要： Provided are, among other things, systems, apparatuses, methods and techniques for converting a discrete-time quantized signal into a continuous-time, continuously variable signal. An exemplary converter preferably includes: (1) multiple oversampling converters, each processing a different frequency band, operated in parallel; (2) multirate (i.e., polyphase) delta-sigma modulators (preferably second-order or higher); (3) multi-bit quantizers; (4) multi-bit-to-variable-level signal converters, such as resistor ladder networks or current source networks; (5) adaptive non-linear, bit-mapping to compensate for mismatches in the multi-bit-to-variable-level signal converters (e.g., by mimicking such mismatches and then shifting the resulting noise to a frequently range where it will be filtered out by a corresponding bandpass (reconstruction) filter); (6) multi-band (e.g., programmable noise-transfer-function response) bandpass delta-sigma modulators; and/or (7) a digital pre-distortion linearizer (DPL) for canceling noise and distortion introduced by an analog signal bandpass (reconstruction) filter bank.
摘要翻译：尤其提供了用于将离散时间量化信号转换成连续时间连续可变信号的系统，装置，方法和技术。示例性转换器优选地包括：（1）多个过采样转换器，每个处理不同的频带，并行操作; （2）多速率（即多相）Δ-Σ调制器（优选二阶或更高）; （3）多位量化器; （4）多位到可变电平信号转换器，如电阻梯形网络或电流源网络; （5）自适应非线性比特映射以补偿多比特到可变等级信号转换器中的不匹配（例如，通过模拟这种不匹配，然后将所得到的噪声移动到将被滤波的频繁范围）通过相应的带通（重建）滤波器）; （6）多频带（例如可编程噪声传递函数响应）带通Δ-Σ调制器; 和/或（7）用于消除由模拟信号带通（重构）滤波器组引入的噪声和失真的数字预失真线性化器（DPL）。

8. 发明授权

US07720160B1 Phase noise shaping using sigma delta modulation in a timing recovery unit 有权
标题翻译：在定时恢复单元中使用Σ-Δ调制的相位噪声整形
公开(公告)号：US07720160B1
公开(公告)日：2010-05-18
申请号：US11639656
申请日：2006-12-14
申请人： James L. Gorecki , Tong Liu
发明人： James L. Gorecki , Tong Liu
IPC分类号： H04B14/06 , H04L7/00 , H03M1/20
CPC分类号： H04B14/062 , H03L7/0812 , H03L7/093 , H03M3/50 , H03M7/3026 , H04L7/0025 , H04L7/033
摘要： A method and apparatus for converting a high precision digital word into a high precision analog signal is disclosed. A sigma delta modulator applies a digital input signal to a dither signal to generate a combined signal for sampling. A digital-to-analog converter quantizes the combined signal. An analog filter provides a cutoff at a bandwidth of interest to remove out of band quantization noise and signals. An I transfer function and a Q transfer function can be coupled between the sigma delta modulator and the digital-to-analog converter for mapping of the combined signal. The apparatus can also include a phase interpolator for receiving the output signal and outputting a clock recovery phase.
摘要翻译：公开了一种用于将高精度数字字转换成高精度模拟信号的方法和装置。 Σ-Δ调制器将数字输入信号施加到抖动信号以产生用于采样的组合信号。数模转换器对组合信号进行量化。模拟滤波器在感兴趣的带宽上提供截止以去除带外量化噪声和信号。可以在Σ-Δ调制器和数 - 模转换器之间耦合I传递函数和Q传递函数，用于映射组合信号。该装置还可以包括用于接收输出信号并输出时钟恢复阶段的相位插值器。

9. 发明申请

US20100117730A1 D/A converter circuit and digital input class-D amplifier 有权
标题翻译： D / A转换器电路和数字输入D类放大器
公开(公告)号：US20100117730A1
公开(公告)日：2010-05-13
申请号：US12583792
申请日：2009-08-26
申请人： Hirotaka Kawai , Nobuaki Tsuji , Morito Morishima , Yohei Otani
发明人： Hirotaka Kawai , Nobuaki Tsuji , Morito Morishima , Yohei Otani
IPC分类号： H03F3/217 , H03M1/66
CPC分类号： H03F3/2173 , H03M1/0639 , H03M1/0673 , H03M1/822 , H03M3/328 , H03M3/50 , H03M3/506 , H03M7/3026
摘要： The present invention provides a D/A converter circuit which enables D/A conversion with a high precision and can prevent occurrence of a limit cycle component in the case where an input signal is low, and can also prevent the effect of dither signal from occurring in an analog signal which is a D/A conversion result.A dither signal generation section 505 outputs a dither signal (DITHER) which is an alternating current signal and a reversal dither signal (DITHER_N) inverted from the dither signal. A DEM decoder 502 processes an input digital signal including a component of the dither signal (DITHER), and outputs a plurality of lines of time-series digital signals having a density of “1” or “0” conforming to the input digital signal to be processed. An analog addition section 503 converts a plurality of lines of time-series digital signals and the reversal dither signal (DITHER_N) into an analog signal respectively and adds them, and outputs an analog signal which is a D/A conversion result.
摘要翻译：本发明提供了一种D / A转换器电路，其能够以高精度实现D / A转换，并且可以防止在输入信号低的情况下出现极限循环分量，并且还可以防止抖动信号的影响在作为D / A转换结果的模拟信号中。抖动信号生成单元505输出作为交流信号的抖动信号（DITHER）和从抖动信号反转的反转抖动信号（DITHER_N）。 DEM解码器502处理包括抖动信号（DITHER）分量的输入数字信号，并输出符合输入数字信号的密度为“1”或“0”的多行时间序列数字信号到被处理。模拟加法部分503将多行时间序列数字信号和反相抖动信号（DITHER_N）分别转换为模拟信号并将其相加，并输出作为D / A转换结果的模拟信号。

10. 发明授权

US07710300B2 Segmented data shuffler apparatus for a digital to analog converter (DAC) 有权
标题翻译：用于数模转换器（DAC）的分段数据洗牌装置
公开(公告)号：US07710300B2
公开(公告)日：2010-05-04
申请号：US12081547
申请日：2008-04-17
申请人： Tom W. Kwan
发明人： Tom W. Kwan
IPC分类号： H03M3/00 , H03M1/66
CPC分类号： H03M3/416 , H03M3/50 , H03M7/3026
摘要： A sigma-delta digital to analog converter (DAC) module converts the digital input signal to the analog output signal through segmentation, including a primary and a secondary sigma-delta modulator. The primary sigma-delta modulator produces a primary digital segment and a primary quantization error. A primary sample is delayed, decoded, scrambled and converted to produce a primary analog segment. A secondary sigma-delta modulates the primary quantization error to produce a secondary digital segment which is noise shaped by a noise transfer function of the primary sigma-delta modulator to produce a noise shaped secondary digital segment which is decoded, scrambled, converted and scaled to produce a secondary analog segment. An adder combines the primary analog segment and the secondary analog segment to produce the analog output signal.
摘要翻译： Σ-Δ数模转换器（DAC）模块通过包括初级和次级Σ-Δ调制器的分段将数字输入信号转换成模拟输出信号。初级Σ-Δ调制器产生主数字段和主量化误差。主要样本被延迟，解码，加扰和转换以产生主要的模拟段。次级Σ-Δ调制主量化误差以产生次级数字段，其由主要Σ-Δ调制器的噪声传递函数进行噪声整形，以产生噪声形状的次级数字段，其被解码，加扰，转换和缩放为产生二次模拟段。一个加法器结合了主要的模拟段和二级模拟段，以产生模拟输出信号。

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