专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20180309408A1 VARIABLE GAIN AMPLIFIER UTILIZING POSITIVE FEEDBACK AND TIME-DOMAIN CALIBRATION 审中-公开
公开(公告)号：US20180309408A1
公开(公告)日：2018-10-25
申请号：US15803081
申请日：2017-11-03
申请人： BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
发明人： Nan Sun , Miguel Gandara
IPC分类号： H03F1/02 , H03K3/356 , H03F3/45 , H03F1/08
CPC分类号： H03F1/0211 , H03F1/08 , H03F1/086 , H03F1/3211 , H03F1/38 , H03F3/45179 , H03F3/45188 , H03F3/45475 , H03F3/45632 , H03F3/45928 , H03F2203/45048 , H03F2203/45551 , H03F2203/45634 , H03K3/35613 , H03M1/00 , H03M1/06 , H03M1/10 , H03M1/12 , H03M1/14
摘要： A variable gain amplifier utilizing positive feedback and time-domain calibration includes an integration phase and a regeneration phase. A current source provides a bias current that increases linearity in the integration phase and reduces common-mode voltage dependence. The circuit includes a timing control loop, wherein a variable gain of a residue amplifier is proportional to a first time that a timing control loop signal is kept high, as determined by an on or off status of respectively paired inverter assemblies each having an input voltage determined by an amplifier output voltage during the regeneration phase. A strong-arm latch structure acts as a positive feedback latch until the first time is de-asserted.

2. 发明申请

US20180241411A1 A/D CONVERSION DEVICE 审中-公开
公开(公告)号：US20180241411A1
公开(公告)日：2018-08-23
申请号：US15752096
申请日：2015-11-11
申请人： Mitsubishi Electric Corporation
发明人： Yusuke KOBAYASHI , Takayasu NARUKAWA , Masaya TSUNEOKA , Masayuki FUNAKOSHI , Norihiro YAMAGUCHI , Takahiro OKANOUE
IPC分类号： H03M1/36 , H03M1/10 , H03M1/12
CPC分类号： H03M1/362 , H03M1/10 , H03M1/1071 , H03M1/12 , H03M1/123
摘要： A first mode in which to output analog electricity quantities of objects one by one independently to an A/D converter, a second mode in which to output none of the analog electricity quantities of the objects, a third mode in which to output none of the analog electricity quantities of the objects and cause the output to the A/D converter to be resistor, and a fourth mode in which to output to the A/D converter a plurality of the analog electricity quantities of the objects at the same time, are caused to be generated, thus acquiring the A/D conversion values of the objects individually when in the first mode, and detecting an anomaly of the A/D converter itself or a device connected to the A/D converter when in the second mode to the fourth mode.

3. 发明授权

US10009038B2 Wideband Nyquist VCO-based analog-to-digital converter 有权
公开(公告)号：US10009038B2
公开(公告)日：2018-06-26
申请号：US15507704
申请日：2015-09-02
申请人： University of Southern California
发明人： Shuo-Wei Chen
IPC分类号： H03M1/12 , H03M1/14 , H03M1/50 , H03M1/06 , H03M1/10 , H03M1/60
CPC分类号： H03M1/1245 , H03M1/0609 , H03M1/10 , H03M1/14 , H03M1/502 , H03M1/60
摘要： An analog-to-digital converter may convert an analog signal into digital codes representative of the changing level of the analog signal. An analog high pass filter may receive and continuously differentiate the analog signal. A voltage controlled oscillator may receive the differentiated analog signal and continuously generates an output that is an integral of the differentiated analog signal in the phase domain. A time-to-digital converter may sample the output of the voltage controlled oscillator and convert each sample into a digital code representative of the current phase of the sampled output of the voltage controlled oscillator.

4. 发明授权

US09678481B1 Fractional divider using a calibrated digital-to-time converter 有权
公开(公告)号：US09678481B1
公开(公告)日：2017-06-13
申请号：US15185378
申请日：2016-06-17
申请人： Integrated Device Technology, Inc.
发明人： Song Gao , Brian Buell , Katherine T. Blinick
IPC分类号： H03M1/10 , G04F10/00 , H03M3/00
CPC分类号： G04F10/005 , G04G3/02 , G06F1/08 , H03M1/10 , H03M1/1009 , H03M1/66 , H03M1/82
摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a divided clock signal and a control signal in response to (i) an input clock signal and (ii) a configuration signal. The second circuit may be configured to generate an output clock signal in response to (i) the control signal and (ii) the divided clock signal. The second circuit may add a delay to one or more edges of the output clock signal by engaging one or more of a plurality of capacitances. A number of the capacitances engaged may be selected to reduce jitter on the output clock signal. The capacitances may be used each cycle to calibrate the output clock signal.

5. 发明授权

US09407279B2 Systems and methods of element scrambling for compensation and calibration of analog-to-digital converter feedback 有权
标题翻译：元件加扰的系统和方法用于模数转换器反馈的补偿和校准
公开(公告)号：US09407279B2
公开(公告)日：2016-08-02
申请号：US14617376
申请日：2015-02-09
申请人： Cirrus Logic, Inc.
发明人： John L. Melanson , Jaimin Mehta , Stephen T. Hodapp
IPC分类号： H03M1/10 , H03M1/06 , H03M1/08 , H03M1/66 , H03M3/00
CPC分类号： H03M1/1038 , H03M1/06 , H03M1/0665 , H03M1/0863 , H03M1/10 , H03M1/1009 , H03M1/66 , H03M3/458
摘要： An apparatus may include a scrambler element configured to receive an input signal and generate a scrambled thermometer code-like signal having a plurality of bits based on the input signal and having a plurality of possible quantization values. The scrambler element may generate at least one equivalent code of the scrambled thermometer code-like signal for each possible quantization value. For each of one or more of the possible quantization values, the scrambler element may be configured to generate a plurality of possible equivalent codes of the scrambled thermometer code-like signal. Responsive to the input signal indicating a change in quantization value of the scrambled thermometer code-like signal, the scrambler element may change the scrambled thermometer code-like signal by transitioning the smallest possible number of the plurality of bits of the scrambled thermometer code-like signal to change quantization value of the scrambled thermometer code-like signal in accordance with the input signal.
摘要翻译：装置可以包括扰频器元件，其被配置为接收输入信号并且基于输入信号生成具有多个比特的加扰温度计类似码字的信号，并且具有多个可能的量化值。加扰器元件可以为每个可能的量化值生成加扰的温度计代码样信号的至少一个等效代码。对于一个或多个可能的量化值中的每个，加扰器元件可以被配置为生成加扰的温度计代码样信号的多个可能的等效代码。响应于指示加扰的温度计编码类信号的量化值的改变的输入信号，加扰器元件可以通过转换加扰的温度计代码样信号的多个比特的最小可能数来改变加扰的温度计代码样信号信号以根据输入信号改变加扰的温度计代码样信号的量化值。

6. 发明授权

US09214951B1 Self-calibrating VCO-based analog-to-digital converter and method thereof 有权
标题翻译：自校准基于VCO的模数转换器及其方法
公开(公告)号：US09214951B1
公开(公告)日：2015-12-15
申请号：US14291441
申请日：2014-05-30
申请人： Realtek Semiconductor Corp.
发明人： Chia-Liang (Leon) Lin
IPC分类号： H03M1/10 , H03M1/12
CPC分类号： H03M1/1019 , H03M1/10 , H03M1/1004 , H03M1/1009 , H03M1/1235 , H03M1/60
摘要： A circuit includes an input dispatch unit for receiving an input signal and a calibration signal and outputting N dispatched signals in accordance with a selection signal. The circuit also includes N analog-to-digital converter (ADC) units for receiving the N dispatched signals, N control signals, and N mapping tables and outputting N raw data, and N refined data, respectively. An output dispatch unit receives the N refined data and outputting an output data in accordance with the selection signal, and a calibration controller receives the N raw data and outputting the selection signal, the N control signals, the N mapping tables, and a digital code. A DAC (digital-to-analog converter) receives the digital code and outputting the calibration signal, wherein one of the dispatched signals, as specified by the selection signal is from the calibration signal while the other dispatched signals are from the input signal.
摘要翻译：电路包括输入调度单元，用于接收输入信号和校准信号，并根据选择信号输出N个调度信号。该电路还包括N个模拟 - 数字转换器（ADC）单元，用于分别接收N个调度信号，N个控制信号和N个映射表，并分别输出N个原始数据和N个精细数据。输出调度单元接收N个精细数据并根据选择信号输出输出数据，校准控制器接收N个原始数据并输出选择信号，N个控制信号，N个映射表和数字代码。 DAC（数模转换器）接收数字代码并输出校准信号，其中由选择信号指定的调度信号之一来自校准信号，而另一个调度信号来自输入信号。

7. 发明申请

US20150349794A1 SELF-CALIBRATING VCO-BASED ANALOG-TO-DIGITAL CONVERTER AND METHOD THEREOF 有权
标题翻译：自校准基于VCO的模数转换器及其方法
公开(公告)号：US20150349794A1
公开(公告)日：2015-12-03
申请号：US14291441
申请日：2014-05-30
申请人： Realtek Semiconductor Corp.
发明人： Chia-Liang (Leon) Lin
IPC分类号： H03M1/10 , H03M1/12
CPC分类号： H03M1/1019 , H03M1/10 , H03M1/1004 , H03M1/1009 , H03M1/1235 , H03M1/60
摘要： A circuit includes an input dispatch unit for receiving an input signal and a calibration signal and outputting N dispatched signals in accordance with a selection signal. The circuit also includes N analog-to-digital converter (ADC) units for receiving the N dispatched signals, N control signals, and N mapping tables and outputting N raw data, and N refined data, respectively. An output dispatch unit receives the N refined data and outputting an output data in accordance with the selection signal, and a calibration controller receives the N raw data and outputting the selection signal, the N control signals, the N mapping tables, and a digital code. A DAC (digital-to-analog converter) receives the digital code and outputting the calibration signal, wherein one of the dispatched signals, as specified by the selection signal is from the calibration signal while the other dispatched signals are from the input signal.
摘要翻译：电路包括输入调度单元，用于接收输入信号和校准信号，并根据选择信号输出N个调度信号。该电路还包括N个模拟 - 数字转换器（ADC）单元，用于分别接收N个调度信号，N个控制信号和N个映射表，并分别输出N个原始数据和N个精细数据。输出调度单元接收N个精细数据并根据选择信号输出输出数据，校准控制器接收N个原始数据并输出选择信号，N个控制信号，N个映射表和数字代码。 DAC（数模转换器）接收数字代码并输出校准信号，其中由选择信号指定的调度信号之一来自校准信号，而另一个调度信号来自输入信号。

8. 发明申请

US20150295586A1 ANALOG-DIGITAL CONVERTER 有权
标题翻译：模拟数字转换器
公开(公告)号：US20150295586A1
公开(公告)日：2015-10-15
申请号：US14749352
申请日：2015-06-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Lukas Kull , Thomas H. Toifl
IPC分类号： H03M1/10 , H03M1/44 , H03M1/12 , H03M1/00
CPC分类号： H03M1/1009 , H03M1/002 , H03M1/10 , H03M1/1038 , H03M1/1245 , H03M1/442 , H03M1/468
摘要： An analog-digital converter with successive approximation includes a capacitor array for being loaded by applying a given input signal potential and for providing a sampling potential, wherein capacitors of the capacitor array are serially coupled with switches. A decision latch is included for evaluating the sampling potential in a number of consecutive decision steps. The analog-digital converter also includes a logic unit for selectively changing the sampling potential by selectively switching switches associated to the capacitors of the capacitor array for each decision step based on an evaluation result of a previous decision step, wherein the switches are respectively coupled with a calibration switch.
摘要翻译：具有逐次逼近的模数转换器包括通过施加给定输入信号电位并提供采样电位来加载的电容器阵列，其中电容器阵列的电容器与开关串联耦合。包括用于评估多个连续判定步骤中的采样电位的判定锁存器。模拟数字转换器还包括一个逻辑单元，用于通过根据先前决定步骤的评估结果选择性地切换与每个决定步骤的电容器阵列的电容器相关联的开关来选择性地改变采样电位，其中开关分别与校准开关。

9. 发明申请

US20150070199A1 CIRCUITRY AND METHODS FOR USE IN MIXED-SIGNAL CIRCUITRY 有权
标题翻译：用于混合信号电路的电路和方法
公开(公告)号：US20150070199A1
公开(公告)日：2015-03-12
申请号：US14025330
申请日：2013-09-12
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Ian Juso DEDIC , Saul Darzy , Gavin Lambertus Allen
IPC分类号： H03M1/10
CPC分类号： H03M1/1009 , H03M1/10 , H03M1/745
摘要： A method of calibrating switching circuitry, the switching circuitry comprising a measurement node and a plurality of output switches connected to the measurement node, and the circuitry being configured, in each clock cycle of a series of clock cycles, to control whether or not one or more of said output switches carry a given current based upon input data, the method comprising: inputting a plurality of different data sequences to the circuitry, each sequence causing a given pattern of voltages to occur at the measurement node as a result of currents passing through the output switches; measuring the voltages occurring at the measurement node for each said sequence; and calibrating the switching circuitry in dependence upon a result of said measuring.
摘要翻译：一种校准开关电路的方法，所述开关电路包括连接到所述测量节点的测量节点和多个输出开关，并且所述电路在一系列时钟周期的每个时钟周期中被配置以控制是否一个或者更多的所述输出开关基于输入数据携带给定的电流，该方法包括：向电路输入多个不同的数据序列，每个序列导致给定的电压模式由于电流通过而在测量节点处出现输出开关; 测量每个所述序列在测量节点处出现的电压; 并根据所述测量的结果校准开关电路。

10. 发明授权

US08928515B1 Analog-to-digital converter and method of converting an analog signal to a digital signal 有权
标题翻译：模拟数字转换器和将模拟信号转换成数字信号的方法
公开(公告)号：US08928515B1
公开(公告)日：2015-01-06
申请号：US14194675
申请日：2014-03-01
申请人： Beken Corporation
发明人： Desheng Hu , Dawei Guo
IPC分类号： H03M1/34 , H03M1/12 , H03M1/38 , H03M1/10
CPC分类号： H03M1/10 , H03M1/0863 , H03M1/146 , H03M1/38
摘要： An analog-to-digital converter (ADC) comprises a sample/hold (S/H) unit, a digital-to-analog converter (DAC), a comparing unit, and a control unit. The S/H unit samples a first analog signal. The control unit comprises a compensating unit. The compensating unit receives an indication signal, and compensates a current bit and all its less significant bits, such that the sum of the current bit and all its less significant bits approximates a bit weight of the current bit, when the indication signal indicates that the comparison result cannot be determined. The compensating unit then outputs the compensated current bit and all its less significant bits together with more significant bits of the current bit.
摘要翻译：模数转换器（ADC）包括采样/保持（S / H）单元，数模转换器（DAC），比较单元和控制单元。 S / H单元采样第一个模拟信号。控制单元包括补偿单元。补偿单元接收指示信号，并补偿当前位及其所有较低有效位，使得当指示信号指示当前位和当前位的总和与当前位的位权重近似为当前位的位权重时，比较结果无法确定。补偿单元然后将补偿的当前位及其所有较低有效位与当前位的更高有效位一起输出。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式