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1. 发明授权

US07705635B1 Circuit for converting a voltage range of a logic signal 失效
标题翻译：用于转换逻辑信号的电压范围的电路
公开(公告)号：US07705635B1
公开(公告)日：2010-04-27
申请号：US11836635
申请日：2007-08-09
申请人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
发明人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H03K3/35613
摘要： In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A source-follower circuit includes a current source and a source follower output, and the source follower output is coupled to the output node. A second MOS transistor selectively couples the source-follower circuit to a second reference voltage when the output node is to be in the second state.
摘要翻译：在将具有第一范围的第一逻辑信号转换为具有第二范围的第二逻辑信号的电路中，当输出节点将处于该状态时，第一金属氧化物半导体（MOS）晶体管选择性地将输出节点耦合到第一参考电压第一个状态源跟随器电路包括电流源和源极跟随器输出，并且源极跟随器输出耦合到输出节点。当输出节点处于第二状态时，第二MOS晶体管选择性地将源极跟随器电路耦合到第二参考电压。

2. 发明申请

US20090102688A1 MULTISTAGE ANALOG/DIGITAL CONVERTER AND METHOD FOR CALIBRATING SAID CONVERTER 有权
标题翻译：多模式模拟/数字转换器和校准转换器的方法
公开(公告)号：US20090102688A1
公开(公告)日：2009-04-23
申请号：US12198709
申请日：2008-08-26
申请人： Giovanni Antonio Cesura , Roberto Giampiero Massolini
发明人： Giovanni Antonio Cesura , Roberto Giampiero Massolini
IPC分类号： H03M1/10 , H03M1/12 , H03M1/00
CPC分类号： H03M1/1061 , H03M1/1004 , H03M1/162 , H03M1/164 , H03M1/40 , H03M1/44
摘要： A multistage analog/digital converter for converting in multi-step cycles an input signal into respective digital codes, each cycle step resolving at least one bit of a respective digital code. The converter includes: a sampling circuit inputting the signal and outputting a first sequence of analog samples; a generation block of a pseudorandom sequence of samples; a summing node, such as to input the first sequence and the pseudorandom sequence, obtaining in output a second sequence of analog samples including non-pseudorandom samples; a converter having a controllable digital gain receiving the second sequence and outputting bits of the digital codes; a feedback loop with a loop gain and including an analog amplifier; a digital calibration block to match the digital gain to the loop gain and including a prediction block to produce a digital estimation of said input signal starting from the bits resulting from converting the non-pseudorandom samples.
摘要翻译：一种用于以多步循环将输入信号转换成相应数字代码的多级模拟/数字转换器，每个循环步骤分辨相应数字代码的至少一位。转换器包括：采样电路，输入信号并输出第一序列模拟样本; 伪随机序列样本的生成块; 求和节点，诸如输入第一序列和伪随机序列，在输出中获得包括非伪随机样本的模拟样本的第二序列; 转换器，其具有可控数字增益，接收第二序列并输出数字码的位; 具有环路增益并包括模拟放大器的反馈回路; 数字校准块，用于将数字增益与环路增益相匹配，并包括预测块，以从转换非伪随机采样得到的位开始产生所述输入信号的数字估计。

3. 发明授权

US08031579B2 Read/write transducer for a ferroelectric storage medium, and corresponding storage device and method 有权
标题翻译：用于铁电存储介质的读/写换能器，以及相应的存储装置和方法
公开(公告)号：US08031579B2
公开(公告)日：2011-10-04
申请号：US12199207
申请日：2008-08-27
申请人： Giacomino Bollati , Alessandro Bosi , Giovanni Antonio Cesura
发明人： Giacomino Bollati , Alessandro Bosi , Giovanni Antonio Cesura
IPC分类号： G11B9/00
CPC分类号： B82Y10/00 , G11B5/86 , G11B9/02 , G11B9/1418 , G11B11/002
摘要： A transducer for a storage medium has a supporting element positioned over the storage medium with a first head configured to interact with the storage medium and a second head operatively connected to the first head to interact with the storage medium. The second head is carried by the supporting element in a position adjacent to the first head, and the first head and the second head are aligned in a scanning direction. The first head performs the reading of a data item stored in a portion of the storage medium, the reading entailing the deletion of the data item, and the second head performs the rewriting of the data item in the same portion of the storage medium.
摘要翻译：用于存储介质的换能器具有位于存储介质上的支撑元件，其中第一头配置成与存储介质相互作用，第二头与第一头可操作地连接以与存储介质相互作用。第二头部由支撑元件承载在与第一头部相邻的位置，第一头部和第二头部沿扫描方向排列。第一头执行存储在存储介质的一部分中的数据项的读取，读取需要删除数据项，并且第二头在存储介质的相同部分中执行数据项的重写。

4. 发明授权

US07671769B2 Multistage analog/digital converter and method for calibrating said converter 有权
标题翻译：多级模拟/数字转换器和校准所述转换器的方法
公开(公告)号：US07671769B2
公开(公告)日：2010-03-02
申请号：US12198709
申请日：2008-08-26
申请人： Giovanni Antonio Cesura , Roberto Giampiero Massolini
发明人： Giovanni Antonio Cesura , Roberto Giampiero Massolini
IPC分类号： H03M1/06
CPC分类号： H03M1/1061 , H03M1/1004 , H03M1/162 , H03M1/164 , H03M1/40 , H03M1/44
摘要： A multistage analog/digital converter for converting in multi-step cycles an input signal into respective digital codes, each cycle step resolving at least one bit of a respective digital code. The converter includes: a sampling circuit inputting the signal and outputting a first sequence of analog samples; a generation block of a pseudorandom sequence of samples; a summing node, such as to input the first sequence and the pseudorandom sequence, obtaining in output a second sequence of analog samples including non-pseudorandom samples; a converter having a controllable digital gain receiving the second sequence and outputting bits of the digital codes; a feedback loop with a loop gain and including an analog amplifier; a digital calibration block to match the digital gain to the loop gain and including a prediction block to produce a digital estimation of said input signal starting from the bits resulting from converting the non-pseudorandom samples.
摘要翻译：一种用于以多步循环将输入信号转换成相应数字代码的多级模拟/数字转换器，每个循环步骤分辨相应数字代码的至少一位。转换器包括：采样电路，输入信号并输出第一序列模拟样本; 伪随机序列样本的生成块; 求和节点，诸如输入第一序列和伪随机序列，在输出中获得包括非伪随机样本的模拟样本的第二序列; 转换器，其具有可控数字增益，接收第二序列并输出数字码的位; 具有环路增益并包括模拟放大器的反馈回路; 数字校准块，用于将数字增益与环路增益相匹配，并包括预测块，以从转换非伪随机采样得到的位开始产生所述输入信号的数字估计。

5. 发明授权

US07629909B1 Circuit for converting a voltage range of a logic signal 失效
标题翻译：用于转换逻辑信号的电压范围的电路
公开(公告)号：US07629909B1
公开(公告)日：2009-12-08
申请号：US11836628
申请日：2007-08-09
申请人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
发明人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
IPC分类号： H03M1/00
CPC分类号： H03K19/00361 , H03K17/162 , H03M1/742
摘要： In a circuit to convert a voltage range of a control signal, a first switch selectively couples, based on the control signal, an output node to a first reference voltage when the output node is to be in a first state. A second switch selectively establishes, based on the control signal, a second reference voltage when the output node is to be in a second state, the second state being a logical complement of the first state. A feedback control loop is coupled to the output node to maintain the second reference voltage in response to voltage fluctuation at the output node. The feedback control loop includes a current mirror and a transistor coupled to the current mirror. The transistor is controlled by feedback from the output node to modify a biasing current established by the current mirror to thereby counteract the voltage fluctuation.
摘要翻译：在转换控制信号的电压范围的电路中，当输出节点处于第一状态时，第一开关基于控制信号将输出节点选择性地耦合到第一参考电压。当输出节点处于第二状态时，第二开关基于控制信号选择性地建立第二参考电压，第二状态是第一状态的逻辑补码。反馈控制回路耦合到输出节点以响应于输出节点处的电压波动来维持第二参考电压。反馈控制回路包括电流镜和耦合到电流镜的晶体管。晶体管通过来自输出节点的反馈来控制，以修改由电流镜所建立的偏置电流，从而抵消电压波动。

6. 发明授权

US07609186B1 Circuit for converting a voltage range of a logic signal 失效
标题翻译：用于转换逻辑信号的电压范围的电路
公开(公告)号：US07609186B1
公开(公告)日：2009-10-27
申请号：US11836584
申请日：2007-08-09
申请人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
发明人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
IPC分类号： H03K19/094
CPC分类号： H03K19/018528
摘要： In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second transistor selectively discharges the output node toward a second reference voltage via a resistor when the output node is to transition from the first state to a second state, the second state being a logical complement of the first state. A source-follower circuit has a source follower output coupled to the output node and has a dynamic current source, the dynamic current source having a control input coupled to the resistor. A third transistor selectively couples the source follower output to the dynamic current source when the output node is to be in the second state.
摘要翻译：在将具有第一范围的第一逻辑信号转换成具有第二范围的第二逻辑信号的电路中，当输出节点处于第一状态时，第一晶体管选择性地将输出节点耦合到第一参考电压。当输出节点要从第一状态转变到第二状态时，第二晶体管通过电阻器选择性地将输出节点放电到第二参考电压，第二状态是第一状态的逻辑补码。源跟随器电路具有耦合到输出节点并具有动态电流源的源极跟随器输出，动态电流源具有耦合到电阻器的控制输入。当输出节点处于第二状态时，第三晶体管选择性地将源极跟随器输出耦合到动态电流源。

7. 发明授权

US07605608B1 Circuit for converting a voltage range of a logic signal 失效
标题翻译：用于转换逻辑信号的电压范围的电路
公开(公告)号：US07605608B1
公开(公告)日：2009-10-20
申请号：US11836571
申请日：2007-08-09
申请人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
发明人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
IPC分类号： H03K19/094
CPC分类号： H03K19/018521 , H03M1/742
摘要： In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second MOS transistor selectively discharges the output node toward a second reference voltage when the output node is to transition from the first state to a second state, the second state a logical complement of the first state. An output of a source-follower circuit, having a current source, is coupled to the output node. A third MOS transistor selectively couples the current source of the source-follower circuit to the second reference voltage when the output node is to be in the second state.
摘要翻译：在将具有第一范围的第一逻辑信号转换为具有第二范围的第二逻辑信号的电路中，当输出节点将处于该状态时，第一金属氧化物半导体（MOS）晶体管选择性地将输出节点耦合到第一参考电压第一个状态当输出节点从第一状态转变到第二状态时，第二MOS晶体管选择性地将输出节点放电到第二参考电压，第二状态是第一状态的逻辑补码。具有电流源的源跟随器电路的输出耦合到输出节点。当输出节点处于第二状态时，第三MOS晶体管将源极跟随器电路的电流源选择性地耦合到第二参考电压。

8. 发明申请

US20080316906A1 READ/WRITE TRANSDUCER FOR A FERROELECTRIC STORAGE MEDIUM, AND CORRESPONDING STORAGE DEVICE AND METHOD 有权
标题翻译：一种用于存储介质的读/写传感器，以及相应的存储设备和方法
公开(公告)号：US20080316906A1
公开(公告)日：2008-12-25
申请号：US12199207
申请日：2008-08-27
申请人： Giacomino Bollati , Alessandro Bosi , Giovanni Antonio Cesura
发明人： Giacomino Bollati , Alessandro Bosi , Giovanni Antonio Cesura
IPC分类号： G11B9/00
CPC分类号： B82Y10/00 , G11B5/86 , G11B9/02 , G11B9/1418 , G11B11/002
摘要： A transducer for a storage medium has a supporting element positioned over the storage medium with a first head configured to interact with the storage medium and a second head operatively connected to the first head to interact with the storage medium. The second head is carried by the supporting element in a position adjacent to the first head, and the first head and the second head are aligned in a scanning direction. The first head performs the reading of a data item stored in a portion of the storage medium, the reading entailing the deletion of the data item, and the second head performs the rewriting of the data item in the same portion of the storage medium.
摘要翻译：用于存储介质的换能器具有位于存储介质上的支撑元件，其中第一头配置成与存储介质相互作用，第二头与第一头可操作地连接以与存储介质相互作用。第二头部由支撑元件承载在与第一头部相邻的位置，第一头部和第二头部沿扫描方向排列。第一头执行存储在存储介质的一部分中的数据项的读取，读取需要删除数据项，并且第二头在存储介质的相同部分中执行数据项的重写。

9. 发明授权

US07595745B1 Circuit for converting a voltage range of a logic signal 有权
标题翻译：用于转换逻辑信号的电压范围的电路
公开(公告)号：US07595745B1
公开(公告)日：2009-09-29
申请号：US11836619
申请日：2007-08-09
申请人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
发明人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal
IPC分类号： H03M1/00
CPC分类号： H03K3/356113
摘要： In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a switch selectively couples an output node to a first reference voltage when the output node is to be in a first state based on the control signal. A source-follower circuit having a current source establishes a second reference voltage. A logic circuit coupled to the switch and the source-follower circuit and having a logic gate selectively discharges, in accordance with the control signal, the output node to the second reference voltage when the output node is to transition from the first state to a second state.
摘要翻译：在将具有第一范围的第一逻辑信号转换成具有第二范围的第二逻辑信号的电路中，当输出节点将基于控制的第一状态时，开关选择性地将输出节点耦合到第一参考电压信号。具有电流源的源极跟随器电路建立第二参考电压。耦合到开关和源极跟随器电路并且具有逻辑门的逻辑电路在输出节点要从第一状态转变到第二状态时，根据控制信号将输出节点选择性地放电到第二参考电压州。

10. 发明授权

US07511649B1 Circuit for converting a voltage range of a logic signal 有权
标题翻译：用于转换逻辑信号的电压范围的电路
公开(公告)号：US07511649B1
公开(公告)日：2009-03-31
申请号：US11846292
申请日：2007-08-28
申请人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal , Stefano Marchesi
发明人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal , Stefano Marchesi
IPC分类号： H03M1/66
CPC分类号： H03K17/6871 , H03K3/35613
摘要： In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second MOS transistor has a source coupled to the output node and a gate coupled to a bias voltage. A current source circuit selectively biases the second MOS transistor to act as part of a source-follower circuit when the output node is to be in a second state. Additionally, a memory circuit has an input coupled to the output node, and an output. The memory circuit is configured to temporarily store a Boolean value of the output node when the output node transitions from the first state to the second state. Further, a discharging circuit is coupled to the output node and a second reference voltage. The discharging circuit is configured to temporarily provide a discharging path between the output node and the second reference voltage when the output node is transitioning from the first state to the second state. The discharging circuit has a first input coupled to the output of the memory circuit and a second input coupled to a control signal. The control signal indicates that the output node is to transition from the first state to the second state.
摘要翻译：在将具有第一范围的第一逻辑信号转换为具有第二范围的第二逻辑信号的电路中，当输出节点将处于该状态时，第一金属氧化物半导体（MOS）晶体管选择性地将输出节点耦合到第一参考电压第一个状态第二MOS晶体管具有耦合到输出节点的源极和耦合到偏置电压的栅极。当输出节点处于第二状态时，电流源电路选择性地偏压第二MOS晶体管，以充当源跟随器电路的一部分。另外，存储器电路具有耦合到输出节点的输入和输出。存储器电路被配置为当输出节点从第一状态转换到第二状态时临时存储输出节点的布尔值。此外，放电电路耦合到输出节点和第二参考电压。放电电路被配置为当输出节点从第一状态转变到第二状态时临时提供输出节点与第二参考电压之间的放电路径。放电电路具有耦合到存储器电路的输出的第一输入和耦合到控制信号的第二输入。控制信号表示输出节点要从第一状态转换到第二状态。

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