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    • 2. 发明授权
    • Programmable I/O cell capable of holding its state in power-down mode
    • 可编程I / O单元能够在掉电模式下保持其状态
    • US08041975B2
    • 2011-10-18
    • US12120015
    • 2008-05-13
    • Biranchinath SahuDouglas F. PastorelloGolam R. Chowdhury
    • Biranchinath SahuDouglas F. PastorelloGolam R. Chowdhury
    • G06F1/26
    • H03K3/0375H03K3/356147H03K19/0008
    • The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell. The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state.
    • 本发明包括一个微控制器单元,其包括用于产生掉电信号的处理器。 控制逻辑响应于掉电信号产生保持信号。 电压调节器响应于输入电压提供调节电压,并响应于掉电信号而断电。 响应于稳压器进入断电状态,由调节电压供电的至少一个数字设备进入断电模式。 所述至少一个数字设备提供提供给输入/输出单元的至少一个数字输出信号。 输入/输出单元也被连接以接收保持信号。 当至少一个数字设备进入掉电状态时,输入/输出单元响应于保持信号维持数字输出信号的最后状态。
    • 4. 发明授权
    • Programmable I/O cell capable of holding its state in power-down mode
    • 可编程I / O单元能够在掉电模式下保持其状态
    • US07373533B2
    • 2008-05-13
    • US11241277
    • 2005-09-30
    • Biranchinath SahuDouglas F. PastorelloGolam R. Chowdhury
    • Biranchinath SahuDouglas F. PastorelloGolam R. Chowdhury
    • G06F1/26
    • H03K3/0375H03K3/356147H03K19/0008
    • The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell. The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state.
    • 本发明包括一个微控制器单元,其包括用于产生掉电信号的处理器。 控制逻辑响应于掉电信号产生保持信号。 电压调节器响应于输入电压提供调节电压,并响应于掉电信号而断电。 响应于稳压器进入断电状态,由调节电压供电的至少一个数字设备进入断电模式。 所述至少一个数字设备提供提供给输入/输出单元的至少一个数字输出信号。 输入/输出单元也被连接以接收保持信号。 当至少一个数字设备进入掉电状态时,输入/输出单元响应于保持信号维持数字输出信号的最后状态。
    • 8. 发明申请
    • Programmable I/O cell capable of holding its state in power-down mode
    • 可编程I / O单元能够在掉电模式下保持其状态
    • US20070079149A1
    • 2007-04-05
    • US11241277
    • 2005-09-30
    • Biranchinath SahuDouglas PastorelloGolam Chowdhury
    • Biranchinath SahuDouglas PastorelloGolam Chowdhury
    • G06F1/26
    • H03K3/0375H03K3/356147H03K19/0008
    • The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell. The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state.
    • 本发明包括一个微控制器单元,其包括用于产生掉电信号的处理器。 控制逻辑响应于掉电信号产生保持信号。 电压调节器响应于输入电压提供调节电压,并响应于掉电信号而断电。 响应于稳压器进入断电状态,由调节电压供电的至少一个数字设备进入断电模式。 所述至少一个数字设备提供提供给输入/输出单元的至少一个数字输出信号。 输入/输出单元也被连接以接收保持信号。 当至少一个数字设备进入掉电状态时,输入/输出单元响应于保持信号维持数字输出信号的最后状态。
    • 10. 发明申请
    • CIRCUITS AND METHODS FOR CONTROLLING PWM INPUT OF DRIVER CIRCUIT
    • 用于控制驱动电路PWM输入的电路和方法
    • US20130063114A1
    • 2013-03-14
    • US13232720
    • 2011-09-14
    • Jitendra Kumar AgrawalBiranchinath Sahu
    • Jitendra Kumar AgrawalBiranchinath Sahu
    • G05F1/618
    • H02M3/1588H02M1/38Y02B70/1466
    • Circuits and methods for controlling Pulse Width Modulation (PWM) input of a driver circuit during transition of states are provided. The driver circuit is operative in one of a high state, a low state and a tri-state based on the PWM input. The method includes receiving a tri-state command for transition from the high state to the tri-state. A PWM output signal is enabled to transition from a high logic value to a low logic value for driving the driver circuit from the high state to the low state upon receipt of the tri-state command. The PWM output signal is enabled to transition from the low logic value to a tri-state logic value for driving the driver circuit from the low state to the tri-state upon elapse of a threshold time delay. The PWM input to the driver circuit is based on the PWM output signal.
    • 提供了在状态转换期间控制驱动电路的脉宽调制(PWM)输入的电路和方法。 基于PWM输入,驱动电路工作在高状态,低状态和三态之一。 该方法包括接收用于从高状态转换到三态的三态命令。 PWM输出信号使能从高逻辑值转换到低逻辑值,用于在接收到三态命令时将驱动电路从高状态驱动到低电平状态。 PWM输出信号使能从低逻辑值转换到三态逻辑值,用于在经过阈值时间延迟时将驱动电路从低状态驱动到三态。 驱动电路的PWM输入基于PWM输出信号。