会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明申请
    • PROGRAMMABLE I/O CELL CAPABLE OF HOLDING ITS STATE IN POWER-DOWN MODE
    • 可编程I / O单元,可在掉电模式下保持状态
    • US20080246526A1
    • 2008-10-09
    • US12120015
    • 2008-05-13
    • BIRANCHINATH SAHUDOUGLAS F. PASTORELLOGOLAM R. CHOWDHURY
    • BIRANCHINATH SAHUDOUGLAS F. PASTORELLOGOLAM R. CHOWDHURY
    • H03K3/02
    • H03K3/0375H03K3/356147H03K19/0008
    • The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell. The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state.
    • 本发明包括一个微控制器单元,其包括用于产生掉电信号的处理器。 控制逻辑响应于掉电信号产生保持信号。 电压调节器响应于输入电压提供调节电压,并响应于掉电信号而断电。 响应于稳压器进入断电状态,由调节电压供电的至少一个数字设备进入断电模式。 所述至少一个数字设备提供提供给输入/输出单元的至少一个数字输出信号。 输入/输出单元也被连接以接收保持信号。 当至少一个数字设备进入掉电状态时,输入/输出单元响应于保持信号维持数字输出信号的最后状态。
    • 2. 发明授权
    • Method for search and matching of capacitors for a digital to analog converter of an SAR analog to digital converter
    • SAR模数转换器的数模转换器的电容搜索和匹配方法
    • US07199746B1
    • 2007-04-03
    • US11311508
    • 2005-12-19
    • Golam R. ChowdhuryDouglas Piasecki
    • Golam R. ChowdhuryDouglas Piasecki
    • H03M1/12
    • H03M1/468H03M1/0673H03M1/682
    • The method is described for selecting capacitors from a capacitor array for each bit of a SAR ADC. The process involves selecting a group of capacitors from the capacitor array and determining a weight of the selected group of capacitors. A determination is made if the weights of the selected group of capacitors are substantially equal to their desired values. If the weights are substantially equal to their desired values, the selected group of capacitors is associated with each bit of the SAR ADC. If the weights are not substantially equal to their desired values, a next group of capacitors from the capacitor array is selected for the bits. This process of selecting a group of capacitors and determining their weights is repeated until determined weight for a group of capacitors equals or is closest to the desired values.
    • 描述了用于从SAR ADC的每个位的电容器阵列中选择电容器的方法。 该过程涉及从电容器阵列中选择一组电容器并确定所选择的电容器组的重量。 如果所选择的电容组的权重基本上等于其所需的值,则确定。 如果权重基本上等于其所需值,则所选择的电容组与SAR ADC的每个位相关联。 如果权重基本上不等于其所需值,则选择来自电容器阵列的下一组电容器用于该位。 重复选择一组电容器并确定它们的权重的该过程,直到一组电容器的确定的重量等于或最接近所需值。
    • 4. 发明授权
    • Programmable I/O cell capable of holding its state in power-down mode
    • 可编程I / O单元能够在掉电模式下保持其状态
    • US07373533B2
    • 2008-05-13
    • US11241277
    • 2005-09-30
    • Biranchinath SahuDouglas F. PastorelloGolam R. Chowdhury
    • Biranchinath SahuDouglas F. PastorelloGolam R. Chowdhury
    • G06F1/26
    • H03K3/0375H03K3/356147H03K19/0008
    • The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell. The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state.
    • 本发明包括一个微控制器单元,其包括用于产生掉电信号的处理器。 控制逻辑响应于掉电信号产生保持信号。 电压调节器响应于输入电压提供调节电压,并响应于掉电信号而断电。 响应于稳压器进入断电状态,由调节电压供电的至少一个数字设备进入断电模式。 所述至少一个数字设备提供提供给输入/输出单元的至少一个数字输出信号。 输入/输出单元也被连接以接收保持信号。 当至少一个数字设备进入掉电状态时,输入/输出单元响应于保持信号维持数字输出信号的最后状态。
    • 7. 发明授权
    • Programmable I/O cell capable of holding its state in power-down mode
    • 可编程I / O单元能够在掉电模式下保持其状态
    • US08041975B2
    • 2011-10-18
    • US12120015
    • 2008-05-13
    • Biranchinath SahuDouglas F. PastorelloGolam R. Chowdhury
    • Biranchinath SahuDouglas F. PastorelloGolam R. Chowdhury
    • G06F1/26
    • H03K3/0375H03K3/356147H03K19/0008
    • The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell. The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state.
    • 本发明包括一个微控制器单元,其包括用于产生掉电信号的处理器。 控制逻辑响应于掉电信号产生保持信号。 电压调节器响应于输入电压提供调节电压,并响应于掉电信号而断电。 响应于稳压器进入断电状态,由调节电压供电的至少一个数字设备进入断电模式。 所述至少一个数字设备提供提供给输入/输出单元的至少一个数字输出信号。 输入/输出单元也被连接以接收保持信号。 当至少一个数字设备进入掉电状态时,输入/输出单元响应于保持信号维持数字输出信号的最后状态。