专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 外观设计

USD939140S1 Hair clip 有权
公开(公告)号：USD939140S1
公开(公告)日：2021-12-21
申请号：US29760129
申请日：2020-11-30
申请人： Hao Luo
设计人： Hao Luo

2. 发明申请

US20160131481A1 MEMS INERTIAL SENSING USING ACOUSTIC WAVES 审中-公开
标题翻译：使用声波的MEMS惯性感测
公开(公告)号：US20160131481A1
公开(公告)日：2016-05-12
申请号：US14934669
申请日：2015-11-06
申请人： Hao Luo
发明人： Hao Luo
IPC分类号： G01C19/5698
CPC分类号： G01C19/5698 , G01P15/08
摘要： A MEMS structure includes a generating diaphragm, one or more wave channels, and one or more sensing diaphragm. A method for inertial sensing comprises driving the generating diaphragm to generate an acoustic wave, passing the acoustic wave through a channel in the MEMS structure to the sensing diaphragm, and measuring a relative phase of the wave at the sensing diaphragm to determine acceleration or rotation of the MEMS structure.
摘要翻译： MEMS结构包括生成膜片，一个或多个波通道以及一个或多个感测膜片。用于惯性感测的方法包括驱动发生膜片以产生声波，使声波通过MEMS结构中的通道传递到感测膜片，并测量感测膜片上的波的相对相位，以确定加速度或旋转速度 MEMS结构。

3. 发明申请

US20150242217A1 SYSTEM AND METHOD TO QUANTIFY DIGITAL DATA SHARING IN A MULTI-THREADED EXECUTION 有权
标题翻译：在多线程执行中定量数据共享的系统和方法
公开(公告)号：US20150242217A1
公开(公告)日：2015-08-27
申请号：US14613066
申请日：2015-02-03
申请人： Chen Ding , Hao Luo
发明人： Chen Ding , Hao Luo
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3863 , G06F9/3001 , G06F9/30047 , G06F11/3404 , G06F11/3452 , G06F2201/865 , G06F2201/88 , G06F2201/885
摘要： A method to quantify a plurality of digital data sharing in a multi-threaded execution includes the steps of: providing at least one processor; providing a computer readable non-transitory storage medium including a computer readable multi-threaded executable code and a computer readable executable code to calculate a plurality of shared footprint values and an average shared footprint value; running the multi-threaded executable code on the at least one computer processor; running the computer readable executable code configured to calculate a plurality of shared footprint values and an average shared footprint value; calculating a plurality of shared footprint values by use of a linear-time process for a corresponding plurality of executable windows in time; and calculating and saving an average shared footprint value based on the plurality of shared footprint values to quantify by a metric the data sharing by the multi-threaded execution. A system to perform the method is also described.
摘要翻译：一种在多线程执行中量化多个数字数据共享的方法包括以下步骤：提供至少一个处理器; 提供包括计算机可读多线程可执行代码和计算机可读可执行代码的计算机可读非暂存存储介质，以计算多个共享足迹值和平均共享足迹值; 在所述至少一个计算机处理器上运行所述多线程可执行代码; 运行被配置为计算多个共享足迹值和平均共享足迹值的计算机可读可执行代码; 通过对时间上相应的多个可执行窗口的线性时间过程来计算多个共享足迹值; 以及基于所述多个共享足迹值来计算和保存平均共享足迹值，以通过所述多线程执行的度量来量化数据共享。还描述了执行该方法的系统。

4. 发明授权

US09085591B2 Organosilicon amine electrolyte materials containing polyether chain and application thereof in electrolytes of lithium-ion batteries 有权
标题翻译：含有聚醚链的有机硅胺电解质材料及其在锂离子电池电解质中的应用
公开(公告)号：US09085591B2
公开(公告)日：2015-07-21
申请号：US13702576
申请日：2011-03-10
申请人： Lingzhi Zhang , Hao Luo , Xinyue Zhao
发明人： Lingzhi Zhang , Hao Luo , Xinyue Zhao
IPC分类号： C07F7/18 , C07F7/10 , H01M10/056 , C07F7/08 , H01M10/0565 , H01M10/0525 , H01M10/0567 , H01G11/62
CPC分类号： C07F7/1804 , C07F7/081 , C07F7/0838 , C07F7/10 , H01G11/62 , H01M10/0525 , H01M10/056 , H01M10/0565 , H01M10/0567 , Y02E60/122 , Y02E60/13
摘要： The invention provides an organosilicon amine electrolyte material containing a polyether chain, which has a wide range of applications, as well as an application of the electrolyte material in a lithium ion battery. The chemical structure thereof is as shown in Formula 1, wherein R1 and R2 are selected from the same or different C1-C10 alkyls; A is a polyether chain segment having the structure of (CH2)nO[(CH2)mO]x(CH2)y, where n and m are integers from 0 to 10, and x is an integer from 1 to 10; R3, R4 and R5 are selected from the same or the different C1-C10 alkyls or alkoxyl groups, or are equivalent to ANR1R2 or —O—SiR6R7R8 in structure; wherein R6, R7 and R8 are C1-C10 alkyls.
摘要翻译：本发明提供一种含有聚醚链的有机硅胺电解质材料，其具有广泛的应用范围，以及在锂离子电池中应用电解质材料。其化学结构如式1所示，其中R 1和R 2选自相同或不同的C 1 -C 10烷基; A是具有（CH 2）n O [（CH 2）m O] x（CH 2）y结构的聚醚链段，其中n和m是0至10的整数，x是1至10的整数; R3，R4和R5选自相同或不同的C1-C10烷基或烷氧基，或相当于结构中的ANR1R2或-O-SiR6R7R8; 其中R6，R7和R8是C1-C10烷基。

5. 发明授权

US09010184B2 MEMS devices sensing both rotation and acceleration 有权
标题翻译： MEMS器件感应旋转和加速
公开(公告)号：US09010184B2
公开(公告)日：2015-04-21
申请号：US13141282
申请日：2011-05-23
申请人： Bo Zou , Hao Luo
发明人： Bo Zou , Hao Luo
IPC分类号： G01C19/00 , G01P15/125 , G01P15/18 , G01P15/14 , G01C19/5762
CPC分类号： G01P15/125 , G01C19/5762 , G01P15/14 , G01P15/18
摘要： A MEMS device comprises a proof mass suspended above a substrate, one or more driving combs, and one or more sensing combs. During operation, a DC actuating potential in series with an AC modulation potential is applied to the proof mass, and an AC actuating potential is applied to the one or more driving combs such that the proof mass moves in an oscillatory manner. An inertial sensing system further comprises a sensing element configured to detect a rotation information coupled with an AC signal and an acceleration information coupled with a DC signal.
摘要翻译： MEMS器件包括悬浮在衬底上的校准块，一个或多个驱动梳和一个或多个感测梳。在操作期间，将与AC调制电位串联的DC致动电位施加到检测质量块，并且将AC致动电位施加到一个或多个驱动梳，使得校准质量块以振荡方式移动。惯性感测系统还包括感测元件，其被配置为检测与AC信号耦合的旋转信息和与DC信号耦合的加速度信息。

6. 发明申请

US20100321094A1 METHOD AND CIRCUIT IMPLEMENTATION FOR REDUCING THE PARAMETER FLUCTUATIONS IN INTEGRATED CIRCUITS 审中-公开
标题翻译：降低集成电路中参数波动的方法与电路实现
公开(公告)号：US20100321094A1
公开(公告)日：2010-12-23
申请号：US12870833
申请日：2010-08-29
申请人： HAO LUO , Yan Han , Xiaoxia Han , Xiaopeng Liu
发明人： HAO LUO , Yan Han , Xiaoxia Han , Xiaopeng Liu
IPC分类号： H01L37/00 , G05F1/10
CPC分类号： G05F3/205 , H03F1/30 , H03F3/217 , H03M3/356 , H03M3/418
摘要： This invention provides a method for reducing the effects of process, supply voltage and temperature variations in integrated circuits and its circuit implementation. The disclosed method builds up a detecting-feedback loop with a plurality of target MOS transistors in main circuits, an induction MOS transistor and a current-to-voltage conversion circuit, and performs a body modulation to effectively reduce the parameter fluctuations of the target MOS transistors in a sub-threshold region or a saturated region due to process, supply voltage and temperature variations. A body-modulated circuit achieves the disclosed method with only a few circuit elements, which effectively improves the stability, reliability and product yield of integrated circuits, especially sub-threshold integrated circuits, without significantly increasing the circuit complexity and power consumption.
摘要翻译：本发明提供一种降低集成电路中工艺，电源电压和温度变化的影响及其电路实现的方法。所公开的方法在主电路中构建具有多个目标MOS晶体管的检测反馈回路，感应MOS晶体管和电流 - 电压转换电路，并且执行体调制以有效地减小目标MOS的参数波动由于过程，电源电压和温度变化导致的亚阈值区域或饱和区域中的晶体管。身体调制电路仅利用几个电路元件实现了所公开的方法，这有效地提高了集成电路，特别是亚阈值集成电路的稳定性，可靠性和产品产量，而不显着增加电路复杂性和功耗。

7. 发明申请

US20100167418A1 STABILIZED LOW AFFINITY CONFORMATION OF INTEGRINS FOR DRUG DISCOVERY 有权
标题翻译：稳定低浓度组合的药物发现
公开(公告)号：US20100167418A1
公开(公告)日：2010-07-01
申请号：US12645958
申请日：2009-12-23
申请人： Timothy A. Springer , Bing Hao Luo
发明人： Timothy A. Springer , Bing Hao Luo
IPC分类号： G01N33/53 , C07K14/00
CPC分类号： G01N33/5032 , C07K14/70546 , G01N33/566 , G01N33/6872 , G01N2333/70546 , G01N2333/70557 , G01N2500/04
摘要： The methods and compositions described herein are based, in part, on the discovery that the introduction of a disulfide bond into an integrin polypeptide by the substitution of at least one cysteine residue in the polypeptide permits stabilization of the integrin in a “closed/inactive” state. This stabilizing disulfide bond permits integrins to be screened for a candidate molecule that can bind to the closed state. In particular, this approach can be used to screen for agents that bind to the closed state of an integrin polypeptide, and are useful as therapeutic treatments to prevent integrin activation.
摘要翻译：本文描述的方法和组合物部分地基于以下发现：通过取代多肽中的至少一个半胱氨酸残基将二硫键引入整联蛋白多肽，可使整联蛋白稳定在“闭合/不活动” 州。这种稳定的二硫键允许整合素筛选可以结合到封闭状态的候选分子。特别地，该方法可用于筛选结合整联蛋白多肽的闭合状态的试剂，并且可用作防止整联蛋白活化的治疗性处理。

8. 发明申请

US20080100559A1 Integrated line selection apparatus within active matrix arrays 失效
标题翻译：有源矩阵阵列内集成选线装置
公开(公告)号：US20080100559A1
公开(公告)日：2008-05-01
申请号：US11590339
申请日：2006-10-30
申请人： Warren Jackson , Carl Taussig , Hao Luo
发明人： Warren Jackson , Carl Taussig , Hao Luo
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G3/3266 , G09G3/3275 , G09G3/3688 , G09G2300/0408 , G09G2310/0254 , G09G2310/0267 , G09G2310/0275 , G09G2310/0297 , G09G2320/043 , G09G2330/08
摘要： An integrated line selection apparatus within active matrix arrays is described. The circuit includes multiple gate line drive transistor devices, each gate line drive transistor device having a drain coupled to a gate line of multiple gate lines in a gate line driver circuit coupled to an active matrix array and a source to receive an input signal. The circuit further includes at least one address line transistor device corresponding to each gate line transistor device, each address line transistor device having a drain coupled to a gate of the corresponding gate line drive transistor device and a gate coupled to a corresponding address line, such that by asserting a predetermined combination of voltages on the plurality of address lines, a single gate line of said plurality of gate lines is selected to receive the input signal to be transmitted to a corresponding pixel within the corresponding active matrix array.
摘要翻译：描述了有源矩阵阵列内的集成线选择装置。该电路包括多个栅极线驱动晶体管器件，每个栅极线驱动晶体管器件具有耦合到耦合到有源矩阵阵列的栅极线驱动器电路中的多个栅极线的栅极线的漏极和用于接收输入信号的源极。该电路还包括对应于每个栅极线晶体管器件的至少一个地址线晶体管器件，每个地址线晶体管器件具有耦合到相应的栅极线驱动晶体管器件的栅极的漏极和耦合到相应的地址线的栅极，通过在多个地址线上确定电压的预定组合，选择所述多条栅极线的单个栅极线以接收要传输到相应的有源矩阵阵列内的对应像素的输入信号。

9. 发明申请

US20060018143A1 Logical arrangement of memory arrays 有权
公开(公告)号：US20060018143A1
公开(公告)日：2006-01-26
申请号：US10896163
申请日：2004-07-21
申请人： Carl Taussig , Richard Elder , Hao Luo
发明人： Carl Taussig , Richard Elder , Hao Luo
IPC分类号： G11C5/02
CPC分类号： G11C5/063
摘要： An aspect of the present invention is a logical arrangement of memory arrays. The logical arrangement includes a plurality of memory arrays deposed in a row-column configuration, a controller coupled to the plurality of memory arrays and at least one power line, at least one sense line and at least one address line coupled to the controller wherein a number of connections from the controller to the at least one power line, the at least one sense line and the at least one address line is minimized.

10. 发明授权

US09630834B2 Wafer scale monolithic CMOS-integration of free- and non-free-standing Metal- and Metal alloy-based MEMS structures in a sealed cavity 有权
公开(公告)号：US09630834B2
公开(公告)日：2017-04-25
申请号：US14306139
申请日：2014-06-16
申请人： Noureddine Tayebi , Hao Luo
发明人： Noureddine Tayebi , Hao Luo
IPC分类号： B81C1/00 , B81B7/02
CPC分类号： B81C1/0023 , B81B7/02 , B81C1/00246 , H01L2224/05014
摘要： An assembly of metallic MEMS structures directly fabricated on planarized CMOS substrates, containing the application-specific integrated circuit (ASIC), by direct deposition and subsequent microfabrication steps on the ASIC interconnect layers, with integrated capping for packaging, is provided. The MEMS structures comprise at least one MEMS device element, with or without moveable parts anchored on the CMOS ASIC wafer with electrical contact provided via the metallic interconnects of the ASIC. The MEMS structures can also be made of metallic alloys, conductive oxides and amorphous semiconductors. The integrated capping, which provides a sealed cavity, is accomplished through bonding pads defined in the post-processing of the CMOS substrate.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式