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1. 发明公开

US20240235554A9 TERNARY LOGIC ELEMENT AND TERNARY LOGIC SYSTEM INCLUDING SAME 审中-公开
公开(公告)号：US20240235554A9
公开(公告)日：2024-07-11
申请号：US18366119
申请日：2023-08-07
申请人： KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
发明人： Yang Kyu CHOI , Joon Kyu HAN
IPC分类号： H03K19/082
CPC分类号： H03K19/0823
摘要： A ternary logic element including a transistor and a switching element. The transistor includes a channel layer including silicon, an input electrode, an output electrode, and a control electrode. The switching element includes an emitter, a base extending from the emitter, and a collector extending from the base. When a first control voltage is applied to the control electrode, the ternary logic element outputs a first voltage, and when a second control voltage different from the first control voltage is applied to the control electrode, the ternary logic element outputs a second voltage different from the first voltage, and when a third control voltage different from the first control voltage and the second control voltage is applied to the control electrode, the ternary logic element outputs a third voltage different from the first voltage and the second voltage.

2. 发明授权

US4454432A Power efficient TTL buffer for driving large capacitive loads 失效
标题翻译：高效TTL缓冲器，用于驱动大容性负载
公开(公告)号：US4454432A
公开(公告)日：1984-06-12
申请号：US300617
申请日：1981-09-09
申请人： Grady M. Wood
发明人： Grady M. Wood
IPC分类号： H03K19/00 , H03K19/018 , H03K19/082 , H03K19/088 , H03K19/013
CPC分类号： H03K19/001 , H03K19/01806 , H03K19/0823
摘要： A TTL gate for driving large capacitive loads with minimal current drain of the gate's power supply during the logic low output level is provided. The current drain from the power supply is minimized by a feedback means which becomes active when the logic low output level is reached. The feedback means comprises a current mirror circuit connected between the drive means and the output means of the gate. The drive means also comprises a current mirror circuit.
摘要翻译：提供了一个TTL门，用于在逻辑低输出电平下驱动大容量负载，栅极电源的电流消耗最小。通过反馈装置将来自电源的电流消耗最小化，当达到逻辑低输出电平时，反馈装置变为有效。反馈装置包括连接在驱动装置和门的输出装置之间的电流镜电路。驱动装置还包括电流镜电路。

3. 发明授权

US3253158A Multistable circuits employing plurality of predetermined-threshold circuit means 失效
标题翻译：采用多个预定阈值电路装置的多电路电路
公开(公告)号：US3253158A
公开(公告)日：1966-05-24
申请号：US27773963
申请日：1963-05-03
申请人： IBM
发明人： HORGAN THOMAS B
IPC分类号： H03K3/26 , H03K3/29 , H03K19/082
CPC分类号： H03K3/26 , H03K3/29 , H03K19/0823

4. 发明授权

US3242348A Circuit arrangement for producing potentials having equal absolute values but opposite sign depending on received signal combinations 失效
标题翻译：用于根据接收到的信号组合产生具有相等绝对值但相反符号的电位的电路装置
公开(公告)号：US3242348A
公开(公告)日：1966-03-22
申请号：US13321361
申请日：1961-08-22
申请人： ERICSSON TELEFON AB L M
发明人： GEORGE SEM-SANDBERG SVERRE , PER-ARNE MANNBY
IPC分类号： H03K19/082 , H03M1/00
CPC分类号： H03K19/0823 , H03M1/785

5. 发明授权

US3213294A Signal level discriminator circuit with zener diode interrogated by bipolar pulses and biased by ternary input 失效
标题翻译：信号电平鉴相器电路采用双极性脉冲询问的齐纳二极管，并被三进制输入偏置
公开(公告)号：US3213294A
公开(公告)日：1965-10-19
申请号：US16651762
申请日：1962-01-16
申请人： NIPPON ELECTRIC CO
发明人： JIRO OKUDA
IPC分类号： H03K19/082 , H04Q3/00
CPC分类号： H03K19/0823 , H04Q3/0004

6. 发明授权

US4706299A Frequency encoded logic devices 失效
标题翻译：频率编码逻辑器件
公开(公告)号：US4706299A
公开(公告)日：1987-11-10
申请号：US610592
申请日：1984-05-15
申请人： Peter O. Jorgensen
发明人： Peter O. Jorgensen
IPC分类号： G06E1/04 , G06F7/49 , G11C19/34 , H03K19/082 , H04B9/00
CPC分类号： H03K19/0823 , G06E1/04 , G06F7/49 , G11C19/34
摘要： Logic devices for frequency encoded trinary logic signals are simulated by standard binary circuits. The binary circuits include frequency sensing and frequency selecting devices at the inputs and outputs thereof for decoding the frequency encoded trinary logic signals to binary level logic signals and for frequency encoding the resulting binary output to trinary logic signals. Optical encoding using the three primary light frequencies provides a convenient trinary signal format for the frequency encoded signals. A latch register, a shift register, a half adder and full series and parallel adder circuits are disclosed.
摘要翻译：用于频率编码的三态逻辑信号的逻辑器件由标准二进制电路进行仿真。二进制电路包括其输入和输出处的频率感测和频率选择装置，用于将频率编码的三进制逻辑信号解码为二进制电平逻辑信号，并将所得到的二进制输出频率编码为三进制逻辑信号。使用三个主要光频率的光学编码为频率编码信号提供了一种方便的三态信号格式。公开了一种锁存寄存器，移位寄存器，半加法器和全串并联加法器电路。

7. 发明授权

US4280065A Tri-state type driver circuit 失效
标题翻译：三态驱动电路
公开(公告)号：US4280065A
公开(公告)日：1981-07-21
申请号：US969269
申请日：1978-12-14
申请人： Osamu Minato , Toshiaki Masuhara , Toshio Sasaki , Masaharu Kubo
发明人： Osamu Minato , Toshiaki Masuhara , Toshio Sasaki , Masaharu Kubo
IPC分类号： H03K19/0175 , H03K5/02 , H03K19/082 , H03K19/094 , H03K19/0944 , H03K19/0948 , H03K3/01 , H03K19/08
CPC分类号： H03K19/09429 , H03K19/0823 , H03K19/09448 , H03K5/023
摘要： This invention relates to a tri-state type driver circuit in which any one of the three possible output signals of "float", "on", or "off" is produced at high speed even when an output terminal is accompanied with a great load. The tri-state type driver circuit comprises an output inverter circuit which employs a bipolar transistor as a load thereof and a MOS-FET as a driver thereof, a first logical circuit which is coupled to an input terminal of the bipolar transistor, which first logical circuit is made up of a C-MOS circuit receiving an external select signal and a C-MOS circuit having an input signal transmitted thereto and whose output can be specified by the external select signal, and a second logical circuit which is coupled to an input terminal of the MOS-FET, which second logical circuit is made up of a C-MOS circuit receiving the external select signal and a C-MOS circuit having the input signal transmitted thereto. The state of the external select signal will determine whether the driver circuit output will be "float" (regardless of the input to the driver circuit) or "on" or "off" (in correspondence with the input to the driver circuit).
摘要翻译：本发明涉及一种三态型驱动电路，其中即使输出端子伴随着大的负载，也可以高速度地产生“浮动”，“接通”或“断开”的三个可能的输出信号中的任何一个。三态型驱动器电路包括采用双极晶体管作为其负载的输出反相器电路和作为其驱动器的MOS-FET，耦合到双极晶体管的输入端的第一逻辑电路，第一逻辑电路由接收外部选择信号的C-MOS电路和具有传输的输入信号的C-MOS电路组成，其输出可由外部选择信号指定，第二逻辑电路耦合到输入端 MOS-FET的端子，该第二逻辑电路由接收外部选择信号的C-MOS电路和传输了该输入信号的C-MOS电路组成。外部选择信号的状态将决定驱动器电路输出是否为“浮动”（不管驱动电路的输入）还是“开”或“关”（与驱动电路的输入相对应）。

8. 发明授权

US3155845A Three level converter 失效
标题翻译：三电平转换器
公开(公告)号：US3155845A
公开(公告)日：1964-11-03
申请号：US16332361
申请日：1961-12-29
申请人： IBM
发明人： GRUODIS ALGIRDAS J , LANGE LAWRENCE K , MCANNEY WILLIAM H
IPC分类号： H03K3/2893 , H03K19/082 , H03M5/18
CPC分类号： H03K3/2893 , H03K19/0823 , H03M5/18

9. 发明授权

US3099753A Three level logical circuits 失效
标题翻译：三级逻辑电路
公开(公告)号：US3099753A
公开(公告)日：1963-07-30
申请号：US2228960
申请日：1960-04-14
申请人： IBM
发明人： SCHMOOKLER MARTIN S
IPC分类号： G06F7/50 , G06F7/502 , H03K19/00 , H03K19/08 , H03K19/082 , H03K19/086
CPC分类号： G06F7/502 , H03K19/0002 , H03K19/08 , H03K19/0823 , H03K19/086

10. 发明授权

US3005112A Direct coupled transistor logic using commoned emitters and complementary logic blocks 失效
标题翻译：直接耦合晶体管逻辑使用共用发射极和互补逻辑块
公开(公告)号：US3005112A
公开(公告)日：1961-10-17
申请号：US2723560
申请日：1960-04-14
申请人： IBM
发明人： MEADE ROBERT M
IPC分类号： G06F7/50 , G06F7/501 , H03K19/082
CPC分类号： G06F7/501 , H03K19/0823

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