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1. 发明授权

US08502198B2 Switching device and methods for controlling electron tunneling therein 有权
标题翻译：用于控制电子隧穿的开关装置和方法
公开(公告)号：US08502198B2
公开(公告)日：2013-08-06
申请号：US11414578
申请日：2006-04-28
申请人： R. Stanley Williams , Zhiyong Li , Douglas Ohlberg , Philip J. Kuekes , Duncan Stewart
发明人： R. Stanley Williams , Zhiyong Li , Douglas Ohlberg , Philip J. Kuekes , Duncan Stewart
IPC分类号： H01L29/08
CPC分类号： G11C13/02 , G11C13/0009 , G11C2213/77 , H01L51/0591
摘要： A switching device includes at least one bottom electrode and at least one top electrode. The top electrode crosses the bottom electrode at a non-zero angle, thereby forming a junction. A metal oxide layer is established on at least one of the bottom electrode or the top electrode. A molecular layer including a monolayer of organic molecules and a source of water molecules is established in the junction. Upon introduction of a forward bias, the molecular layer facilitates a redox reaction between the electrodes, thereby reducing a tunneling gap between the electrodes.
摘要翻译：开关装置包括至少一个底部电极和至少一个顶部电极。顶部电极以非零角度穿过底部电极，从而形成结。在底电极或顶电极中的至少一个上建立金属氧化物层。在连接处建立了包括有机分子单层和水分子源的分子层。在引入正向偏压时，分子层促进电极之间的氧化还原反应，从而减少电极之间的隧道间隙。

2. 发明授权

US08214786B2 Scalable, component-accessible, and highly interconnected three-dimensional component arrangement within a system 有权
标题翻译：系统内可扩展的，可组件访问的和高度互连的三维组件布置
公开(公告)号：US08214786B2
公开(公告)日：2012-07-03
申请号：US10935845
申请日：2004-09-08
申请人： Philip J. Kuekes , R. Stanley Williams , Raymond G. Beausoleil, Jr.
发明人： Philip J. Kuekes , R. Stanley Williams , Raymond G. Beausoleil, Jr.
IPC分类号： G06F17/50
CPC分类号： G06F1/18 , G06F17/509 , H05K7/1444
摘要： Embodiments of the present invention include dense, but accessible and well-interconnected component arrangements within multi-component systems, such as high-end multi-processor computer systems, and methods for constructing such arrangements. In a described embodiment, integrated-circuit-containing processing components, referred to as a “flat components,” are arranged into local blocks of intercommunicating flat components. The local flat-component blocks are arranged into interconnected, primitive multi-local-block repeating units, and the primitive local-block repeating units are layered together in a three-dimensional, regularly repeating structure that can be assembled to approximately fill any specified three-dimensional volume. The arrangement provides for relatively short, direct pathways from the surface of the specified volume to any particular local block and flat component within the three-dimensional arrangement.
摘要翻译：本发明的实施例包括在诸如高端多处理器计算机系统的多组件系统内的密集但可访问和良好互连的组件布置，以及用于构造这种布置的方法。在所描述的实施例中，被称为“平面部件”的集成电路的处理部件被布置在相互连通的平面部件的局部块中。本地平面组件块被布置成互连的原始多局部块重复单元，并且原始局部块重复单元以三维的规则重复的结构分层在一起，其可以被组装以大致填充任何指定的三维数。该装置提供从指定体积的表面到三维布置中的任何特定局部块和平坦部件的相对短的直接通路。

3. 发明申请

US20120105263A1 ANALOG TO DIGITAL CONVERTER 有权
标题翻译：模拟到数字转换器
公开(公告)号：US20120105263A1
公开(公告)日：2012-05-03
申请号：US12916376
申请日：2010-10-29
申请人： John Paul Strachan , Philip J. Kuekes
发明人： John Paul Strachan , Philip J. Kuekes
IPC分类号： H03M1/12 , H05K3/00 , H05K1/09
CPC分类号： H03M1/368 , Y10T29/49117
摘要： An analog to digital converter includes a dielectric substrate, an analog input wire, and digital output wires, with a metal insulator extending over the digital output wires. The analog input wire can be in proximity to the dielectric substrate and can generate heat when an electric current flows through the analog input wire. The digital output wires can also be in proximity to the dielectric substrate. The metal insulator can have a phase transition temperature above which the metal insulator is electrically conductive to short circuit at least one of the digital output wires in contact with a metal insulator portion above the phase transition temperature. The digital output wires can be arranged at predetermined distances from the analog input wire such that output wires have varying short circuit thresholds.
摘要翻译：模数转换器包括电介质基板，模拟输入线和数字输出线，金属绝缘体延伸在数字输出线上。模拟输入线可以靠近电介质基板，并且当电流流过模拟输入线时可以产生热量。数字输出线也可以靠近电介质基片。金属绝缘体可以具有相对转变温度，在该相转变温度以上，金属绝缘体导电以使与数字输出线中至少一个与相变温度以上的金属绝缘体部分接触的短路。数字输出线可以布置在距离模拟输入线的预定距离处，使得输出线具有变化的短路阈值。

4. 发明授权

US08149485B2 Dynamically reconfigurable holograms with electronically erasable programmable intermediate layers 有权
标题翻译：具有电子可擦除可编程中间层的动态可重构全息图
公开(公告)号：US08149485B2
公开(公告)日：2012-04-03
申请号：US12317731
申请日：2008-12-29
申请人： Jingjing Li , Philip J. Kuekes , Shih-Yuan Wang
发明人： Jingjing Li , Philip J. Kuekes , Shih-Yuan Wang
IPC分类号： G03H1/08 , G02B5/32 , G02F1/01
CPC分类号： G03H1/22 , G03H1/02 , G03H1/2294 , G03H2001/0224 , G03H2225/22 , G03H2225/32 , G03H2225/33 , G03H2225/60 , G03H2240/24 , Y10S977/762 , Y10S977/765
摘要： Dynamically reconfigurable holograms with electronically erasable programmable intermediate layers are disclosed. An example apparatus includes first nanowires, each of the first nanowires having protuberances along a length thereof. The example apparatus also includes second nanowires arranged approximately perpendicular to the first nanowires, the protuberances of the first nanowires being approximately parallel to corresponding ones of the second nanowires. In addition, a layer is disposed between the first and second nanowires. The layer is to control refractive indices at nanowire intersections at intersecting ones of the first and second nanowires.
摘要翻译：公开了具有电子可擦除可编程中间层的动态可重构全息图。示例性设备包括第一纳米线，第一纳米线中的每一个具有沿其长度的突起。示例性装置还包括大致垂直于第一纳米线布置的第二纳米线，第一纳米线的突起大致平行于第二纳米线中的相应纳米线。此外，在第一和第二纳米线之间设置一层。该层用于控制在第一和第二纳米线的相交处的纳米线交点处的折射率。

5. 发明授权

US08045253B2 Sub-diffraction-limited imaging systems and methods 有权
$Sub-diffraction-limited imaging systems and methods$
标题翻译：次衍射限制成像系统和方法
公开(公告)号：US08045253B2
公开(公告)日：2011-10-25
申请号：US12473402
申请日：2009-05-28
申请人： Jingjing Li , Philip J. Kuekes
发明人： Jingjing Li , Philip J. Kuekes
IPC分类号： G02F1/03 , G02F1/29 , G02B5/18
CPC分类号： G02B27/56 , G01D5/30 , G02F1/29 , G02F2202/027 , G02F2202/20 , G02F2202/30 , G02F2202/36
摘要： Various embodiments of the present invention are directed to systems and methods for obtaining images of objects with higher resolution than the diffraction limit. In one aspect, a method for collecting evanescent waves scattered from an object comprises electronically configuring a reconfigurable device to operate as a grating for one or more lattice periods using a computing device. Propagating waves scattered from the object pass through the reconfigurable device and a portion of evanescent waves scattered from the object are projected into the far field of the object. The method includes detecting propagating waves and detecting the portion of evanescent waves projected into the far field for each lattice period using an imaging system.
摘要翻译：本发明的各种实施例涉及用于获得具有比衍射极限更高分辨率的物体的图像的系统和方法。一方面，一种用于收集从物体散射的ev逝波的方法包括使用计算装置电子地配置可重构装置作为一个或多个晶格周期的光栅。从物体散射的传播波通过可重构装置，并且从物体散射的一部分ev逝波被投射到物体的远场中。该方法包括使用成像系统检测传播波并且检测投射到远场中的每个格周期的瞬逝波的部分。

6. 发明申请

US20110249322A1 Nanowire-based opto-electronic device 有权
标题翻译：基于纳米线的光电器件
公开(公告)号：US20110249322A1
公开(公告)日：2011-10-13
申请号：US11790446
申请日：2007-04-25
申请人： Shih-Yuan Wang , M. Saif Islam , Philip J. Kuekes , Nobuhiko Kobayashi
发明人： Shih-Yuan Wang , M. Saif Islam , Philip J. Kuekes , Nobuhiko Kobayashi
IPC分类号： H01S5/20 , H01L29/06
CPC分类号： H01S5/341 , B82Y20/00 , H01L31/035281 , H01L31/09 , H01L31/1025 , H01S5/021 , H01S5/125 , H01S5/3412 , H01S5/4031 , H01S5/5018 , H01S5/5072 , H01S2301/14 , Y02E10/50 , Y10S977/762
摘要： Nanowire-based opto-electronic devices including nanowire lasers, photodetectors and semiconductor optical amplifiers are disclosed. The devices include nanowires grown from single crystal and/or non-single surfaces. The semiconductor optical amplifiers include nanowire arrays that act as ballast lasers to amplify a signal carried by a signal waveguide. Embodiments of the nanowire lasers and photodetectors include horizontal and vertical nanowires that can provide different polarizations.
摘要翻译：公开了包括纳米线激光器，光电检测器和半导体光放大器的基于纳米线的光电器件。这些器件包括从单晶和/或非单一表面生长的纳米线。半导体光放大器包括用作镇流器激光器以放大由信号波导承载的信号的纳米线阵列。纳米线激光器和光电检测器的实施例包括可以提供不同偏振的水平和垂直的纳米线。

7. 发明申请

US20110248381A1 Multilayer Memristive Devices 有权
标题翻译：多层记忆装置
公开(公告)号：US20110248381A1
公开(公告)日：2011-10-13
申请号：US13130815
申请日：2009-01-20
申请人： William Tong , Nathaniel J. Quitoriano , Duncan Stewart , Philip J. Kuekes
发明人： William Tong , Nathaniel J. Quitoriano , Duncan Stewart , Philip J. Kuekes
IPC分类号： H01L29/86 , H01L21/02
CPC分类号： H01L21/26586 , H01L45/08 , H01L45/1233 , H01L45/14 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/165
摘要： A multilayer memristive device includes a first electrode (410); a second electrode (405); a first memristive region (430) and a second memristive region (435) which created by directional ion implantation of dopant ions (420, 425) and are interposed between the first electrode (410) and the second electrode (405); and mobile dopants (315) which move within the first memristive region (430) and the second memristive region (435) in response to an applied electrical field.
摘要翻译：多层回忆装置包括第一电极（410）; 第二电极（405）; 通过定向离子注入掺杂剂离子（420,425）而形成并且介于第一电极（410）和第二电极（405）之间的第一忆阻区（430）和第二忆阻区（435）。以及响应于施加的电场在第一忆阻区（430）和第二忆阻区（435）内移动的移动掺杂剂（315）。

8. 发明授权

US07989798B2 Fabricating arrays of metallic nanostructures 失效
标题翻译：制造金属纳米结构阵列
公开(公告)号：US07989798B2
公开(公告)日：2011-08-02
申请号：US12509689
申请日：2009-07-27
申请人： Philip J Kuekes , M. Saif Islam , Shih-Yuan Wang , Alexandre M. Bratkovski
发明人： Philip J Kuekes , M. Saif Islam , Shih-Yuan Wang , Alexandre M. Bratkovski
IPC分类号： H01L29/06
CPC分类号： G02B6/107 , B82Y30/00 , Y10S977/712 , Y10S977/762 , Y10T29/41
摘要： A patterned array of metallic nanostructures and fabrication thereof is described. A device comprises a patterned array of metallic columns vertically extending from a substrate. Each metallic column is formed by metallically coating one of an array of non-metallic nanowires catalytically grown from the substrate upon a predetermined lateral pattern of seed points placed thereon according to a nanoimprinting process. An apparatus for fabricating a patterned array of metallic nanostructures is also described.
摘要翻译：描述了金属纳米结构的图案阵列及其制造。一种器件包括从衬底垂直延伸的金属柱的图案化阵列。根据纳米压印方法，通过在其上放置的种子点的预定横向图案上，从衬底催化生长的非金属纳米线阵列之一金属地涂覆每个金属柱。还描述了用于制造金属纳米结构的图案化阵列的装置。

9. 发明授权

US07975068B2 System and method for self configuration of reconfigurable systems 有权
公开(公告)号：US07975068B2
公开(公告)日：2011-07-05
申请号：US11540480
申请日：2006-09-28
申请人： Michael S. Schlansker , Boon Seong Ang , Philip J. Kuekes
发明人： Michael S. Schlansker , Boon Seong Ang , Philip J. Kuekes
IPC分类号： G06F15/173
CPC分类号： G06F15/7867
摘要： The invention is a system and method for reconfigurable computers. The invention involves a plurality of reconfigurable component clusters (RCCs), each of which can change their respective configuration upon receiving a configuration command. The invention uses a reconfiguration network for distributing the configuration command to the RCCs, wherein the reconfiguration network comprises a plurality of cells, wherein each RCC is connected to a cell.

10. 发明授权

US07872502B2 Defect-and-failure-tolerant demultiplexer using series replication and error-control encoding 有权
标题翻译：使用序列复制和错误控制编码的缺陷和容错解复用器
公开(公告)号：US07872502B2
公开(公告)日：2011-01-18
申请号：US11484961
申请日：2006-07-12
申请人： Warren Robinett , Philip J. Kuekes , R. Stanley Williams
发明人： Warren Robinett , Philip J. Kuekes , R. Stanley Williams
IPC分类号： H03K19/094
CPC分类号： H03K19/007 , G06F11/1076 , H03K19/00315
摘要： One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers. This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates, each including a reversibly switchable interconnection between a number of address lines, or address-line-derived signal lines, and an output signal line. Each reversibly switchable interconnection includes one or more reversibly switchable elements. In certain demultiplexer embodiments, NMOS and/or PMOS transistors are employed as reversibly switchable elements. In the method that represents one embodiment of the present invention, two or more serially connected transistors are employed in each reversibly switchable interconnection, so that short defects in up to one less than the number of serially interconnected transistors does not lead to failure of the reversibly switchable interconnection. In addition, error-control-encoding techniques are used to introduce additional address-line-derived signal lines and additional switchable interconnections so that the demultiplexer may function even when a number of individual, switchable interconnections are open-defective.
摘要翻译：本发明的一个实施例是一种用于构建缺陷和容错解复用器的方法。该方法适用于纳米尺度，微米级或更大规模的解复用器电路。解复用器电路可以被视为一组与门，每个与门包括多个地址线或地址线导出的信号线之间的可逆切换互连以及输出信号线。每个可逆切换互连包括一个或多个可逆切换元件。在某些解复用器实施例中，NMOS和/或PMOS晶体管被用作可逆切换元件。在表示本发明的一个实施例的方法中，在每个可逆切换互连中使用两个或更多个串联连接的晶体管，使得比串联互连晶体管的数量少一个的短缺陷不会导致可逆地失效可切换互连。此外，误差控制编码技术用于引入附加的地址线导出的信号线和附加的可切换互连，使得即使当多个单独的可切换互连是开放缺陷时，解复用器也可以起作用。

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